Table of Contents Abstract ............................................................................................................................................ 3

I. Introduction .............................................................................................................................. 3

II. First Proposed Design Topology ................................................................................................ 4

III. Design Procedure ..................................................................................................................... 4

1. First Step .................................................................................................................................. 5

2. Second Step .............................................................................................................................. 5

3. Third Step .................................................................................................................................. 5

4. Fourth Step ............................................................................................................................... 5

5. Fifth Step ................................................................................................................................... 6

6. Sixth Step .................................................................................................................................. 6

7. Seventh Step ............................................................................................................................. 7

8. Last Step.................................................................................................................................... 7

9. Biasing Circuit............................................................................................................................ 7

10. Elimination of RHP Zero............................................................................................................ 8

11. Nulling Resistor Rz Calculation .................................................................................................. 9

IV. Simulation Results .................................................................................................................. 10

1. Initial Results .......................................................................................................................... 10

2. Optimized Design .................................................................................................................... 10

3. Optimized Design with Nulling NMOS ..................................................................................... 12

4. Results After Optimization ...................................................................................................... 12

a. AC Response Plots ................................................................................................................... 13

b. Transient Response plots ........................................................................................................ 13

c. Output Swing .......................................................................................................................... 16

d. Closed Loop 3 dB Point ............................................................................................................ 16

V. Second Proposed Design Topology.......................................................................................... 17

1. Stable Transconductance Biasing current Circuit ..................................................................... 17

2. Simulation Results .................................................................................................................... 19

a. AC Response Plots .................................................................................................................... 19

b. Transient Response .................................................................................................................. 20

c. Output Swing ............................................................................................................................ 22

d. Closed Loop 3dB point .............................................................................................................. 23

V. Summary/Conclusion ............................................................................................................... 24

Appendix ........................................................................................................................................ 26

Abstract In this project, I designed and simulated, using HSPICE, a two stage CMOS operational

amplifier based on the 0.35μm process. I introduced two design topologies that meet the following specifications, as outlined in the table below.

Both designs use a nulling resistor to boost the gain magnitude while keeping the phase margin under control, so that the system is stable. The nulling resistor can be used to either eliminate the Right Hand Plane, RHP, zero or move it to the Left Hand Plane, LHP. I implemented the nulling resistor using an NMOS operating in triode mode, instead of a discrete resistor, for better circuit performance, and more control of the trans-conductance gm.

The designed operational amplifier in both designs is meant to meet the specifications, even when there is a ± 10% variation of the DC input of the supply voltage, Vdd. To achieve such a purpose, I used the stable trans-conductance biasing circuit, we learned about in class, in the second design (Figure 19); while I used in the first design the biasing circuit given in the project proposal (Figure 2).

Process 0.35µm VDD 3.3V VSS 0V Load 1pF Nominal Input Common-mode( input DC Level) 1.65V Nominal Output Common Mode ( Output DC Level) 1.65 +/-0.1V Overall Power Consumption( including bias Circuit) ≤ 1mW Output peak-peak swing 1.5V Low-Frequency Differential to Single Ended Gain ≥ 50dB Unity Gain Frequency ≥ 200MHz Phase Margin ≥ 60 Degrees Slew Rate ≥ 10V/µV Maximum length of transistor L= 5xLmin

Figure1. Design Specification

I. Introduction An operational amplifier is such a versatile electronics component that finds its use in

almost any electronics device nowadays. Operational amplifiers are used in Measurements, DSP (Audio, Video), and Control circuits. They are also used for data conversion (ADCs, and DACs) and data transmission.

The next sections of this report cover the calculations, design procedures taken, and simulation results.

II. First Proposed Design Topology The image below shows the schematics of the suggested design topology. It is a two

stages differential input amplifier with a biasing circuit.

Figure2. The Opamp designed topology

In this design topology, it is assumed that: VGS4=VGS6, as this result in proper mirroring in M3-M4 mirror. The gate and drain of M4 are assumed to be at same potential

so that M4 is forced into saturation: VDG4=0. Consequently: I6=I7; and:

=

, which sets the “Balance Condition” for the Opamp.

To compensate the two stage op-amp we insert a capacitor, Cc, across the second stage. Therefore, due to the miller effect the inter stage pole moves towards origin ( appears as

at the input of the second stage).Therefore knowing the dc gain we can calculate the unity gain bandwidth.

III. Design Procedure With the help of an excel spreadsheet, all relevant equations needed to obtain the

MOSFETs channel length and width were evaluated. Afterwards, HSPICE was used to verify that design specifications were met and to optimize design as well. Below are the steps I followed in the evaluation of all the equations:

1. First Step: I estimated µCox, Vth, and λ for both NMOSFETs and PMOSFETs Vth Estimation: Varying VGS and keeping VDS constant. I used two different

saturation currents to solve for Vth using this equation:

=μ ( − )

μ ( − )

λ Estimation: Varying VDS and keeping VGS constant. I used two different saturation currents to solve for λ using this equation:

=μ ( + )( − )

μ ( + )( − )

µCox Estimation: Using V

th, and λ we estimated, and a saturation current Id, we

estimate µCox using the following equation:

= μ ( − ) ( + )

The same process was repeated for PMOSFETs: Vth was estimated by varying VSG and keeping VSD constant; while λ was estimated by varying VSD and keeping VSG constant. Finally, the estimated parameters were found to be:

For the NMOSFETs: µnCox=100µA/V2; Vth=0.55V; λ=0.075 V-1

For the PMOSFETs: µpCox=50µA/V2; Vth= 0.5V; λ=0.092 V-1

2. Second Step: I calculated the minimum value for the compensation capacitor Cc :

Cc>(0.22)(CL)=0.22pF; with CL =1pF.

Cc=1pF was selected. It is worth mentioning here that the equation above assumes 60 degrees Phase Margin and Zero ≥10 GB (Unity Gain Bandwidth.)

3. Third Step: I calculated the “tail current” I5 based on the slew rate given in the design specification and Cc that we just calculated above:

= ∗ =10µA

But we selected 150µA, as this value resulted in a good matching between the calculated and simulated results.

4. Fourth Step: I calculated (W/L)3 ,using ICMR requirements (used worst case thresholds +/- 0.10V):

=/

μ ( )

I assumed Veff3=0.1V.

From which we get: = = 150; For L=0.35 µm; W=52.5 µm.

Also I needed to verify that the pole of M3 due to Cgs3 and Cgs4 will not be dominant

by assuming it to be greater than 10GB: > ; =

≈ − = . ∗ ( ) / = .

= . ;

=6fF/µm2

Soitlooksp3 is not a concern as it is significantly larger than 10 GB.

5. Fifth Step: In this step I calculate: and

= = ( ) =210.55;

With:

= ∗ = . μ ;

And = =75μA; and GB=200MHz

From which we get: L1=L2=0.35µm; W1=W2≈ 73.7 µm.

6. Sixth Step: Here we needed to find VSD5(sat) so that we can calculate :

= ( )− − − ( ) ≥

. ≥ ;

For better simulation results I selected VSD= 300mV.

Therefore: 5 = ( )

=210.5 , which leads us to L5=0.35µm and

W5=23.3µm.

7. Seventh Step: Here I calculate for a 60 degrees Phase Margin, with gm6

≥10gm1

We assumed VGS4=VGS6 and let second pole p2 equal 2.2 times GB:

gm6=2.2gm2(CL/Cc); p2=-gm6/CL

I selected gm6 equal 40 times gm1 for better simulation results:

gm6= 50265.4816µS ≥10gm1

=

Therefore: = ≈71.1 ; L6=0.35 µm and W6=49.8 µm.

8. Last Step: In this last step, I calculated: . In this calculation, I selected

I5=I6=150µA. Also I went back and verified the DC gain and power dissipation of the system, using the equations below:

=

=210.5, therefore: L=0.35 µm and W=23.3 µm

9. Biasing Circuit The biasing current in this circuit is defined by the following equation (I referred to

assignment4 of previous year on the course website):

( / ) + − I R =

( / )+

=2

√−√

As the design specifications says: Ibias=25µA, I selected R= 4Kῼ, and with Hpice I optimized the biasing circuit till I was able to set the current though M12 to be equal 25 µA. For references I attached the HSPICE script for this simulation (BiasCircuit.sp). Below are the width values for M9, M10, M11 and M12 for the bias current circuit. As it appears from the equation above, the bias current Ibias is independent of the supply voltage Vdd:

(W/L) = 4.2 (W/L) = 16.8

WL ,

= 7

The table below summarizes the design parameters we obtained before and after design optimization, with Cc=1pF; CL=1pF; Ibias=I5=150µm:

Initial Design for W Initial Design for L Aspect Ratio

W1=73.5 µm L1=0.35µm 210 W2=73.5 µm L2=0.35µm 210 W3=52.5 µm L3=0.35µm 150 W4=52.5 µm L4=0.35µm 150 W5=23.8 µm L5=0.35µm 68 W6=49.7 µm L6=0.35µm 142 W7=23.8 µm L7=0.35µm 68 W9=4.2 µm L7=0.35µm 12 W10=16.8 µm L7=0.35µm 48 W11=7 µm L7=0.35µm 10 W12=7µm L7=0.35µm 10

Figure3. Summary of Design parameters

10. Elimination of RHP Zero Right Hand Plane Zero boots the magnitude, but it lags the phase which causes instability of the

system. One approach is to add a resistor to the Miller compensated Opamp, a resistor in series with

compensation capacitor Cc, as in the following design topology, so that RHP zero is eliminated or

moved to LHP.

Figure4. Implementation of Nulling Resistor Rz

11. Nulling Resistor Rz Calculation

Here we desire to have second pose p2 equal to zero: P2=Z1, so that RHP zero ,Z1, cancels output P2.

= −

= −−

Therefore:

=( + )

=( + )

⎝

⎛

⎠

⎞

Using the calculated gm6, Rz turned out to be 1.37KΩ.

IV. Simulation Results

1. Initial Results

Figure5. DC Gain in dB and Phase Margin

As it can be seen from the bode plot the required deferential gain is equal to 59.1dB, which is more than required gain (50dB). However, the Phase Margin, Unity Gain frequency, and the other design requirements are not met. Therefore, an optimization of the design had to be done.

2. Optimized Design

The table below summarizes all the values for Length, and Width of the MOSFETs. The values for Cc, CL , and Rz: Cc=1 PF, CL=1pF, Rz=1.5Kῼ

W After Optimization L After Optimization Aspect Ratio W1=79.8 µm L1=0.7µm 114 W2=79.8 µm L2=0.7µm 114 W3=60.2 µm L3=0.7µm 86 W4=60.2 µm L4=0.7µm 86 W5=26.6 µm L5=0.35µm 76 W6=50.4 µm L6=0.35µm 144 W7=49 µm L7=0.35µm 140 W9=4.2 µm L4=0.35µm 12 W10=16.8 µm L5=0.35µm 48 W11=7 µm L6=0.35µm 10 W12=7 µm L7=0.35µm 10

Figure6. Optimized design Parameters

The screen shots below shows the simulation results of the optimized design. Results shows a DC gain of 64.4 dB, a Phase Margin of 72 Degrees, and a Unity bandwidth equal to 270 MHz.

Figure7. DC gain in dB

Figure8. Phase Margin and Unity Gain Bandwidth

Even though this design has met most of design specifications, I further optimized the design so that instead of using a normal resistor as a nulling resistor, I want to use an NMOS that operates in triode mode. This NMOSFET connection is as such: the gate is connected to gate of M11, source connected to gate of M6, and drain is connected to Cc.

This implementation allows for the circuit to be dependent on the process parameters of the MOSFET rather than on the value of the resistor.

3. Optimized Design with Nulling NMOS The table below summarizes all the final values for Length, and Width of the

MOSFETs:

W After Optimization L After Optimization Aspect Ratio

W1=79.8 µm L1=0.7µm 114 W2=79.8 µm L2=0.7µm 114 W3=60.2 µm L3=0.7µm 86 W4=60.2 µm L4=0.7µm 86 W5=24.5 µm L5=0.35µm 70 W6=50.4 µm L6=0.35µm 144 W7=49 µm L7=0.35µm 140 W9=4.2µm L4=0.35µm 12 W10=16.8 µm L5=0.35µm 48 W11=7 µm L6=0.35µm 10 W12=7 µm L7=0.35µm 10

Figure9. Optimized design Parameters

4. Results After Optimization The table below summarizes all achieved design parameters versus the design

requirements. The design can be verified by running the following HSPIC scripts: OpAmpCmp.sp: for Frequency response bode plot. OpAmpTransCmp.sp: for transient response plots. OpAmpCmp_3dB.sp: for close loop AC response, showing 3dB plot.

Design Requirements Achieved Results Process 0.35µm 0.35µm VDD 3.3V 3.3V VSS 0V 0V Load 1pF 1pF Nominal Input Common-mode (input DC Level)

1.65V 1.65V

Nominal Output Common Mode (Output DC Level)

1.65 +/-0.1V 1.65 +/-0.1V

Overall Power Consumption (including bias Circuit)

≤ 1mW 990.05 µW

Output peak-peak swing 1.5V 1.5V Low-Frequency Differential to Single Ended Gain

≥ 50dB 63.1 dB

Unity Gain Frequency ≥ 200MHz 238 MHz Phase Margin ≥ 60 Degrees 72 Degrees

Slew Rate ≥ 10V/µs 59.7V/µs Maximum length of transistor L= 5xLmin 25xLmin

Figure10. The achieved results after optimization

a. AC Response Plots

Figure11. DC gain in dB

Figure12. Phase Margin and Unity Gain Bandwidth

b. Transient Response plots More simulation results were taken for the transient response of the operational

amplifier. In a closed loop configuration a step input of: 0.1V, -0.1V, 1V, -1V, 0.1V, -0.1V was applied. The closed loop configured by connecting one of the two differential inputs to the

output (node 9) and used the other input to apply the step input (node10). Below are the transient response plots with measured rise time and slew rate.

Figure13. Closed loop unity gain transient response to a 0.1V step

Rise Time is measured from 1.66V to 1.74V = 14.9ns - 10.4ns = 4.5ns

Settling time from 1.65V to 1.75V = 46.8ns -19.8ns=36.8ns

Figure14. Closed loop unity gain transient response to a -0.1V step

Fall Time is measured from 1.64V to 1.56V = 14.7ns - 10.3ns = 4.37ns

Settling time from 1.65V to 1.55V = 26.2ns -10.1ns=16.1ns

Figure15. Closed loop unity gain transient response to a +1V step

Rise Time is measured from 1.75V to 2.55V = 30.8ns – 11.7ns = 19.1ns

Settling time from 1.65V to 2.65V = 53.6ns -10.3ns=43.3ns

For Slew Rate calculation, I measured time at 1.8V and at 2.2V, and this is what I got:

Slew Rate= (1.8V-2.2V)/(12.3ns-19ns) ≈59.7V/µs

Figure16. Closed loop unity gain transient response to a -1V step

Fall Time is measured from 1.55V to 0.75V = 17.2ns -10.2ns = 7.01ns

Settling time from 1.65V to 0.65V = 25.3ns -10.1ns= 15.2ns

The plot below shows the output peak to peak swing. The input signal is a sinusoidal waveform with a 1.5V peak to peak, and 1MHz frequency, with a 1.65V DC offset. The output is an exact waveform of the input: a peak to peak swing of 1.5V symmetric around 1.65V and 1 MHz frequency. Vout Maximum=2.4V and Vout Minimum=0.9V.

c. Output Swing

Figure17.Closed loop output swing peak to peak

d. Closed Loop 3 dB Point

Figure18.Closed loop output unity gain AC response showing -3dB frequency

V. Second Proposed Design Topology

1. Stable Transconductance Biasing Current Circuit Even though the biasing circuit I introduced in the first design topology for this

opamp has a bias current that is independent of the power supply voltage VDD, I still want to replace it with the stable trans-conductance biasing circuit we learned about in class so that I would gain more insight and understanding of how this circuit operates.

The circuit allows the opamp to meet all design specifications even with a -/+10% variations in power supply Vdd. The figure below shows the circuit diagram.

Figure 19. Stable transconductance biasing current circuit

Using the following formula from the class notes and Hspice, I found the aspect ratios of all MOSFETs making the circuit. The table below summarizes the widths and lengths of the circuit MOSFETs. The circuit generates a 25 uA current, as it is required in the design specs.

= 2

⎣⎢⎢⎢⎡

1−

√√

√√

⎦⎥⎥⎥⎤

/

The tans-conductance of M10 is determined by geometric ratios only. It is independent of power supply voltages, process parameters, temperature, etc.

I found that = 0.91/

W for Opamp Circuit L for Opamp Circuit Aspect Ratio

W1=79.8 µm L1=0.7µm 114 W2=79.8 µm L2=0.7µm 114 W3=60.2 µm L3=0.7µm 86 W4=60.2 µm L4=0.7µm 86 W5=75.25 µm L5=0.35µm 215 W6=46.9 µm L6=0.35µm 134 W7=50.4 µm L7=0.35µm 144 W for Bias Circuit L for Bias Circuit Aspect Ratio W9=15.4 µm L9=0.7µm 22 W10=11.2µm L10=0.35µm 32 W11=7µm L11=0.35µm 20 W12=7 µm L12=0.35µm 20 W13=1.05 µm L13=0.35µm 3 W14=1.05 µm L14=0.35µm 3

Figure20. The Aspect Ratio of the MOSFETS

Below is a snapshot of the HSPICE script that I used for simulating the bias circuit. The full to be run for verification is names: BiasCircuit2.sp

**Biasing Circuit M11 node3 node3 node1 0 PCH l=0.35U w= 7U M12 node2 node3 node1 0 PCH l=0.35U w= 7U

M13 node3 node2 node13 0 NCH l=0.35U w= 1.05U M14 node2 node2 node14 0 NCH l=0.35U w= 1.05U M9 node13 node14 node4 node4 NCH l=0.7U w= 15.4U M10 node14 node14 0 0 NCH l=0.35U w= 11.2U

RB node4 0 10k

2. Simulation Results

a. AC Response Plots The plots below show the simulation results for the final design. These plots include:

Frequency Response, Closed Loop Transient Response, and closed loop -3dB AC response. For references, the following HSPICE can be run for view of full simulation results:

OpAmpTransCmp2.sp: for the AC frequency response. OpAmpTransCmp2.sp: for the closed loop transient response. OpAmpCmp_3dB.sp: for the AC closed loop -3dB point.

Figure21. DC gain in dB

Figure22. Phase margin and the unity gain bandwidth

b. Transient Response More simulation results were taken for the transient response of the operational

amplifier. In a closed loop configuration a step input of: 0.1V, -0.1V, 1V, -1V, 0.1V, -0.1V was applied. The closed loop configured by connecting one of the two differential inputs to the output (node 9) and used the other input to apply the step input (node10). Below are the transient response plots with measured rise time and slew rate.

Figure23. Closed loop unity gain transient response to a +0.1V step

Rise Time is measured from 1.66V to 1.74V = 15.3ns - 10.7ns = 4.6ns

Settling time from 1.65V to 1.75V = 38.9ns -10ns=28.9ns

Figure24. Closed loop unity gain transient response to a -0.1V step

Fall Time is measured from 1.64V to 1.56V = 13.9ns - 10.4ns = 5.51ns

Settling time from 1.65V to 1.55V = 15.7ns -9.94ns=5.8ns

Figure25. Closed loop unity gain transient response to a +1V step

Rise Time is measured from 1.75V to 2.55V = 48.3ns – 18.4ns = 29.9ns

Settling time from 1.65V to 2.65V = 271ns -11ns=260ns

For Slew Rate calculation, I measured time at 1.8V and at 2.4V, and this is what I got:

Slew Rate= (1.8V-2.4V)/(20.7ns-43.7ns) ≈26.1V/µs

Figure26. Closed loop unity gain transient response to a -1V step

Fall Time is measured from 1.55V to 0.75V = 16.3ns – 10.2ns = 6.1ns

Settling time from 1.65V to 0.65V = 21ns -10ns=11ns

The plot below shows the output peak to peak swing. The input signal is a sinusoidal waveform with a 1.5V peak to peak, and 1MHz frequency, with a 1.65V DC offset. The output is an exact waveform of the input: a peak to peak swing of 1.5V symmetric around 1.65V and 1 MHz frequency. Vout Maximum=2.4V and Vout Minimum=0.9V.

c. Output Swing

Figure27.Closed loop output swing peak to peak

d. Closed Loop 3dB point

Figure28.Closed loop output unity gain AC response showing -3dB frequency

V. Summary/Conclusion

Two design topologies for a deferential input 2 stage operational amplifier have been designed and simulated. The two design topologies defer only in the biasing circuitry; however, both designs meet all design specifications even if the supply voltage Vdd experiences a -/+10 % variation. The table below lists the achieved results in both designs.

Design Requirements

Achieved Results with Suggested Design Topology

Achieved Results with Transconductance Bias Circuit

Process 0.35µm 0.35µm 0.35 µm VDD 3.3V 3.3V 3.3V VSS 0V 0V 0V Load 1pF 1pF 1pF Nominal Input Common-mode (input DC Level)

1.65V 1.65V 1.65V

Nominal Output Common Mode (Output DC Level)

1.65 +/-0.1V

1.65V 1.59V

Overall Power Consumption

≤ 1mW 990.05 µW 804 µW

Output peak-peak swing 1.5V 1.5V 1.5V Low-Frequency single ended gain ≥ 50dB 63.1 dB 67.1dB Unity Gain Frequency ≥

200MHz 238 MHz 204 MHz

Phase Margin ≥ 60 Degrees

72 Degrees 65.1 Degrees

Slew Rate ≥ 10V/µs 59.7V/µs 26.1 V/µs Maximum length of transistor L= 5xLmin 2xLmin 2xLmi

Figure29. The achieved results after optimization

Appendix Hspice Script with with Stable Transconductance Bias current Circuit, AC frequency Response

**Farid Mabrouk **Final Term Project, Winter 2014 *Cascode Two Stage Opamp design with Stable Transconductance Bias current Circuit .lib '/ubc/ece/home/courses/eece488/hspice/cmosp35/mm0355v.l' TT **Biasing Circuit M11 node3 node3 node1 0 PCH l=0.35U w= 7U M12 node2 node3 node1 0 PCH l=0.35U w= 7U M13 node3 node2 node13 0 NCH l=0.35U w= 1.05U M14 node2 node2 node14 0 NCH l=0.35U w= 1.05U M9 node13 node14 node4 node4 NCH l=0.7U w= 15.4U M10 node14 node14 0 0 NCH l=0.35U w= 11.2U R node4 0 10k **Two Stage OpAmp M1 node6 node9 node5 node1 PCH l=0.7U w=79.8U M2 node8 node10 node5 node1 PCH l=0.7U w=79.8U M3 node6 node6 0 0 NCH l=0.7U w=60.2U M4 node8 node6 0 0 NCH l=0.7U w=60.2U M5 node5 node3 node1 node1 PCH l=0.35U w=75.25U M6 node11 node8 0 0 NCH l=0.35U w=46.9U M7 node11 node3 node1 node1 PCH l=0.35U w=50.4U **Voltage Sources Vdd node1 0 DC 3.3 Vin1 node9 0 DC 1.65 AC 1 vin2 node10 0 DC 1.65 AC 1, 180 **Compensating Circuit Cc node12 node11 1p MC node12 node3 node8 0 NCH l=0.7U w=2.1U CL node11 0 1p .ac dec 100 1k 10G .print ac vdb (node11) .print ac vp (node11) .OP .option post list .option brief .END

Hspice Script with with Stable Transconductance Bias current Circuit, Closed Loop Transient Response

**Farid Mabrouk **Final Term Project, Winter 2014 *Cascaded Two Stage Opamp design .lib '/ubc/ece/home/courses/eece488/hspice/cmosp35/mm0355v.l' TT **Biasing Circuit M11 node3 node3 node1 0 PCH l=0.35U w= 7U M12 node2 node3 node1 0 PCH l=0.35U w= 7U M13 node3 node2 node13 0 NCH l=0.35U w= 1.05U M14 node2 node2 node14 0 NCH l=0.35U w= 1.05U M9 node13 node14 node4 node4 NCH l=0.7U w= 15.4U M10 node14 node14 0 0 NCH l=0.35U w= 11.2U R node4 0 10k **Two Stage OpAmp M1 node6 node9 node5 node1 PCH l=0.7U w=79.8U M2 node8 node10 node5 node1 PCH l=0.7U w=79.8U M3 node6 node6 0 0 NCH l=0.7U w=60.2U M4 node8 node6 0 0 NCH l=0.7U w=60.2U M5 node5 node3 node1 node1 PCH l=0.35U w=75.25U M6 node9 node8 0 0 NCH l=0.35U w=46.9U M7 node9 node3 node1 node1 PCH l=0.35U w=50.4U **Voltage Sources Vdd node1 0 DC 3.3 **Compensating Circuit Cc node12 node9 1p MC node12 node3 node8 0 NCH l=0.35U w=2.1U CL node9 0 1p *Transient Response for 0.1V Step********** *Vin2 node10 0 DC PWL(0us 1.65V 10ns 1.65V 10.001ns 1.75V 2us 1.75V) *.TRANS 1n 2u *Vin2 node10 0 SIN(1.65V 1V 1Meg ) *.TRANS 1n 4u *Transient Response for -0.1V Step********** *Vin2 node10 0 DC PWL(0us 1.65V 10ns 1.65V 10.001ns 1.55V 2us 1.55V) *.TRANS 1n 2u *Transient Response for 1V Step********** Vin2 node10 0 DC PWL(0us 1.65V 10ns 1.65V 10.001ns 2.65V 20us 2.65V) .TRANS 1n 20u *Transient Response for -1V Step**********

*Vin2 node10 0 DC PWL(0us 1.65V 10ns 1.65V 10.001ns 0.65V 2us 0.65V) *.TRANS 1n 2u *.measure tran peaktopeak pp v(node9)=0 to= 2ms *.MEASURE t_rise TRIG v(node9) VAL=1.66 RISE=1 TARG v(node9) VAL=1.74 RISE=1 .OP .OPTION LIST NODE POST .END Hspice Script with Suggested design Topology, AC frequency Response

**Farid Mabrouk **Final Term Project, Winter 2014 *Cascode Two Stage Opamp design .lib '/ubc/ece/home/courses/eece488/hspice/cmosp35/mm0355v.l' TT **Biasing Circuit M9 node4 node2 0 0 NCH l=0.35U w= 4.2U M10 node3 node4 0 0 NCH l=0.35U w= 16.8U M11 node2 node3 node1 node1 PCH l=0.35U w=7U M12 node3 node3 node1 node1 PCH l=0.35U w=7U R node2 node4 4k **Two Stage OpAmp M1 node6 node9 node5 node1 PCH l=0.7U w=79.8U M2 node8 node10 node5 node1 PCH l=0.7U w=79.8U M3 node6 node6 0 0 NCH l=0.7U w=60.2U M4 node8 node6 0 0 NCH l=0.7U w=60.2U M5 node5 node3 node1 node1 PCH l=0.35U w=24.5U M6 node11 node8 0 0 NCH l=0.35U w=50.4U M7 node11 node3 node1 node1 PCH l=0.35U w=49U **Voltage Sources Vdd node1 0 DC 3.3 Vin1 node9 0 DC 1.65 AC 1 vin2 node10 0 DC 1.65 AC 1 , 180 **Compensating Circuit Cc node12 node11 1p MC node12 node3 node8 0 NCH l=0.35U w=1.75U CL node11 0 1p .ac dec 100 1k 10G .print ac vdb (node11) .print ac vp (node11) .OP .option post list

.option brief

.END Hspice Script with Suggested design Topology, Closed Loop Transient Response

**Farid Mabrouk **Final Term Project, Winter 2014 *Cascaded Two Stage Opamp design .lib '/ubc/ece/home/courses/eece488/hspice/cmosp35/mm0355v.l' TT **Biasing Circuit M9 node4 node2 0 0 NCH l=0.35U w= 4.2U M10 node3 node4 0 0 NCH l=0.35U w= 16.6U M11 node2 node3 node1 node1 PCH l=0.35U w=7U M12 node3 node3 node1 node1 PCH l=0.35U w=7U R node2 node4 4k **Two Stage OpAmp M1 node6 node9 node5 node1 PCH l=0.7U w=79.8U M2 node8 node10 node5 node1 PCH l=0.7U w=79.8U M3 node6 node6 0 0 NCH l=0.7U w=60.2U M4 node8 node6 0 0 NCH l=0.7U w=60.2U M5 node5 node3 node1 node1 PCH l=0.35U w=24.2U M6 node9 node8 0 0 NCH l=0.35U w=50.4U M7 node9 node3 node1 node1 PCH l=0.35U w=49U **Voltage Sources Vdd node1 0 DC 3.3 **Compensating Circuit Cc node12 node9 1p MC node12 node3 node8 0 NCH l=0.35U w=1.75U CL node9 0 1p *Transient Response for 0.1V Step********** *Vin2 node10 0 DC PWL(0us 1.65V 10ns 1.65V 10.001ns 1.75V 2us 1.75V) *.TRANS 1n 2u *Vin2 node10 0 SIN(1.65V 0.75V 1Meg ) *.TRANS 1n 4u *Transient Response for -0.1V Step********** *Vin2 node10 0 DC PWL(0us 1.65V 10ns 1.65V 10.001ns 1.55V 2us 1.55V) *.TRANS 1n 2u *Transient Response for 1V Step********** Vin2 node10 0 DC PWL(0us 1.65V 10ns 1.65V 10.001ns 2.65V 20us 2.65V) .TRANS 1n 20u

*Transient Response for -1V Step********** *Vin2 node10 0 DC PWL(0us 1.65V 10ns 1.65V 10.001ns 0.65V 2us 0.65V) *.TRANS 1n 2u *.measure tran peaktopeak pp v(node9)=0 to= 2ms .MEASURE t_rise TRIG v(node9) VAL=1.75 RISE=1 TARG v(node9) VAL=2.55 RISE=1 .OP .OPTION LIST NODE POST .END