Table of Contents 135250

7/28/2019 Table of Contents 135250

1/20

Computer

Architectureand Organization

Third Edition

John P. ~ a ~ e s

McGraw-Hill PrimisCustom PublishingNew York St. Louis San Francisco Auckland BogotaCaracas Lisbon London Madrid Mexico Milan MontrealNew Delhi Paris San Juan Singapore Sydney Tokyo


2/20

CONTENTS

Preface ...X l l l

1 Computing andComputers 11.1 The Nature of Computing 1

1.1.1 The Elements of Computers / 1.1.2 Limitationsof Computers

1.2 The Evolution Of Computers 12

1.2.1 The Mechanical Era / 1.2.2 Electronic Computers /1.2.3 The Later Generations

1.3 The VLSI Era 35

1.3.1 Integrated Circuits / 1.3.2 ProcessorArchitecture /1.3.3 System Architecture

1.4 Summary 56

1.5 Problems 57

1.6 References 62

2 DesignMethodology2.1 System Design

2.1.1 System Representation / 2.1.2 Design Process /2.1.3 The Gate Level

2.2 The Register Level

2.2.1 Register-Level Components / 2.2.2 ProgrammableLogic Devices / 2.2.3 Register-Level Design

2.3 The Processor Level

2.3.1 Processor-Level Components / 2.3.2 Processor-LevelDesign

2.4 Summary

2.5 Problems

2.6 References

3 ProcessorBasics

3.1 CPU Organization

3.1.1 Fundamentals / 3.1.2 Additional Features


3/20

Contents

3.2 Data Representation 160

3.2.1 Basic Formats / 3.2.2 Fixed-Point Numbers /3.2.3 Floating-Point Numbers

3.3 Instruction Sets 178

3.3.1 Instruction Formats / 3.3.2 Instruction Types /3.3.3 Programming Considerations

3.4 Summary 21 13.5 Problems 212

3.6 References 221

4 Datapath Design 2234.1 Fixed-Point Arithmetic 223

4.1.1 Addition and Subtraction / 4.1.2 Multiplication /4.1.3 Division

4.2 Arithmetic-Logic Units 252

4.2.1 CombinationalALUs / 4.2.2 Sequential ALUs4.3 Advanced Topics 266

4.3.1 Floating-Point Arithmetic / 4.3.2 Pipeline Processing4.4 Summary 292

4.5 Problems 293

4.6 References 301

5 Control Design 3035.1 Basic Concepts 303

5.1 .l Introduction / 5.1.2 Hardwired Control /5.1.3 Design Examples

5.2 Microprograrnmed Control 332

5.2.1 Basic Concepts / 5.2.2 Multiplier Control Unit /5.2.3 CPU Control Unit

5.3 Pipeline Control 364

5.3.1 Instruction Pipelines / 5.3.2 Pipeline Perjormance /5.3.3 Superscalar Processing

5.4 Summary 390

5.5 Problems 392

5.6 References 399

6 Memory Organization 400

6.1 Memory Technology 400

6.1.1 Memory Device Characteristics / 6.1.2 Random-Access Memories/6.1.3 Serial-Access Memories


4/20

6.2 Memory Systems 426

6.2.1 Multilevel Memories / 6.2.2 Address Translation / contents6.2.3 Memory Allocation

6.3 Caches 452

6.3.1 Main Features / 6.3.2 Address Mapping /6.3.3 Structure versus Performance

6.4 Summary 4716.5 Problems 472

6.6 References 478

7 SystemOrganization 4807.1 Communication Methods 480

7.1.1 Basic Concepts / 7.1.2 Bus Control7.2 I0 And System Control 504

7.2.1 ProgrammedI0 / 7.2.2 DMA and Interrupts /7.2.3 I 0 Processors / 7.2.4 Operating Systems

7.3 Parallel Processing 539

7.3.1 Processor-Level Parallelism / 7.3.2Multiprocessors /7.3.3 Fault Tolerance

7.4 Summary 578

7.5 Problems 579

7.6 References 587

Index 589


5/20

Index

Abacus, 1Absolute addressing, 187Access efficiency, memory, 430Access time, 402,419,430Accumulator, 140Acknowledge signal, 496Acorn RISC Machine, 150Actel Corp., 101Ada programming language, 66Adder, 224-233

4-bit serial, 80, 10974283 circuit, 229carry-lookahead, 228-229conditional-sum, 295expansion of, 229floating-point, 270-272,277-280full, 74, 89

half, 67,127parallel, 80,92,224ripple-carry, 224,229serial, 79,102,224

Adder-subtracter, twos-complement,226,231-233Addition

carry-save, 285fixed-point, 224-233floating-point, 269-271

Address, 22, 179,333

Address cache, 435Address interleaving, 416Address mapping;see Address

translationAddress register, 22Address trace, 147,447Address translation, 432-443

in cache, 457-465in Intel Pentium, 439-441in MIPS R2/3000,435

Addresses, number of, 179, 189Addressing, in microinstructions, 337Addressing modes, 184-191

of680XO,154,188Address-modify instruction, 23, 164Advanced Micro Devices (AMD)

products

2900 bit-sliced microprocessor series,260

2901 ALU slice, 261-264,350-3532902 carry-lookahead generator, 2632909 microprogram sequencer,

341-344,3522910 microprogram sequencer, 352

Advanced programmable interruptcontrol (APIC), 529

Advanced Research Projects Agency

(ARPA), 54


6/20

90

NDEX

Advanced RISC Machines Ltd. (ARM),150

Age register, 447Aiken, Howard, 17Algorithm, 3ALU (arithmetic-logic unit), 3,252-265

1601 circuit, 264

2901 circuit, 261-

264,350-

35374181 circuit, 254-256,299bit-sliced, 261, 350-353combinational, 252-256expansion of, 258sequential, 256-265ALUIfunction generator, 74181,

254-256,299Amdahl, Gene M., 549Amdahl470Vl7 computer, 369,380Amdahl's law, 549American National Standards Institute

(ANSI), 482Analog, 3Analysis, 69Analytical Engine, 15Apple Macintosh computer, 41Arithmetic

fixed-point, 223-251floating-point, 266-275

Arithmetic element, 9 1Arithmetic instruction, 194Arithmetic pipeline, 275-292Arithmetic-logic unit; seeALUARM6 microprocessor, 150-154, 162,

181ARPANET computer network, 54,487ASCII code, 161,171Assembler, 20,204Assembly language, 20,202

programming in, 202-

21 1Assembly listing, 204Associative addressing, 436,457Associative memory, 457459Asynchronous signal, 78Asynchronous transfer mode (ATM),

485AT&T No. 1 Electronic SwitchingSystem, 571

Atanasoff, John V., 17Autoindexing, 158, 188

Automatic Sequence ControlledCalculator, 17

Availability, 571,575instantaneous, 574

Babbage, Charles, 2, 13, 15, 17,66,75Backus, John, 29Bandwidth, 122,406Base

of fixed-point number, 167of floating-point number, 173

Base address, 187,433Base addressing, 432-434Base register, 182, 187Basic computer organization, 51Basic programming language, 29

Batch processing, 32BCD code, 171Behavior, 65Bell Laboratories, 27,530Benchmark program, 44,122,467Bias, exponent, 175Big-endian, l63Binary number code, 167, 169Binary-coded decimal; seeBCD codeBipolar IC, 38

Bisection width, graph, 579Bit (binary digit), 4Bit slicing, 258,349Bit-sliced ALU, 261,350-353Block diagram, 65,66Blocking network, 562Bolt, Beranekand Newman (BBN) Inc.,

566Bolt, Beranek and Newman computers

Butterfly, 566

TC2000,566Boole, George, 75Boolean algebra, 66,73,75word-based, 85Boolean function, 73

Booth, Andrew D., 238Booth multiplication algorithm,

238-240,242-244,297modified, 297

Brain as computer, 3Branch history table, 388


7/20

Branch instruction, 16,23,150Branch prediction, 387Branch target buffer, 388Bridge, 42,501Broadcasting in hypercube, 585Burroughs computersB5000,30B6500/7500,164,216,437

Burst mokle, 417Bus, 84,97,481-483; see also

Communication; Interconnectionnetwork

dedicated, 9710,482local, 483,501Multibus, 580PCI, 41,483,501-504

Rambus, 417shared, 489,491

-

504,544synchronous, 492system, 481timing of, 495-498token, 487

Bus arbitration, 493,498daisy-chaining, 499independent requesting, 500polling, 499

Bus control, 118,491-

504Bus master, 481Bus slave, 481Busicom, 37Butterfly connection, 563Byte, 34

C programming language, 29,66Cache, 27,45,115,117,138,401

address translationin, 457-465data (D-cache), 465

design of, 467of Data General ECLIPSE, 459instruction (I-cache), 465look-aside, 453,470look-through, 455,470operation of, 455-457organization of, 453-455performance of, 466ofPowerPC620 microprocessor, 468

Cache-Cont. 591ofPowerPC series, 461,463,465

INDEXsplit, 426,465unified, 369,426,465write policy of, 456

Cache coherence problem, 456,554Cache data memory, 453

Cache snooping, 555Cache tag memory, 453CAD (computer-aided design), 67,70,

76Calculator

mechanical, l 2pocket, 3,31,37

Call instruction, 31, 210Caltech (California Institute of

Technology), 558

Cambridge University, 34Carrier, 483Carry-lookahead, 228-229Carry-save addition, 285CD-R (compact disk recordable)

memory, 405,425CD-ROM (compact disk read-only

memory), 405,424Cedar multiprocessor, 561Central processing unit; see CPU

CERN (CentreEuropCen pour laRecherche NuclCaire), 54Channel; see IOPChannel command word; 524; see alsoI 0 instructionsCharacter, l61Characteristic, floating-point, 105Characteristic equation, 78Chip, semiconductor, 36CISC (complex instruction set

computer), 43, 179, 197Classical design method, 308,312Clock, 44Clock cycle, 44, 139Clock frequency, 44,121CMOS IC technology, 38COBOL programming language, 29Collision

in network, 487in pipeline, 374

Collision register, 377


8/20

592

INDEX

Collision vector, 377Combinational circuit, 74Combinational function, 73Communication,480-504; see alsoBus;

Computer network;Interconnection network

asynchronous, 492

intersystem, 480,483intrasystem, 480,483long-distance, 483synchronous, 492

Compaction, memory, 446Comparator, magnitude, 9 1-93,130Compatibility

of control signals, 347software, 33 >

Compiler, 29

Completenessfunctional, 75of instruction set, 193

Complexity, time, 11Comptometer, l 7Computable function, 193Computer architecture, 34Computer network, 53-55,484ARPANET, 54,487

Internet, 54,487

local-

area (LAN), 54,484wide-area (WAN), 484Computer organization, 34Computer-aided design; see CADCondition code, 147Conditional-sum addition, 295Condition-select field, 338Connectivity of graph, 582Content addressing; see Associative

addressingContent-addressable memory (CAM);

see Associative memoryContext switching, 532Control Data computers

CDC 6660,35CYBER series, 35STAR-100,283

Control Data Corp., 35Control dependency, pipeline, 379-381Control field, microinstruction, 332

encoding methods for, 346-350

Control line, 84,304types of, 305

Control memory, 307,332address register for, 333writable, 334

Control point, 108,303Control unit, 104,303; see also

Hardwired control;Microprograrnrned control

Convolution, 300Coprocessor, 51, 159, 198,272-275

in MIPS RX000,272Motorola 68881, 159Motorola 68882, 159,273-275,287

Copy back, cache, 456CORDIC computing technique, 300Cosmic Cube computer, 558

Counter, 96programmable, 97ring, 18

CPI (cycles per instruction), 45,372CPU (central processing unit), 3, 115

accumulator-based, 140,326hardwired control unit for, 326-33 1microprogrammed control unit for,354-364organization of, 137-160

Cray Research Inc., 55Cray-l computer, 55,416Critical resource, 533Crossbar interconnection network, 489,

544,563Crosspoint, 489CSMA/CD arbitration, 486Cube-connected-cycles graph, 580Curie temperature, 425Cycle stealing, 513Cycle time, memory, 406

D flip-flop, 77Data cache (D-cache), 465Data dependency, pipeline, 382Data format, 160Data General ECLIPSE computer, 459Data register, 22Data stream, 543Datapath unit, 104, 108,303


9/20

Data-processing instruction, 23Data-processing unit, 21Data-transfer instruction, 23, 194Data-transfer rate, 406Deadlock, 534-536Decimal number codes, 171Decoder, 90

Dedicated bus, 97Degree, node, 490Delay slot, 369Delayed branching, 381Demand swapping, 444Demultiplexer, 90Denormalized number, 177Design, top-down, 73Design level, 71Design problem, 69

Design verification, 108Destructive readout (DRO), 405Diameter, of graph, 491Difference Engine, 3, 13-15Digital, 3Digital audio tape @AT), 474Digital Equipment computers

Alpha-based, 122PDP series, 35,507VAX series, 35,122

VAX-1U780 computer, 463,465

Digital Equipment Corp., 35Digital video disk (DVD), 425Direct addressing, 154, 185Direct mapping, in cache, 451,460462Direct memory access; see DMADirective, 203,204Disk mirroring, 569,576

Displacement (offset), 182, 187,433Distance, in graph, 491Distributed-memory computer, 56,

539-541,544,557Divider

combinational array, 250sequential, 245-249

Divisionfixed-point, 244-25 1floating-point, 266

Division-Cont.nonrestoring, 248pencil-and-paper, 245by repeated multiplication, 250restoring, 248SRT, 248

DMA (direct memory access), 504,

511-

515DMA block transfer, 5 13DMA channel, 515,526DMA controller, 505,513

design of, 315-3 19DRAM; see RAMDuplex system, 568Dynamic full-access network, 586Dynamic microprogramming, 334

Eckert,J. Presper, 17Eckert-Mauchly Corp., 19Edge triggering, 77,128Editor program, 71EDVAC computer, 18Effective address, 182, 187,433Efficiency

of parallel computer, 548of pipeline, 373

Electronic computer, l 7Embeddability, in hypercube, 557Embedded system, 52Emulation, 307,332Emulator, 332Encoder, 90ENIAC computer, 17Erlang, A. K., 123Error, 567

round-off, 170

Error detection and correction, 165-

166Espresso program, 82,321Ethernet, 485-487Euclid's algorithm, 309Euler, Leonhard, 8Euler circuit, 8, 9E-unit, 21, 115Exception, 147Excess-three code, 171Excitation table, 3 12EXCLUSIVE-OR, 65972

INDEX


10/20

94

DEX

Execute step, 139Execution trace, 147Expansion

of adder, 229of ALU, 258

Exponent, floating-point, 173Exponential law of failure, 572

Failure rate, 571Fan-in, 75Fan-out, 76Fault diagnosis, 568Fault elimination, 568Fault tolerance, 567-577Fault-tolerant computers, 543Felt,Dorr E., 17Ferrite-core memory, 19,27Fetch step, 139Field programming, 98Field-programmable gate array; see

FPGAFIFO (first-in first-out) replacement

policy, 447,449Finite differences, method of, 13Finite-state machine, 8,79Firmware, 308First-generation computer, 19Fixed-point arithmetic, 223

-

25 1addition, 224-233division, 244-25 1multiplication, 233-244subtraction, 225-227

Fixed-point number, 20, 167-173Fixed-point unit, 258; see also ALUFlag register, 147Flash memory, 415Flip-flop, 76

D type, 77JK type, 128

Floating-point adder, 270-272,277-280

Floating-point arithmetic, 266-275Floating-point number, 28, 167,

173-178B6500/7500,216IBM Systeml360-370,178IEEE 754 standard, 175-178,269

Floating-point unit, 268; see alsoCoprocessor

of 68040,287-289Floppy disk memory, 422Flushing, pipeline, 380Flynn, Michael J., 543Flynn's classification of computers, 543Forbidden list, 375FORTRAN programming language, 29FPGA (field-programmable gate array),

100-1 04ACT series, 101, 131

Fragmentation, memory, 439Frequency modulation, 484Full adder, 74,89Full-access network, 561Full-adder equations, 224

Full-subtracter equations, 227Functional completeness, 75

Gate level, 39,71Gate types, 72,75Gated-clocking, 131Gate-level design, 73-83Gateway, 54GCD (greatest common divisor), 309GCD processor, 309-3 15GEC Plessey 1601 ALU, 264General-register organization, 147Glitch, 78Goldbach, Christian, 7Goldbach's conjecture, 7Graph, 8,64 .

of interconnection network, 491resource allocation, 535

Guard bit, 267

Half adder, 67,127Half-adder equations, 224Halting problem, 8Handshaking signals, 498Hard disk memory, 422Hardware description language; see

HDLHardwired control, 307

design of, 308-331


11/20

Harvard Mark I, 17, 18, 19Harvard University, 17Harvard-class computer, 59Hazard, pipeline, 379,382HDL (hardware description language),22,66-69,105-107Heuristic procedure, 12,71Hewlett

-

Packard PA-

RISC computer,122 +Hexadecimal (hex) code, 173Hidden bit, 176Hierarchy, 72,402,426High-impedance state, 493History buffer, 523Hit ratio, 430

block, 448Hollerith,Herman, 17Homogeneous network, 490Horizontal microinstruction, 337html (hypertextmarkup language), 54http (hypertext transport protocol), 54,

488Hypercube computer, 545,557-560Hypercube interconnection network,

490indirect, 564

I ~ C(inter-

integrated circuit) bus, 529IAS computer, 19-27,50

vector addition program for, 25IBM Corp., 17IBM computers

3033,3814300,34701,19801,43,381PC series, 41

POWER architecture, 465RISC System/6000,43,47Systed360Model 91,270-272,386,

452Systed360series, 32-34,335,524Systed370series, 34,334, 369Systed390series, 34IC (integrated circuit), 32, 35IC density, 36IC packaging, 36

IEEE (Institute of Electrical and 595

Electronics Engineers), 67, 175INDEX

IEEE 754 floating-point numberstandard, 175-178,269

IEEE 796 bus standard (Multibus), 580ILLLAC IV computer, 543Immediate addressing, 157, 179, 185

Inclusion property, 449Index register, 187Indexed addressing, 185Indirect addressing, 186Indirect hypercube network, 564Indirection, levels of, 185Industry Standard Architecture (ISA)

bus, 483Input-output; see I0"input-output processor;see IOPInstitute for Advanced Studies,

Princeton, 19Instruction buffer, 384Instruction buffer register, 22Instruction cache (I-cache), 465Instruction cycle, 23,44, 116, 139Instruction execution time, 121Instruction format, 178-191MIPSRXOOO, 182-184

Motorola 680x0, 179RISC I computer, 181

Instruction issue, multiple, 384Instruction mix, 121Instruction pipeline, 149,364-371Instruction register, 21Instruction retry, 371Instruction scheduling, dynamic, 386Instruction set

basic, 143ARM6,151-154,162IAS computer, 22-24,27MIPS RX000,197-202Motorola680x0, 154-158,179Motorola PowerPC, 47-50Turing machine, 5,193representative, 194-196

Instruction stream, 543Instruction types, 194Instruction-level parallelism, 47,539Instruction-set processor; see CPU, IOPIntegrated circuit;see IC


12/20


13/20

Level 2 (L2) cache, 470Level triggering, 77Limit address, 433LINC computer, 35Line, cache, 453Link; see BusLinker, 204Little's equation, 124Little-endian, 163Load instruction, 142Loadlstorearchitecture, 44, 142Local bus, 483,501Locality of reference, 428-429Logarithm, 2Logic function, 73Logic level, 39,71Logical address, 428Logical instruction, 194Loosely-coupled multiprocessor, 56,

551; see also Distributed-memorycomputer

LRU (least recently used) replacementpolicy, 447,449

LSI (large-scale integration), 36Lukasiewicz, Jan, 31

m-address machine, 179

M M 1 queueing model, 123Machine language, 19,202Macroinstruction (macro), 203,209Magnetic-disk memory, 42 1423Magnetic-surface recording, 420Magnetic-tape memory, 423Magneto-optical disk memory, 425Main memory, 3,51Mainframe computer, 33,40Manchester University, 19,530

Mantissa, 173Mask programming, 97Massachusetts Institute of Technology

(MIT), 19,530Massive parallelism, 56, 551Match circuit, 458, 568Matrix multiplication, 290Mauchly, John W., 17Mealy, G.H., 309Mealy machine, 309

Mean time before failure (MTBF), 407, 597575

INDEXMean time to failure (MTTF),572Mean time to repair (MTTR), 575Mechanical computers, 13-17ME1cache-coherence protocol, 585Memory

access mode of, 404associative, 457459cost of, 402,430external, 138,402hierarchical, 402,426main, 3,51, 116performance of, 402,429432random access, 117,404,407-418read only, 405

" secondary, 27,117,401serial access, 117,404,418-425types of, 400virtual, 428

Memory address register, 22Memory allocation, 443452

best-fit, 445first-fit, 445preemptive, 446

Memory fault, 447Memory hierarchy, 402,426Memory interference, 416

Memory management unit (MMU),160,432

Memory map, 433Memory mapping; see Address

translationMemory technology, 400-425Memory-mapped 10,139,505Mesh interconnection network, 490MESI cache coherence protocol, 555Message, 483

Message switching, 484Message-passing computer; see

Distributed-memory computerMFLOPS (millions of floating-point

operations per second), 548Microassembler, 332Microassembly language, 332Microcomputer, 37,40Microcontroller, 52

as IOP, 528


14/20

NDEX

Microinstruction, 306,332branch, 348horizontal, 337operate, 348parallelism in, 334-337timing of, 338vertical, 337

Micron Technology 64MbDRAM,412-415Microoperation, 306Microprocessor, 37 ,51, 115Microprogram, 34,306,332Microprogram counter, 337Microprogram sequencer, 341,357-361AMD 2909,341-344,352AMD 2910,352Texas Instruments 890,359-361

Microprogrammed control, 307,332

-

364,365Microprograrnming, 34dynamic, 334in Motorola 680x0 series, 160,363

Microsoft Corp., 41Microsoft productsMSJDOS operating system, 41

Windows, 41MTMD computer, 543MIN (multistage interconnectionnetwork), 560

-

567Minicomputer, 35,40MIPS (millions of instructions per

second), 45,121,371MIPS Computer Systems Inc., 182MIPS Computer Systems productsR10000 microprocessor, 389

R213000 microprocessor, 368,381-383,435,451

R4400 microprocessor, 575

RXOOO series, 182-

1 84, 197-

202MISD computer, 543Miss ratio, 430MITS Altair computer, 41MITS Inc., 41Modem (modulator-demodulator),483Monophase microinstruction, 339Moore, E.F., 309Moore, Gordon E., 60Moore machine, 309

Moore's law, 60MOS 1C technology, 38Motorola products

68020 microprocessor, 154-160,275,287

68040 microprocessor, 275,287-289

68060 microprocessor, 154680x0 microprocessor series, 41,154,179,205-208,514,520-522

68450 DMA controller, 51568851 MMU, 16068881 coprocessor, 15968882 coprocessor, 159,273-275,

287PowerPC 601 microprocessor, 371PowerPC 620 microprocessor, 468PowerPC microprocessor series, 41,47-

50,463,465MS1 (medium-scale integration), 36Multibus, 580Multichip module, 36Multicycling, 259Multimedia equipment, 42Multiple precision, 171,259Multiplexer, 87-90

as function generator, 87Multiplexing, 488,493

Multiplicationbit-sliced, 350-353Booth, 238-240,242-244,297fixed-point, 233-244floating-point, 266matrix, 290program for, '144pencil-and-paper, 233Robertson, 236-238,3 19-325,

344-353

Multiplier circuitcarry-save, 285combinational array, 240,244counter-based, 133hardwired control for, 319-325microprogrammed control for,344-353pipelined, 284-286sequential, sign-magnitude, 106,

110-1 14


15/20

Multiplier circuit-Cont.sequential, twos-complement,234-244,3 19-325,344-353Wallace tree, 285

Multiprocessor, 35,56,550-567l-D array, 539-541loosely-coupled, 551

scalability, of, 55 1Sequent Symmetry, 553Sequent Symmetry 5000,552shared-bus, 551-554symmetric, 551tightly-coupled, 551

Multiprogramming, 32Multistage interconnection network

(MIN), 560-567Mutual exclusion, 533,552

L'

NaN (not a number), 177Nanodata Corp., 362Nanodata QM-1 computer, 362Nanoinstruction, 362Nanoprogramming,361-3 64

in 68000 microprocessor, 363nCUBE Corp., 559nCUBE hypercube computers, 558Negative number codes, 168Network; see Computer network;

Interconnection networkNewton personal digital assistant,

150n-modular redundancy (nMR), 567Noise, 165,483Nonblocking network, 562Nondestructive readout (NDRO),405Nonweighted number code, 172Normalized number, 175Number format

fixed-point, 20, 167-173floating-point, 28, 173-178

Offset; see DisplacementOmega network, 561One-address instruction, 191One-hot design method, 308, 313-315Ones-complement code, 168

On-line transaction processing (OLTP), 599576 INDEX

Opcode, 179Open architecture, 41Open Systems Interconnection (OSI)

reference model, 485Operating system, 32,529-538

Atlas, 530DYNE, 554kernel of, 531MSDOS, 41Multics, 530Nonstop, 576OS/360,530UNIX, 530,536-538VMS, 532Windows, 41

OPT (optimal) replacement policy, 447Optical memory, 424Optimal algorithm, 71Orthogonality, 186Overflow

fixed-point, 170,227floating-point, 267

Packet, 54,485Packet switching, 54Page, 429,438Page frame, 438Page mode, memory access, 414Page size, 442Page table, 438PAL (programmable array logic),100Parallel computers, 384

classification of, 542-547performance of, 547-550

Parallel processing, 11,539-

551; seealso'~u1ti~rocessor;PipelineParallelism

instruction-level, 47, 539microinstruction-level, 334-337processor-level, 539

Parity bit, 165Pascal, Blaise, 13Pascal programming language, 29Patterson, David A., 181


16/20

00

NDEX

PC1(peripheral componentinterconnect) bus, 41,483,501-504

Performance, 8,42cache, 466measurement of, 44-47, 120-126,

371-373

memory, 402,429432parallel computer, 547-

550pipeline, 371-3 83

Personal computer (PC), 40-42Philips Semiconductor Corp., 529Physical address, 428Pipeline

4-bit serial adder, 109arithmetic, 275-292,364collision in, 374

control dependency in, 379-

381data dependency in, 382design of, 278-280feedback in, 280floating-point adder, 277-280hazard in, 379,382instruction, 364-37 1interrupts in, 522latency of, 276,376microinstruction, 308,365multifunction, 279multiplier, 284

-

286optimizing size of, 373performance of, 371-383space-time diagram for, 372two-stage, 365vector sum, 280-283

Pipeline, instruction, 149Pipeline processing, 275-292Pipelining, 35,45, 149PLA (programmable logic array), 98

PLD (programmable logic device),97-104

Point-of-sale (POS) terminal, 52Poisson, Sirnkon-Denis, 124Poisson process, 124Polish notation, 31Polyphase microinstruction, 339Pop instruction, 29,189,191Positional notation, 167Primary cache, 470

Princeton-class computer, 59Printed circuit board, 36Priority encoder, 91Privileged instruction, 34, 160Procedure, 3Process, 530,537Process control block, 532

Processor;see

CPU, IOPProcessor level, 40,71,114-126Processor-level design, 118-126Processor-level parallelism, 539Product-of-sums (POS) form, 75Program, 3,306Program control unit, 3,21

hardwired, 326-331microprogrammed, 354-364

Program counter, 21

Program execution, 145Program execution time, 45Program status word, 34Program-control instruction, 194Programmable array logic (PAL), 100Programmable logic array (PLA), 98Programmable logic device;see PLDProgrammable read-only memory;see

PROMProgrammed 10,504,505-511Programming language

assembly, 20high-level, 29machine, 19

PROM (programmable read-onlymemory), 99,405,415

Protocol, bus, 495Protocol, co&unication, 485Prototype design,119Pseudoinstruction;see DirectivePunched card, 16, 17

Push instruction, 29, 189, 191Pyramid graph, 580

Quantum Atlas I1hard-disk memory,422

Queueing model, 123-126M/M/l, 123of shared computer, 125

Queueing theory, 123


17/20

Radix, of number, 167RAID (redundant array of inexpensive

disks), 569-571RAM (random-access memory), 117,

404,407-41 8cached DRAM (CDRAM), 417d-dimensional, 408

design of, 411-415dynamic (DRAM), 37,406multiport, 258Rambus, 417semiconductor, 409411static (SRAM), 406,410synchronous DRAM (SDRAM), 417Rambus, 417

Random replacement policy, 451Random-access memory; see RAM "Read-only memory; see ROMRead

-write memory, 405

Real address, 428 ,431Receive instruction, 540,544Recovery, 568Redundancy, 567

dynamic, 568n-modular (nMR), 567static, 567triple modular (TMR), 567

Refreshing, of memory, 406,415Register, 83

parallel, 94shift, 95

Register file, 257,401Register level, 40 , 71Register renaming, 386Register-level components, 83Register-level design, 104-1 14Register-transfer language; see HDLRegister-transfer level, 40 ,71Relative addressing, 187Reliability, 571Replacement policy, 444,446-452

comparison of, 448FIFO (first-in first-out), 447, 449LRU (least recently used), 447,449OPT (optimal), 447random, 451simplified LRU (SLRU), 477stack, 449

Reservation station, 386Reservation table, 375Residual control, 339Resource allocation graph, 535Return address, 210Return instruction, 31,210Ring counter, 18

Ring network, 490RISC (reduced instruction setcomputer), 43, 179, 197

RISC 1 computer, 181Robertson, James E., 236,248Robertson multiplication algorithm,236-238ROM (read-only memory), 405,415

as function generator, 99Rounding, 171Round-off error, 170

Scalability,of multiprocessor, 551Scalar, 541Scientific notation, 173SCSI (Small Computer System

Interface) bus, 482SECDED code, 166,215Secondary cache, 470Secondary memory, 27,401Second

-

generation computer, 27Seek time, 418Segment, 437Segment descriptor, 437Segment table, 437Self-routing network, 566Semantic gap, 180Semaphore, 534,552Semiconductor technology, 32,

36-38

Send instruction, 540,544Sequent Computer Systems Inc., 543Sequent Symmetry computer, 543,552,

553Sequential circuit, 76,79-83Serial adder, 79, 102,224Serial-access memory, 117,404,

418 4 2 5magnetic disk, 421-423magnetic tape, 423

INDEX


18/20

EX

Serial-access memory-Cont.magneto-optical, 425optical, 424

Server, 54Set-associative addressing, 4 6 2 4 6 5Setup time, 77Shannon, ClaudeE., 66Shared bus, 97,489,491-504,544Shared-memory computer, 56,543Shift operation, 95Shift register, 95Shuffle connection, 563Shuffle-exchange network, 563Sign extension, 181Signed number codes, 168Significand, 173Sign-magnitude code, 168SIMD computer, 543

Simon, Herbert A., 72Simplex system, 568Simplified LRU (SLRU) replacement

policy, 477Simulator program, 71SISD computer, 543,551Slide rule, 1, 3Snooping, cache, 555Software compatible, 33Space utilization, 431

Space-time diagram, pipeline, 372Spatial locality, 429SPEC performance measure, 122,

467Speculative execution, 380,387Speedup

of parallel computer, 547of pipeline, 373

SRAM; see RAMSS1 (small-scale integration), 36Stack, 29, 148,210

in Motorola 680x0, 189Stack computer, 29Stack pointer, 31, 148, 189Stack replacement policy, 449Stage, pipeline, 276Star interconnection network,

490

State diagram, 129State table, 79,308

State transition graph, 129Static redundancy, 567Status register, 34, 147Storage; see MemoryStore and forward, 484,559Store instruction, 142Stored-program computer, 18,163Strobe signal, 497Structure, 65Subroutine, 209Subtracter, 225-227Subtraction

fixed-point, 225-227sign-magnitude, 295twos-complement, 226Sum-of-products (SOP) form, 75

Sun Microsystems computers,picoJava, 30SPARC, 43SuperSparc, 387

Supercomputer, 35,55Superscalar, 47,371,384Superscalar processing, 384-390Supervisor program, 139Supervisor state, 34, 160Sweeney, Dura W., 248Switch level, 39Switching element, 560,585

Switching network; see MINSymmetric multiprocessor, 551Synchronous circuit, 79Synchronous operation, 78Synthesis, 69Synthesis program, 71,76

Espresso, 82,321System, 64

hierarchical, 72System bus, 481

System design, 64System level, 40, 114System reliability, 572Systolic array, 290-292

Table lookup, 100Tag

address, in cache, 453in word, 164


19/20

Tandem computers,Himalaya series, 575-578Nonstop series, 575VLX, 575

Tandem Computers Inc., 576Task-initiation diagram (TID), 378TCPJIP (Transmission Control

ProtocoVInternetProtocol), 54,487 '

Technology independence, 40Temporal locality, 429Test-and-set instruction, 533Texas Instruments products

888 8-bit ALU, 35988X microprocessor series, 359890 microprogram sequencer,

359-361

Third-

generation computer, 32Thrashing, 444Three-address instruction, 191Throughput, 371Tightly-coupled multiprocessor,

551; see also Shared-memorycomputer

Time-sharing system, 32Timing diagram, 495Timing, of bus, 4 9 5 4 9 8TMR (triple

-

modular redundancy), 567,573TMWSimplex,587

Tocher, Keith D., 248Token, 487Token-passing network, 487Tomasulo, R. M., 386Tomasulo's algorithm, 386Top-down design, 73Tractable problem, 8

Transistor, 27Translation look-aside buffer (TLB),

435Trap, 201,273,520Traveling salesman problem, 10, 12Tree computer, 545Tristate buffer, 493Tristate logic, 493-495Truncation,171Truth table, 65

Turing, Alan M., 5

Turing machine, 5, 193addition program for, 6halting problem for, 8universal, 7

Two-address instruction, 191Two-level circuit, 75Two-out-of-five code, 172

Twos-

complement code, 168, 182Type declaration, 164

INDEX

UMA (uniform-memory access)computer, 551

Unary number, 6Undecidable problem, 8Underflow

fixed-point, 170

floating-

point, 267Uniprocessor, 551U.S. Department of Defense, 29 ,54 ,67UNIVAC computer, 19Universal asynchronous receiver-

transmitter (UART), 5 11University of California, Berkeley, 43,

181University of Illinois, 561University of Michigan, 558

University of Pennsylvania, 18UNIX operating system, 530,536-

538User program, 139User state, 34

Vacuum tube, 27Vector, 83,541Vector addition program

for 680XO,156-158,205-208for IAS computer, 25 ,50for PowerPC, 48

-

50in FORTRAN, 29

Vector instruction, 283Vector processor, 55,283Vector sum pipeline, 280-283Vectored interrupt, 5 17-520Verilog, 67, 127Vertical microinstruction, 337Very long instruction word (VLIW),

398


20/20

NDEX

VHDL, 67-69Virtual address, 428,431Virtual memory, 160,428VLSI (very large-scale integration), 35,

36Volatile memory, 406von Neumann, John, 18

von Neumann bottleneck, 43,403,452von Neumann computer, 27,51Voter, 567

Wilkes design scheme, 333Word, 20,34, 83, 161Word gate, 86Word-basedBoolean algebra, 85Working set, 429Workstation, 40World Wide Web, 55,488

Writablecontrol memory, 334Write back, cache, 456Write through, cache, 457

Wait state, 496 Zero extension, 182Wallace tree, 285 Zero-address machine, 191Watchdog timer, 511 Zero-detection circuit, 38Whirlwind computer, 19 Zilog Z80 microprocessor, 508Wide-area network(W&), 484 Zuse, Konrad, 17Wilkes, Maurice

V.,34,333 Zuse's computers, 17

Table of Contents 135250

Documents

Transcript of Table of Contents 135250