Table of Content Revision History Sheets/NXP PDFs... · 2018-01-04 · Change D1702,D1703...
23
5 5 4 4 3 3 2 2 1 1 D D C C B B A A A USB Table of Content Cover Block Diagram Page 1 Page 2 Page 3 Page 4 Page 5 Page 6 Page 7 Page 8 Page 9 Page 10 Page 11 Page 12 Page 13 Page 14 Page 15 Page 16 Page 17 Page 18 Page 19 Page 20 Page 21 Revision History Rev. Code Date Description By MCIMX8M-EVK MCIMX8M-EVK MCIMX8M-EVK MCIMX8M-EVK Page 22 1. Unless Otherwise Specified: All resistors are in ohms, 10%, 1/8 Watt,0603 All capacitors are in uF, 20%, 50V,0603 All voltages are DC All polarized capacitors are aluminum electrolytic 2. Interrupted lines coded with the same letter or letter combinations are electrically connected. 3. Device type number is for reference only. The number varies with the manufacturer. 4. Special signal usage: _B Denotes - Active-Low Signal <> or [] Denotes - Vectored Signals 5. Interpret diagram in accordance with American National Standards Institute specifications, current revision, with the exception of logic block symbology. Page 23 Page 24 Page 25 CPU PWR Schematics DevBoard Page 26 Page 27 Page 28 Page 29 PWR TREE 2016-12-09 Javen Revision preliminary version 1 LPDDR4 eMMC/NAND/TF/QSPI CPU IO CPU PHY BOOT CFG PMIC HDMI CODEC WiFi/BT Ethernet Debug MicroSD/IR/LED/BTN MIPI/DSI/CSI EXP CN NOTE IOMUX CPU MISC PCIe (mScale850 Customer Board) A1 2017-05-26 Javen Change J1401 M.2 connector from sink type to non-sink type 1 Update U1001 schematic lib 2 3 4 Add R760 to control the VDD_SNVS_0V9 power up sequence DNP D903, R915, change R936 to 44.2K, Add R942,R943,D910 5 6 Change R715 to 10K, add R761 44.2K OHM/0402,C799 1uF/0402 7 Add Q1402-Q1404, R1458-R1462, C1439-C1441 to prevent current drop during power up due to CAP,DNP C1418,C1419 Add R1802, R1803 to keep VIO voltage for IO REF 8 9 J801 change to femal header 10 Change D1702,D1703 connection to reduce the CP2105 Program step 11 Change R934 to 1K OHM 12 Add R845,R846 for backup 13 Add C779,C929~C932 J1201 PIN2 change to 2.5V Add R510,R511,R512,R513 as back up of different HCSL OSC 14 15 Exchange UART1 and UART2 on CP2105 due to ECI support special input DNP R909,R910,R911,R912, Install R905,R906,R907,R908 16 17 Add L104 FB for PLL to reduce noise 18 Add R764,Q704,R763 to support over drive mode B1 2017-07-24 Javen Change WiFi to QCA6174A 1 2 Change USB TYPE-C connector 3 Change R1004,R1009 PU to DCDC_5V_CN 4 Add C714 to prevent ARM voltage drop when DVFS from 1.0V to 0.9V 5 DNP R1227 DNP C727 add C781 to prevent the power up sequence Javen 2017-08-14 B2 1 Add C781 2 Add R1464, D1404, D1405 for WiFi enable backup Add R1437,Q1405,R1463,D1403,D403 Change R1459 to PCIe_nDIS Install R1411,R1442-R1449,C401 Change C913 to 1nF Change R842 to 1M OHM 6 7 8 9 10 11 DNP D1609 to prevent the SDIO power on later than POR_B 3 4 Install R409 4.7K, change R401 to 0 OHM 5 Add R621 for backup Drawing Title: Size Document Number Rev Date: Sheet of Page Title: Designer: Drawn by: Approved: Microcontroller Product Group 6501 William Cannon Drive West Austin, TX 78735-8598 This document contains information proprietary to NXP and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors. ICAP Classification: CP: IUO: PUBI: SCH-29615 PDF: SPF-29615 B1 mScale850 EVK C Monday, September 25, 2017 Title and Rev History <JW> <Approver> <JW> 1 23 ___ _X_ ___ Drawing Title: Size Document Number Rev Date: Sheet of Page Title: Designer: Drawn by: Approved: Microcontroller Product Group 6501 William Cannon Drive West Austin, TX 78735-8598 This document contains information proprietary to NXP and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors. ICAP Classification: CP: IUO: PUBI: SCH-29615 PDF: SPF-29615 B1 mScale850 EVK C Monday, September 25, 2017 Title and Rev History <JW> <Approver> <JW> 1 23 ___ _X_ ___ Drawing Title: Size Document Number Rev Date: Sheet of Page Title: Designer: Drawn by: Approved: Microcontroller Product Group 6501 William Cannon Drive West Austin, TX 78735-8598 This document contains information proprietary to NXP and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors. ICAP Classification: CP: IUO: PUBI: SCH-29615 PDF: SPF-29615 B1 mScale850 EVK C Monday, September 25, 2017 Title and Rev History <JW> <Approver> <JW> 1 23 ___ _X_ ___
Transcript of Table of Content Revision History Sheets/NXP PDFs... · 2018-01-04 · Change D1702,D1703...
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C C
B B
A A
A
USB
Table of Content
Cover
Block Diagram
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
Page 9
Page 10
Page 11
Page 12
Page 13
Page 14
Page 15
Page 16
Page 17
Page 18
Page 19
Page 20
Page 21
Revision History
Rev. Code Date DescriptionBy
MCIMX8M-EVKMCIMX8M-EVKMCIMX8M-EVKMCIMX8M-EVK
Page 22
1. Unless Otherwise Specified:
All resistors are in ohms, 10%, 1/8 Watt,0603
All capacitors are in uF, 20%, 50V,0603
All voltages are DC
All polarized capacitors are aluminum electrolytic
2. Interrupted lines coded with the same letter or letter combinations are electrically connected.
3. Device type number is for reference only. The number varies with the manufacturer.
4. Special signal usage:
_B Denotes - Active-Low Signal
<> or [] Denotes - Vectored Signals
5. Interpret diagram in accordance with American National Standards Institute specifications, current revision, with the exception of logic block symbology.
Page 23
Page 24
Page 25
CPU PWR
Schematics DevBoard
Page 26
Page 27
Page 28
Page 29
PWR TREE
2016-12-09 Javen Revision preliminary version1
LPDDR4
eMMC/NAND/TF/QSPI
CPU IO
CPU PHY
BOOT CFG
PMIC
HDMI
CODEC
WiFi/BT
Ethernet
Debug
MicroSD/IR/LED/BTN
MIPI/DSI/CSI
EXP CN
NOTE
IOMUX
CPU MISC
PCIe
(mScale850 Customer Board)
A12017-05-26 Javen Change J1401 M.2 connector from sink type to non-sink type1
Update U1001 schematic lib2
3
4
Add R760 to control the VDD_SNVS_0V9 power up sequence
DNP D903, R915, change R936 to 44.2K, Add R942,R943,D910
5
6
Change R715 to 10K, add R761 44.2K OHM/0402,C799 1uF/0402
7
Add Q1402-Q1404, R1458-R1462, C1439-C1441 to prevent current drop during power up due to CAP,DNP C1418,C1419
Add R1802, R1803 to keep VIO voltage for IO REF
8
9
J801 change to femal header
10
Change D1702,D1703 connection to reduce the CP2105 Program step
11
Change R934 to 1K OHM
12
Add R845,R846 for backup
13
Add C779,C929~C932
J1201 PIN2 change to 2.5V
Add R510,R511,R512,R513 as back up of different HCSL OSC 14
15 Exchange UART1 and UART2 on CP2105 due to ECI support special input
DNP R909,R910,R911,R912, Install R905,R906,R907,R90816
17 Add L104 FB for PLL to reduce noise
18 Add R764,Q704,R763 to support over drive mode
B1 2017-07-24 Javen Change WiFi to QCA6174A1
2 Change USB TYPE-C connector
3 Change R1004,R1009 PU to DCDC_5V_CN
4 Add C714 to prevent ARM voltage drop when DVFS from 1.0V to 0.9V
5 DNP R1227
DNP C727 add C781 to prevent the power up sequence
Javen2017-08-14B2 1 Add C781
2 Add R1464, D1404, D1405 for WiFi enable backup
Add R1437,Q1405,R1463,D1403,D403
Change R1459 to PCIe_nDIS
Install R1411,R1442-R1449,C401
Change C913 to 1nF
Change R842 to 1M OHM
6
7
8
9
10
11
DNP D1609 to prevent the SDIO power on later than POR_B3
4 Install R409 4.7K, change R401 to 0 OHM
5 Add R621 for backup
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
Title and Rev History
<JW>
<Approver>
<JW>
1 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
Title and Rev History
<JW>
<Approver>
<JW>
1 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
Title and Rev History
<JW>
<Approver>
<JW>
1 23
____X____
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
mScale850 EVK Block Diagram
eMMC 16GB:MTFC16GAKAECN-2M WT
Qualcomm: AR8031
Dsiplaymini-SAS CN
MIPI-DSI 4-lane
x32
MIPI-DSI
RCA CN
HD
MI IN
2
HD
MI IN
3
HD
MI IN
4
HD
MI IN
1
HD
MI O
UT
From CPU board HDMI OUT
SAI1 RX
JTAG10 PIN Header
JTAG
JTAG
RCA CN
RCA+OPT
##### Block Diagram Rev 0.6 #####
CameraMIPI/CSI x2
NXP PMIC PF4210
PMICPOWER
mScale850
PCIe/UART/PCM
NAND/QSPI
NXP
Audio DACWM8524
MicroSD
x2 USB 3.0
QSPI
eMMC 5.0/MicroSDFootprint Co-layoutSDIO
DRAM
HDMI
USB OTG x2
SDIO
MIC HSLHSRGND
3.5mm POLE
SAI
RGMII
Infrared/LED
GPIO/PWM
x1 USB 3.0 TYPE-Ax1 USB TYPE-C
16-CH LINE OUT
AK4458 (8-CH DAC) x2
SAI1 TXTDMI2C
SPDIF TX/RX
Debug UARTUART->USB CP2105
HDMI 2.0aTYPE-A
LPDDR4 (200b)Micron 768 Meg x 32
HDMI Switch/Receiver
USB
SPDIF
UART
Exp C
N
GPIO/PWM
MIMO 2x2 / BT4.1
WiFi/BT
Audio Jack
RJ45Gigabit Ethernet
SD3.0
ButtonONOFF, RST
# Audio Card
x2 UART(A53/M4)
ONOFF/RST
108dB 216kHz 32Bit DELTA-SIGMA CODEC115dB 768kHz 32-bit 8ch Premium DAC
8-CH LINE IN
AK5558 (8-CH ADC)
SAI1 RXTDMI2C
ADI: ADV7627
32-Bit 2ch DAC
Ref Stereo Output
AK4497EQ
SAI3
NANDFQSPI 256Gb: Micron MT25QL256ABA1EW9
mini-SAS CN
Quad ARM Cortex-A53/M4
x8
# SOM Board
MCIMX8M-EVK
MCIMX8M-AUD
SAI2
M.2 KEY-EPCIe
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
Block Diagram
<JW>
<Approver>
<JW>
2 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
Block Diagram
<JW>
<Approver>
<JW>
2 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
Block Diagram
<JW>
<Approver>
<JW>
2 23
____X____
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MCIMX8M-EVK Board PWR TREE
3.3V/8A
MPS MP8759GD
DCDC BUCK
DC IN (12V)
USB TYPE-C (5-20V)
VSYS
PMIC: PF4210
SEQ
2
4445
66
77777
PWR
VDD_SNVS
SW1A/BSW1CSW3A/BVGEN4
SW4SW2
VGEN3VGEN2VGEN5VGEN1VGEN6
TYP
0.9
0.90.91.01.8
1.81.1
1.80.93.31.52.8
Curr(mA)
2
250020003000350
10002500
100250100100200
CPU: i.MX8M (mScale850)
SEQ12RTC_RESET_B34444556666
777POR_B
PWRNVCC_SNVSVDD_SNVS
VDD_SOC/VDDA_0P9VDD_ARMVDD_GPUVDD_VPUVDD_DRAMVDDA_1P8_xxxVDDA_DRAMNVCC_3V3NVCC_1V8NVCC_DRAMNVCC_SD2
1.8V PHY0.9V PHY3.3V PHY
TYP3.30.9
0.90.9/1.00.9/1.00.9/1.01.01.81.83.31.81.1/1.2/1.351.8/3.3
1.80.93.3
Curr(mA)22
3600400020001000250025050150100700
50250100
0.9V/300mA
AP7343D
LDO
0.9V/4A
MPS MP2147
DCDC BUCK
0.9V/4A
MPS MP2147
DCDC BUCK
3.3V
LdSW
1.8/3.3V/150mA
LDCL015MR
LDO
5V/3A
MPS MP2263
DCDC BUCK
LPDDR4
QSPI
eMMC/MicroSD
Ethernet AR8031
WiFi/BT
Audio DAC
MicroSD
HDMI
mini-SAS (MIPI CSI/DSI)
M.2 PCIe
USB Host/Type-C
VDD1VDD2/VDDQ
VCC
VCCQVCC
AVDD33
VBATVIO
AVDD/LINE VDD
VCC
5V
1.8V3.3V5V
3.3V
VBUS
PTN36043
M850-AUDIO BOARD
(5-20V)
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
Custom
Monday, September 25, 2017
Power Tree
<JW>
<Approver>
<JW>
3 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
Custom
Monday, September 25, 2017
Power Tree
<JW>
<Approver>
<JW>
3 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
Custom
Monday, September 25, 2017
Power Tree
<JW>
<Approver>
<JW>
3 23
____X____
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
mScale850 PWR
GNDGND
NVCC_DRAM_1V1
VDDA_1V8
NVCC_SNVS_3V3VDD_SNVS_0V9
VDD_SOC_0V9
NVCC_3V3
NVCC_ENET_2V5
GND
GND
VDD_PHY_1V8
GND
GNDGND
VDD_PHY_1V8VDD_PHY_0V9
GND
GND
VDD_PHY_3V3
VDD_PHY_0V9
VDD_PHY_3V3
GND
VDD_PHY_0V9
GND
NVCC_SD2NVCC_SD1_1V8
GND
GND
GND
GND
GND
GND
VDD_PHY_0V9
GND
GND
NVCC_SAI2_3V3NVCC_SAI3_3V3NVCC_SAI5_3V3NVCC_I2C_3V3NVCC_ECSPI_3V3
NVCC_JTAG_3V3
NVCC_SAI1_3V3
NVCC_UART_3V3NVCC_GPIO_3V3
NVCC_NAND_3V3
VDD_3V3
NVCC_SD2
NVCC_3V3
GND
VDD_ARM_0V9
VDD_GPU_0V9
VDD_VPU_0V9
GND
GND
GND
GND
VDD_DRAM_0V9
GND
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
CPU PWR
<JW>
<Approver>
<JW>
4 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
CPU PWR
<JW>
<Approver>
<JW>
4 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
CPU PWR
<JW>
<Approver>
<JW>
4 23
____X____
C1950.1uF10V
C1341uF6.3V
C1900.1uF10V
C1551uF6.3V
C241uF6.3V
C1131uF6.3V
C1722uF10V
C1621uF6.3V
C1154700PF10V
C1780.1uF10V
C1520.1uF10V
C1191uF6.3V
C1041uF6.3V
C1860.1uF10V
C1020.1uF10V
C1470.1uF10V
C1631uF6.3V
C200.1uF10V
C42.2uF10V
C122.2uF10V
C30.1uF10V
C1144700PF10V
C16922uF10V
L104
240 OHM
12
C1384700PF10V
C271uF6.3V
C17222uF10V
C1480.1uF10V
C17022uF10V
C1960.1uF10V
C1374700PF10V
C80.1uF10V
MiMX8MQ7DVAJZxA + MBF25004-15W/2.0P+T725 A1
U101M
VDD_DRAM14Y8 VDD_DRAM13Y6
VDD_DRAM15Y20
VDD_DRAM16Y18
VDD_DRAM17Y16
NVCC_DRAM17Y14
NVCC_DRAM18Y12
VDD_DRAM18Y10
VDD_SNVSR18
VDDA_1P8_XTAL_25MW24 VDDA_1P8_XTAL_27MW23
NVCC_SNVSW18
VDDA_1P8_FPLLU17
VDD_SOC1R8
NVCC_JTAGW4
VDD_DRAM1V9
VDD_DRAM2V15
VDD_DRAM3V14
VDD_DRAM4V13
VDD_DRAM5V12
VDD_DRAM6V11
VDD_DRAM7V10
VDD_SOC2R9
VDDA_1P8_LVDSU23
VDD_DRAM8U11
VDD_DRAM9U14
VDD_DRAM10U12
VDD_DRAM11U10
VDD_SOC3R10
HDMI_AVDDCORE2U3
HDMI_AVDDCORE1U4
VDD_SOC4R11
VDDA_1P8_TSENSORT16
VDD_ARM1G15
VDD_DRAM12U13
VDDA_1P8_SPLLW17
VDD_VPU1N8
NVCC_GPIO2R6NVCC_GPIO1R5
HDMI_AVDDCLKV3
NVCC_ENETT18
EFUSE_VQPSR17
VDD_ARM2H15
VDD_SOC5R12
VDD_VPU2N9
VDD_SOC6R13
HDMI_AVDDIOP2
VDD_SOC7R14
VDD_ARM3J15
VDD_ARM4K15
VDD_VPU3N10
VDD_VPU4P9
NVCC_SD2N23
VDD_SOC8R15
VDD_ARM5L15
VDD_SOC9R16
VDD_SOC10T8
NVCC_SAI5M3
VDD_SOC11K12
VDD_ARM6M15
VDD_ARM7G16
VDD_SOC13M12
VDD_VPU5P10
VDD_GPU1J9
NVCC_SAI1_1L3
NVCC_SD1_2L23
VDD_ARM8H16
VDD_SOC15P12
VDD_GPU2K9
NVCC_SAI1_2K3
NVCC_NAND2M18
VDD_ARM9J16
VDD_ARM10K16
VDD_GPU3L9
VDD_GPU4M9
PCIE_VPH2J23
NVCC_NAND1L18
VDD_SOC19N13
VDD_SOC17L13
VDD_SOC12L12
VDD_SOC21T17 VDD_SOC20P13
NVCC_I2CH7
NVCC_SAI2J7
PCIE_VPH1H23
VDD_GPU5J10
PCIE_VPTX1G23
PCIE_VP1G22PCIE_VPTX2F23
PCIE_VP2F22
MIPI_VDDHA3D18MIPI_VDDHA2D17MIPI_VDDHA1C18
USB1_VDD33G12
USB2_VDD33G11
NVCC_ECSPIF5
MIPI_VDDA2E18MIPI_VDDA1E17
MIPI_VDDA3F17
MIPI_VDDPLLF19
USB1_VPHF12
USB1_DVDDE12
USB2_VPHF11
USB2_DVDDE11
NVCC_UARTD8
NVCC_SAI3E3
MIPI_VDDA4F18
USB1_VPD12
USB2_VPD11
USB1_VPTXC12
USB2_VPTXC11
NVCC_DRAM16AD5
NVCC_DRAM14AD21
NVCC_DRAM15AD18
NVCC_DRAM12AC8
NVCC_DRAM13AC6
NVCC_DRAM10AC3
NVCC_DRAM11AC23
NVCC_DRAM9AC20 NVCC_DRAM8AC17 NVCC_DRAM7AC14
NVCC_DRAM5AB8
NVCC_DRAM6AB3
NVCC_DRAM1AB23
NVCC_DRAM3AB17
NVCC_DRAM4AA15
VDDA_DRAMAA11
NVCC_DRAM2AA10
NVCC_SD1_1M23
VDD_SOC18M13
VDD_ARM11L16
VDD_ARM12M16
VDD_ARM13G14
VDD_ARM14H14
VDD_GPU6K10
VDD_GPU7L10
VDD_GPU8M10
MIPI_VDD1E15
MIPI_VDD2F15
VDDA_0P9V18
VDDA_1P8_SPLL_DRAMT15
VDD_SOC14P16
VDD_SOC16P15
VDDA_1P8_FPLL_ARMK14
VDDA_1P8_SPLL_VIDEO2N11
C11622uF10V
C1011uF6.3V
C1261uF6.3V
C1910.1uF10V
C1294700PF10V
C281uF6.3V
C1391uF6.3V
C1170.01UF6.3V
C1031uF6.3V
C211uF6.3V
C16622uF10V
C1201uF6.3V
C1810.1uF10V
C102.2uF10V
L101
120OHM
21
C321uF6.3V
C1401uF6.3V
C221uF6.3V
C334700PF10V
C351uF6.3V
C1870.1uF10V
C1970.1uF10V
C52.2uF10V
C92.2uF10V
C17622uF10V
C1111uF6.3V
C1271uF6.3V
C1300.01UF6.3V
C1091uF6.3V
C1354700PF10V
C1231uF6.3V
C1561uF6.3V
C361uF6.3V
C1790.1uF10V
C1211uF6.3V
C311uF6.3V
C1490.1uF10V
C17422uF10V
C1820.1uF10V
C1930.1uF10V
C17522uF10V
C1601uF6.3V
C1364700PF10V
C1281uF6.3V
C1571uF6.3V
C1980.1uF10V
C190.1uF10V
C1051uF6.3V
C1441uF6.3V
C1311uF6.3V
C1990.1uF10V
C1221uF6.3V
C341uF6.3V
C112.2uF10V
C1771uF6.3V
C16822uF10V
C1800.1uF10V
C1451uF6.3V
C1880.1uF10V
C1822uF10V
C72.2uF10V
U101N
MiMX8MQ7DVAJZxA + MBF25004-15W/2.0P+T725 A1
VSS1B25
VSS2C8
VSS3C10
VSS4C13
VSS5C15
VSS6A24
VSS7C24
VSS8D10
VSS9D13
VSS10D15
VSS11D23
VSS12A2
VSS13E4
VSS14E10
VSS15E13
VSS16E14
VSS18E16
VSS19E19
VSS20E21
VSS21E22
VSS22E23
VSS23F10
VSS24F13
VSS25F14
VSS27F16
VSS28G9
VSS29G10
VSS30G13
VSS31G17
VSS32G18
VSS33G24
VSS34H8
VSS35H9
VSS36H10
VSS37H11
VSS38H12
VSS39H13
VSS40H17
VSS41H18
VSS42J3
VSS43B1
VSS44J8
VSS45J11
VSS46J12
VSS47J13
VSS48J14
VSS49J17
VSS50J18
VSS51J19
VSS52K8
VSS53K11
VSS55K17
VSS56K18
VSS57K23
VSS58L8
VSS59L11
VSS60L14
VSS61L17
VSS62M8
VSS63M11
VSS64M14
VSS65M17
VSS66N3
VSS68N14
VSS69P6
VSS70P8
VSS71P11
VSS72P14
VSS75P17VSS76P18VSS77P23VSS78R7VSS79W9VSS80T3VSS81T4VSS82T9VSS83T10VSS84T11VSS85T12VSS86T13
VSSA_SPLL_DRAMT14
VSS89U8VSS90U9VSS91U15VSS92U18VSS93V4VSS94V8VSS95V16
VSS97W1VSS98W7VSS99W8VSS100W10VSS101W11VSS102W12VSS103W13VSS104W14VSS105W15VSS106W16VSS107W25VSS108Y2VSS109Y3VSS110Y4VSS111Y5VSS112Y7VSS113Y9VSS114Y11VSS115Y13VSS116Y15VSS117Y17VSS118Y19VSS119Y21VSS120Y22VSS121Y23VSS122Y24VSS123AA5VSS124AA16VSS125AA21VSS126AB2VSS127AB9VSS128AB11VSS129AB18VSS130AB24VSS131AC4VSS132AC19VSS133AC22VSS134AD1VSS135AD7VSS136AD9VSS137AD11VSS138AD13VSS139AD16VSS140AD25VSS141AE2
VSSA_XTAL_25MV23
VSSA_XTAL_27MW22
VSS87AE5VSS88AE21
VSS96AE24
VSS17E20
VSS26F20
VSS54N18
VSS67N17
VSS73N16VSS74N15
VSSA_FPLLU16VSSA_FPLL_ARMK13
VSSA_SPLL_VIDEO2N12
VSSA_SPLLV17
C1500.1uF10V
C16722uF10V
C1241uF6.3V
C1830.1uF10V
C1940.1uF10V
C16522uF10V
C1840.1uF10V
C1581uF6.3V
C1321uF6.3V
C146
1uF 6.3V
C10.1uF10V
C1061uF6.3V
C1531uF6.3V
C17122uF10V
C1334700PF10V
C1251uF6.3V
C1890.1uF10V
C1641uF6.3V
C1622uF10V
C231uF6.3V
C17322uF10V
C1510.1uF10V
R101 0 DNP5%
C62.2uF10V
C1104700PF10V
C1084700PF10V
C1522uF10V
C1850.1uF10V
C1181uF6.3V
C1121uF6.3V
C291uF6.3V
C1422uF10V
C1591uF6.3V
C1920.1uF10V
C1322uF10V
C1071uF6.3V
C1541uF6.3V
C20.1uF10V
C1611uF6.3V
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LPDDR4
1.70-1.95V
1.06-1.17V
1.06-1.17V
DRAM VREF# Note: 1K/1.5K are OK
Power supply voltage ramp:
RESET_n is held LOW. VDD1 >= VDD2 VDD2 >= VDDQ
VDD_1V8
GND
NVCC_DRAM_1V1
GND
GND
DRAM_VREF
GND
GND
NVCC_DRAM_1V1
NVCC_DRAM_1V1
NVCC_DRAM_1V1
NVCC_DRAM_1V1
GND
GND
GND
GND
GND GND
DRAM_VREF
GND
NVCC_DRAM_1V1
GND
VREFDDR Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
LPDDR4
<JW>
<Approver>
<JW>
5 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
LPDDR4
<JW>
<Approver>
<JW>
5 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
LPDDR4
<JW>
<Approver>
<JW>
5 23
____X____
R2150
C2154.7uF6.3V
C2044.7uF6.3V
C2144.7uF6.3V
C2054.7uF6.3V
R2021501%
C2094.7uF6.3V
C20122uF10V
MT53B768M32D4NQ-062 WT:B
U201A
CA0_AH2
CA0_BR2
CA1_AJ2
CA1_BP2
CA2_AH9
CA2_BR9
CA3_AH10
CA3_BR10
CA4_AH11
CA4_BR11
CA5_AJ11
CA5_BP11
CK_c_AJ9
CK_c_BP9
CK_t_AJ8
CK_t_BP8
CKE0_AJ4
CKE0_BP4
CKE1_AJ5
CKE1_BP5
CS0_AH4
CS0_BR4
CS1_AH3
CS1_BR3
DMI0_AC3
DMI0_BY3
DMI1_AC10
DMI1_BY10
DNU_A1A1DNU_A2A2DNU_A11A11DNU_A12A12DNU_B1B1DNU_B12B12DNU_AA1AA1DNU_AA12AA12DNU_AB1AB1DNU_AB2AB2DNU_AB11AB11DNU_AB12AB12
DQ0_AB2
DQ0_BAA2
DQ1_AC2
DQ1_BY2
DQ2_AE2
DQ2_BV2
DQ3_AF2
DQ3_BU2
DQ4_AF4
DQ4_BU4
DQ5_AE4
DQ5_BV4
DQ6_AC4
DQ6_BY4
DQ7_AB4
DQ7_BAA4
DQ8_AB11
DQ8_BAA11
DQ9_AC11
DQ9_BY11
DQ10_AE11
DQ10_BV11
DQ11_AF11
DQ11_BU11
DQ12_AF9
DQ12_BU9
DQ13_AE9
DQ13_BV9
DQ14_AC9
DQ14_BY9
DQ15_AB9
DQ15_BAA9
DQS0_c_AE3
DQS0_c_BV3
DQS0_t_AD3
DQS0_t_BW3
DQS1_c_AE10
DQS1_c_BV10
DQS1_t_AD10
DQS1_t_BW10
NC_G11G11
NC_K5K5
NC_K8K8
NC_N5N5
NC_N8N8
ODT_CA_AG2
ODT_CA_BT2
RESET_NT11
ZQ0A5
ZQ1A8
i.MX8M - DDR(LPDDR4/DDR4/DDR3)
MiMX8MQ7DVAJZxA + MBF25004-15W/2.0P+T725 A1
U101A
DRAM_DQ05Y25
DRAM_DQ21Y1
CA1_B / CAS_n(A15) / CAS#AE9 CA0_B / C2 / --AE8
CA3_B / BA0 / BA0AE7
CA4_B / A10(AP) / A10(AP)AE6
DRAM_DQ18AE4
DRAM_DQ16AE3
DRAM_DQ00AE23
DRAM_DQ02AE22
CA3_A / A8 / A8AE20
CA5_A / A5 / A5AE19
CS0_A / CS0_n / CS0#AE18
CKE1_A / CKE1 / CKE1AE17
CA1_A / A11 / A11AE16
CK_c_A / BG1 / A14AE14
CK_c_B / A1 / A1AE12
CKE1_B / CK_c_B / CK#_BAE10
CS1_B / -- / --AD8
CA5_B / A0 / A0AD6
DRAM_DQ19AD4
DRAM_DM2AD3
DRAM_DQ01AD24
DRAM_DM0AD23
DRAM_DQ03AD22CA2_A / A7 / A7
AD20
DRAM_DQ17AD2
CA4_A / A6 / A6AD19
CA0_A / A12 / A12(BC#)AD17
CK_t_A / BG0 / BA2AD14
CK_t_B / A2 / A2AD12
CKE0_B / CK_t_B / CK_BAD10
CS0_B / -- / --AC9
CA2_B / A13 / A13AC7
DRAM_DQS3_NAC5
DRAM_DQS0_NAC25DRAM_DQS0_PAC24
DRAM_DQS1_NAC21
DRAM_DQS2_PAC2
CS1_A / C0 / --AC18
CKE0_A / CKE0 / CKE0AC16
MTEST1 / MTEST1(ALERT_n) / MTEST1AC13
DRAM_DQS2_NAC1
DRAM_DQ29AB7
DRAM_DM3AB6
DRAM_DQS3_PAB5
DRAM_DQ24AB4
DRAM_DQ07AB25
DRAM_DQ08AB22
DRAM_DQS1_PAB21
DRAM_DM1AB20
DRAM_DQ13AB19
-- / A4 / A4AB16
MTEST / MTEST / MTESTAB14
RESET_n / RESET_n / RESET#AB13
DRAM_DQ23AB1
DRAM_DQ31AA9
DRAM_DQ28AA8
DRAM_DQ30AA7
DRAM_DQ27AA6
DRAM_DQ25AA4
DRAM_DQ26AA3
DRAM_DQ06AA25
DRAM_DQ04AA24
DRAM_DQ10AA23DRAM_DQ09AA22
DRAM_DQ11AA20
DRAM_DQ20AA2
DRAM_DQ14AA19
DRAM_DQ12AA18
DRAM_DQ15AA17
VREF / VREF / VREFAA14
ZQ / ZQ / ZQAA13
DRAM_DQ22AA1
-- / WE_n(A14) / WE#AC10
-- / PARITY / --AA12
-- / RAS_n(A16) / RAS#AB10
-- / BA1 / BA1AB12
-- / A9 / A9AB15
-- / CS1_n / CS1#AC11
-- / ODT0 / ODT0AC12
-- / A3 / A3AC15
-- / CK_c_A / CK#_AAD15
-- / ODT1 / ODT1AE11
-- / ACT_n / A15AE13
-- / CK_t_A / CK_AAE15
C2104.7uF6.3V
R2091.5k0.1%DNP
C2024.7uF6.3V
TP201
R2101.5k0.1%DNP
C2034.7uF6.3V
TP202
C2134.7uF6.3V
C2160.1uF50V
C20622uF10V
R208 10K 5%
C2190.1uF
DNP50V
R203 240 1%
C2180.1uF
DNP50V
MT53B768M32D4NQ-062 WT:B
U201B
VDD2_R8R8
VDD1_F1F1
VDD1_F12F12
VDD1_G4G4
VDD1_G9G9
VDD1_T4T4
VDD1_T9T9
VDD1_U1U1
VDD1_U12U12
VDD2_A4A4
VDD2_A9A9
VDD2_F5F5
VDD2_F8F8
VSS_AB8AB8
VDD2_AB4AB4
VSS_AB5AB5
VSS_AB10AB10
VDD2_AB9AB9
VDD2_H1H1
VDD2_H5H5
VDD2_H8H8
VDD2_H12H12
VDD2_K1K1
VDD2_K3K3
VDD2_K10K10
VDD2_K12K12
VDD2_N1N1
VDD2_N3N3
VDD2_N10N10
VDD2_N12N12
VDD2_R1R1
VDD2_R5R5
VDDQ_B3B3
VDDQ_B5B5
VDDQ_B8B8
VDDQ_B10B10
VDDQ_D1D1
VDDQ_D5D5
VDDQ_D8D8
VDDQ_D12D12
VDDQ_F3F3
VDDQ_F10F10
VDDQ_U3U3
VDDQ_U10U10
VDDQ_W1W1
VDDQ_W5W5
VDDQ_W8W8
VDDQ_W12W12
VDDQ_AA3AA3
VDD2_U8U8 VDD2_U5U5 VDD2_R12
R12
VDDQ_AA5AA5
VDDQ_AA8AA8
VDDQ_AA10AA10
VSS_AB3AB3VSS_Y12Y12VSS_Y8Y8VSS_Y5Y5VSS_Y1Y1VSS_W11W11VSS_W9W9VSS_W4W4VSS_W2W2VSS_V12V12VSS_V8V8VSS_V5V5VSS_V1V1VSS_T12T12VSS_T10T10VSS_T8T8VSS_T5T5VSS_T3T3VSS_T1T1VSS_P12P12VSS_P10P10VSS_P3P3VSS_P1P1VSS_N11N11VSS_N9N9VSS_N4N4VSS_N2N2VSS_K11K11VSS_K9K9VSS_K4K4VSS_K2K2VSS_J12J12VSS_J10J10VSS_J3J3VSS_J1J1VSS_G12G12VSS_G10G10VSS_G8G8VSS_G5G5VSS_G3G3VSS_G1G1VSS_E12E12VSS_E8E8VSS_E5E5VSS_E1E1VSS_D11D11VSS_D9D9VSS_D4D4VSS_D2D2VSS_C12C12VSS_C8C8VSS_C5C5VSS_C1C1VSS_A10A10VSS_A3A3
C2124.7uF6.3V
C2174.7uF6.3V
R204 240 1%R205 240 1%
R20610K5%
C2074.7uF6.3V
R20710K5%
C21122uF10V
C2084.7uF6.3V
R2011501%
DRAM_DMI0_ADRAM_DMI1_A
DRAM_SDQS0_C_ADRAM_SDQS0_T_A
DRAM_SDQS1_C_ADRAM_SDQS1_T_A
DRAM_DATA1_ADRAM_DATA0_A
DRAM_DATA2_ADRAM_DATA3_A
DRAM_DATA8_ADRAM_DATA7_ADRAM_DATA6_ADRAM_DATA5_ADRAM_DATA4_A
DRAM_DATA13_ADRAM_DATA12_ADRAM_DATA11_ADRAM_DATA10_ADRAM_DATA9_A
DRAM_DATA15_ADRAM_DATA14_A
DRAM_DMI1_BDRAM_DMI0_B
DRAM_DATA4_BDRAM_DATA3_BDRAM_DATA2_B
DRAM_DATA0_BDRAM_DATA1_B
DRAM_DATA10_BDRAM_DATA9_BDRAM_DATA8_BDRAM_DATA7_BDRAM_DATA6_BDRAM_DATA5_B
DRAM_DATA15_BDRAM_DATA14_BDRAM_DATA13_BDRAM_DATA12_BDRAM_DATA11_B
DRAM_SDQS1_T_BDRAM_SDQS1_C_B
DRAM_SDQS0_T_BDRAM_SDQS0_C_B
DRAM_CA1_ADRAM_CA0_A
DRAM_CA3_A
DRAM_CA5_ADRAM_CA4_A
DRAM_CA2_A
DRAM_CK_C_ADRAM_CK_T_A
DRAM_nCS1_ADRAM_nCS0_A
DRAM_CKE0_ADRAM_CKE1_A
DRAM_CK_C_A
DRAM_CK_T_A
DRAM_CK_C_B
DRAM_CK_T_B
DRAM_nRESET
DRAM_DATA3_A
DRAM_DATA1_ADRAM_DATA0_A
DRAM_DATA4_A
DRAM_DATA7_ADRAM_DATA6_ADRAM_DATA5_A
DRAM_DATA2_A
DRAM_DATA13_ADRAM_DATA12_A
DRAM_DATA8_A
DRAM_DATA10_ADRAM_DATA9_A
DRAM_DATA14_ADRAM_DATA15_A
DRAM_DATA11_A
DRAM_DMI0_A
DRAM_DMI1_A
DRAM_SDQS0_C_ADRAM_SDQS0_T_A
DRAM_SDQS1_C_ADRAM_SDQS1_T_A
DRAM_DATA4_BDRAM_DATA3_BDRAM_DATA2_B
DRAM_DATA0_B
DRAM_DATA7_BDRAM_DATA6_BDRAM_DATA5_B
DRAM_DATA1_B
DRAM_DMI0_B
DRAM_DATA10_BDRAM_DATA9_BDRAM_DATA8_B
DRAM_DATA15_BDRAM_DATA14_BDRAM_DATA13_BDRAM_DATA12_BDRAM_DATA11_B
DRAM_DMI1_B
DRAM_SDQS0_T_BDRAM_SDQS0_C_B
DRAM_SDQS1_C_BDRAM_SDQS1_T_B
DRAM_CA1_ADRAM_CA0_A
DRAM_CA3_ADRAM_CA4_A
DRAM_CA2_A
DRAM_CA5_A
DRAM_nCS1_ADRAM_nCS0_A
DRAM_CKE0_ADRAM_CKE1_A
DRAM_CK_T_ADRAM_CK_C_A
ODT_CA_A
DRAM_CKE0_BDRAM_CKE1_B
DRAM_CK_T_BDRAM_CK_C_B
ODT_CA_B
DRAM_nCS1_BDRAM_nCS0_B
DRAM_CA1_B
DRAM_CA3_B
DRAM_CA5_BDRAM_CA4_B
DRAM_CA2_B
DRAM_CA0_B
DRAM_nRESET
DRAM_ZQ0
DRAM_ZQ1
DRAM_CA1_BDRAM_CA0_B
DRAM_CA3_B
DRAM_CA5_BDRAM_CA4_B
DRAM_CA2_B
DRAM_CK_T_BDRAM_CK_C_B
DRAM_CKE0_BDRAM_CKE1_B
DRAM_nCS1_BDRAM_nCS0_B
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
# NAND/QSPI
-Internal pullup resistors 27 kOhm;-Internal pulldown resistor of 90kOhm is always enabled
NVCC_I2C_3V3
QSPIA_DATA1QSPIA_DATA2QSPIA_DATA3
QSPIA_DATA0
NAND_nWPNAND_nWE
NAND_nREADY
NAND_DATA[7:0]
NAND_nCE3
SD1_CMD
SD1_DATA1SD1_DATA2
SD1_DATA0
SD1_CLK
SD1_DATA3
SD1_DATA5SD1_DATA6
SD1_DATA4
SD1_DATA7
SD1_STROBESD1_nRST
SD2_CMD
SD2_DATA1SD2_DATA2
SD2_DATA0
SD2_CLK
SD2_DATA3
SD2_nRSTSD2_nCD
SAI1_MCLK
SAI1_TXFSSAI1_TXC
SAI1_TXD0SAI1_TXD1SAI1_TXD2SAI1_TXD3SAI1_TXD4SAI1_TXD5SAI1_TXD6SAI1_TXD7
SAI1_RXFSSAI1_RXC
SAI1_RXD0SAI1_RXD1SAI1_RXD2SAI1_RXD3SAI1_RXD4SAI1_RXD5SAI1_RXD6SAI1_RXD7
SAI2_MCLK
SAI2_RXDSAI2_RXCSAI2_RXFS
SAI2_TXDSAI2_TXCSAI2_TXFS
SAI3_TXFS
SAI3_MCLK
SAI3_RXFSSAI3_RXC
SAI3_TXDSAI3_TXC
SAI3_RXD
SPDIF_EXT_CLKSPDIF_RXSPDIF_TX
SAI5_RXCSAI5_RXFS
SAI5_MCLK
SAI5_RXD0SAI5_RXD1SAI5_RXD2SAI5_RXD3
ENET_MDIOENET_MDC
ENET_TX_CTLENET_TXCENET_TD0ENET_TD1ENET_TD2ENET_TD3
ENET_RX_CTLENET_RXC
UART1_TXDUART1_RXD
UART2_TXDUART2_RXD
UART3_TXDUART3_RXD
I2C1_SDAI2C1_SCL
I2C2_SDAI2C2_SCL
I2C3_SDAI2C3_SCL
UART3_CTS
UART3_RTS
nWDOG
SD2_VSELECT
REF_CLK_32K
CLKO2
PWM_LED
AUD_nMUTEPMIC_nINT
ENET_nRSTENET_WoLENET_nINT
PCIe_nWAKEPCIe_nRSTPCIe_nDIS
WL_nPERSTWL_REG_ON
CSI_P1_PWDN
CSI_P2_PWDN
IR_CAP
DSI_TS_nINT
DSI_EN
PCIE2_nCLKREQ
ENET_RD0ENET_RD1ENET_RD2ENET_RD3
CSI_nRST
DSI_BL_PWM
CLKO_25MHz
SDIO_WAKE
BT_DEV_WAKETCPC_nINT
QSPIA_nSS0
QSPIA_SCLK
USB1_SS_SELIPOD_nRST
WL_nWAKE
BT_REG_ON
PCIE1_nCLKREQ
BT_RF_KILL
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
CPU IO
<JW>
<Approver>
<JW>
6 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
CPU IO
<JW>
<Approver>
<JW>
6 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
CPU IO
<JW>
<Approver>
<JW>
6 23
____X____
R307 4.7K 5% DNP
R301 4.7K 5%
NVCC_ENET
i.MX8M - eNET
MiMX8MQ7DVAJZxA + MBF25004-15W/2.0P+T725 A1
U101J
ENET_RD3V19
ENET_RD1U21
ENET_RD2U20
ENET_RD0U19
ENET_RX_CTLT21
ENET_RXCT20
ENET_TXCT19
ENET_TD1R21ENET_TD0R20
ENET_TD2R19
ENET_TD3P20
ENET_TX_CTLP19
ENET_MDCN20
ENET_MDION19
R308 4.7K 5% DNP
R302 4.7K 5%
R309 0 5%
i.MX8M - SD
NVCC_SD1
NVCC_SD2
MiMX8MQ7DVAJZxA + MBF25004-15W/2.0P+T725 A1
U101I
SD1_STROBET24
SD1_DATA7T25 SD1_DATA6R25
SD1_RESET_BR24
SD2_WPM21
SD1_DATA3P25
SD1_DATA5P24
SD2_RESET_BR22
SD2_DATA3P21
SD1_DATA0M25
SD1_DATA4N24
SD2_DATA1N21SD2_DATA0N22
SD1_DATA2N25 SD1_DATA1M24
SD2_CLKL22
SD2_DATA2P22
SD1_CLKL25
SD1_CMDL24
SD2_CMDM22
SD2_CD_BL21
NVCC_SAI2
NVCC_SAI1
NVCC_SAI3
i.MX8M - SAI
NVCC_SAI5
MiMX8MQ7DVAJZxA + MBF25004-15W/2.0P+T725 A1
U101G
SAI5_RXFSN4
SAI5_RXD0M5
SAI5_RXD2M4
SAI5_RXCL5
SAI5_RXD1L4
SAI1_RXD1L2
SAI1_RXFSL1
SAI5_RXD3K5
SAI5_MCLKK4
SAI1_RXD0K2
SAI1_RXCK1
SAI2_RXD0H6
SAI2_RXFSJ4
SAI1_RXD3J2
SAI1_RXD4J1
SAI2_TXCJ5SAI2_TXFSH4
SAI2_RXCH3
SAI1_RXD2H2
SAI1_TXFSH1
SAI2_MCLKH5
SAI2_TXD0G5
SAI3_RXFSG4
SAI3_TXFSG3
SAI1_RXD6G2
SAI1_RXD7G1
SPDIF_RXG6 SPDIF_TXF6
SAI3_RXCF4
SAI3_RXDF3
SAI1_TXD0F2
SAI1_RXD5F1
SPDIF_EXT_CLKE6
SAI1_TXD1E2
SAI1_TXCE1
SAI1_TXD4D2SAI1_TXD3D1
SAI3_MCLKD3
SAI1_TXD5C2
SAI1_TXD7C1
SAI3_TXDC3
SAI1_TXD6B3
SAI1_TXD2B2
SAI3_TXCC4
SAI1_MCLKA3
R303 4.7K 5%R304 4.7K 5%
R310 0 DNP5%
i.MX8M - NAND
NVCC_NAND
MiMX8MQ7DVAJZxA + MBF25004-15W/2.0P+T725 A1
U101H
NAND_DQSM20
NAND_DATA07M19
NAND_DATA04L20
NAND_DATA06L19
NAND_WE_BK22
NAND_WP_BK21
NAND_READY_BK20
NAND_RE_BK19
NAND_DATA05J22
NAND_DATA03J21
NAND_DATA01J20
NAND_DATA02H22
NAND_CLEH21
NAND_CE3_BH20
NAND_CE0_BH19
NAND_CE1_BG21
NAND_DATA00G20
NAND_ALEG19
NAND_CE2_BF21
R305 4.7K 5%R306 4.7K 5%
NVCC_I2C
NVCC_UART
NVCC_GPIO1
NVCC_ECSPI
MiMX8MQ7DVAJZxA + MBF25004-15W/2.0P+T725 A1
U101K
GPIO1_IO01T7GPIO1_IO00T6
GPIO1_IO02R4
GPIO1_IO05P7GPIO1_IO04P5GPIO1_IO03P4
GPIO1_IO08N7GPIO1_IO07N6GPIO1_IO06N5
GPIO1_IO10M7GPIO1_IO09M6
GPIO1_IO12L7GPIO1_IO11L6
GPIO1_IO14K7GPIO1_IO13K6
GPIO1_IO15J6
I2C3_SCLG8
I2C2_SCLG7
I2C4_SDAF9 I2C4_SCLF8
I2C2_SDAF7
I2C3_SDAE9
I2C1_SDAE8 I2C1_SCLE7
UART4_TXDD7
UART2_TXDD6
ECSPI2_MOSIE5
ECSPI1_SS0D4
UART1_RXDC7
UART4_RXDC6 ECSPI2_SCLK
C5
ECSPI1_MOSIA4
UART3_TXDB7
UART2_RXDB6
ECSPI2_MISOB5
ECSPI1_MISOB4UART1_TXD
A7
UART3_RXDA6 ECSPI2_SS0
A5
ECSPI1_SCLKD5
ENET_MDCENET_MDIO
NAND_DATA7NAND_DATA6
NAND_DATA4NAND_DATA3NAND_DATA2NAND_DATA1
NAND_DATA5
NAND_DATA0
NAND_DQS
NAND_nRENAND_CLE
NAND_nWENAND_nWPNAND_nREADY
NAND_ALE
NAND_nCE1NAND_nCE0
NAND_nCE3NAND_nCE2
SD1_CMDSD1_CLK
SD1_DATA0SD1_DATA1SD1_DATA2SD1_DATA3SD1_DATA4SD1_DATA5SD1_DATA6SD1_DATA7
SD1_nRSTSD1_STROBE
SAI5_MCLK
SAI5_RXFSSAI5_RXC
SAI5_RXD1SAI5_RXD2SAI5_RXD3
SAI5_RXD0
SAI3_MCLK
SAI3_TXFSSAI3_TXCSAI3_TXD
SAI3_RXFSSAI3_RXCSAI3_RXD
SPDIF_TX
SPDIF_EXT_CLKSPDIF_RX
ENET_TD0ENET_TXCENET_TX_CTL
ENET_TD1ENET_TD2ENET_TD3
ENET_RX_CTLENET_RXC
GPIO1_IO00GPIO1_IO01GPIO1_IO02GPIO1_IO03GPIO1_IO04GPIO1_IO05GPIO1_IO06GPIO1_IO07GPIO1_IO08GPIO1_IO09GPIO1_IO10GPIO1_IO11GPIO1_IO12GPIO1_IO13GPIO1_IO14GPIO1_IO15
ECSPI1_SS0ECSPI1_MOSI
ECSPI1_SCLKECSPI1_MISO
ECSPI2_SS0ECSPI2_MOSI
ECSPI2_SCLKECSPI2_MISO
UART1_RXDUART1_TXD
UART2_RXDUART2_TXD
UART3_RXDUART3_TXD
UART4_RXDUART4_TXD
I2C1_SDAI2C1_SCL
I2C2_SCLI2C2_SDA
I2C3_SCLI2C3_SDA
I2C4_SCLI2C4_SDA
SD2_CMDSD2_CLK
SD2_DATA0SD2_DATA1SD2_DATA2SD2_DATA3
SD2_nRSTSD2_nCDSD2_WP
SAI1_MCLK
SAI1_TXFSSAI1_TXC
SAI1_RXD0
SAI1_RXD2SAI1_RXD3SAI1_RXD4
SAI1_RXD1
SAI1_RXD5SAI1_RXD6SAI1_RXD7
SAI1_TXD0
SAI1_TXD2SAI1_TXD3
SAI1_TXD1
SAI1_TXD4SAI1_TXD5SAI1_TXD6SAI1_TXD7
SAI1_RXCSAI1_RXFS
SAI2_MCLK
SAI2_TXFSSAI2_TXCSAI2_TXD
SAI2_RXFSSAI2_RXCSAI2_RXD
NAND_DATA3NAND_DATA2NAND_DATA1NAND_DATA0
I2C1_SDAI2C1_SCL
I2C2_SCLI2C2_SDA
I2C3_SCLI2C3_SDA
I2C4_SCLI2C4_SDA
ENET_RD0
ENET_RD2ENET_RD1
ENET_RD3
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
JTAG Debug
PU
PU
PU
PU
Internal 31.25KHz or External RTC CLK
mScale850 MISC
PD
PU
PU
PU
PU
PU
input
output
GND
GND
NVCC_SNVS_3V3
NVCC_JTAG_3V3
GND
GND
GND
GND
NVCC_SNVS_3V3
GND
GND
NVCC_SNVS_3V3
GND
GND
NVCC_SNVS_3V3
PMIC_STBY_REQPMIC_ON_REQ
ONOFF
POR_B
POR_B
BOOT_MODE0BOOT_MODE1
ONOFFPMIC_STBY_REQPMIC_ON_REQ
BOOT_MODE0BOOT_MODE1
CLK2_PCLK2_N
CLK1_PCLK1_N
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
CPU PERI2
<JW>
<Approver>
<JW>
7 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
CPU PERI2
<JW>
<Approver>
<JW>
7 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
CPU PERI2
<JW>
<Approver>
<JW>
7 23
____X____
TP403
R412 1MDNP
1%
R416 100KDNP
1%
C40218PF50V
R417 0 5%
R407 0 5%
D402
ZLLS400
AC
R40410K
DNP
5%
U401
UM803RS
GN
D1
VC
C3
RESET2
TP408
TP406
C40418PF50V
i.MX8M - MISC
VDDA
NVCC_SNVS
NVCC_JTAG
MiMX8MQ7DVAJZxA + MBF25004-15W/2.0P+T725 A1
U101L
BOOT_MODE0W6
JTAG_TDIW5
ONOFFW21
POR_BW20
RTC_RESET_BW19
TEST_MODEV7
BOOT_MODE1V6
JTAG_TMSV5
XTALI_27MV25
XTALO_27MV24
RTCV22
PMIC_STBY_REQV21
PMIC_ON_REQV20
JTAG_MODU7JTAG_TRST_BU6JTAG_TDOU5
XTALI_25MU25
XTALO_25MU24
CLK2_NU22
JTAG_TCKT5
CLK1_NT23
CLK2_PT22
CLK1_PR23
TP407
TP404
TP409
Y401
25MHz
1 4
32
C4011uF25 V
R419100K1%
C4060.1uF50V
R4051001%
TP402
R415 1.5K 1%
R413 100 1% DNP
TP405
Y402
27MHz
1 4
32
R40810K5%
C40518PF50V
C40318PF50V
TP401
R418 0 5% DNP
D401
ZLLS400
A C
R401 0 5%
Y403
32.768KHZ
VIO1
GND2
OUTPUT3
VDD4
J401
HDR 2X5
1234
6 578910
C4070.1uF50V
R411 1MDNP
1%
R414 100 1%
R4094.7K5%
R410 10K 5%
R40310K
DNP
5%
R406 0 DNP5%
R40210K
DNP
5%
JTAG_TCK
JTAG_TDIJTAG_TMS
JTAG_nTRST
JTAG_TDOPOR_B
JTAG_TMSTCKJTAG_TCK GND
GNDTDOJTAG_TDOJTAG_TDI
nRST
TMS
NC/TDI
VCC
XTALO_25MXTALI_25M
XTALI_27MXTALO_27M
JTAG_MODJTAG_nTRSTJTAG_TDOJTAG_TDIJTAG_TMSJTAG_TCK
BOOT_MODE1BOOT_MODE0
TEST_MODE
BOOT_MODE1BOOT_MODE0
PMIC_STBY_REQONOFF
PMIC_ON_REQ
RTC_CLK_32K768
JTAG_nTRST
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
mScale850 PHYUSB_RESREF: Attach a 200-Ω 1% 100-ppm/C precision resistor-to-ground on the board. MIPIDSI_REXT: 15K-ΩPCIE: 200-Ω±1% ± 100 ppm/°C precision resistor to-ground on the board.HDMI:a 499Ω ±1% tolerance resistor to-ground on the board
AC coupled differential low swing clock (HCSL levels)
AC coupled differential low swing clock (HCSL levels)
DIODES: NX5427001Z 5032 3.3V
VDD_PHY_0V9
VDD_PHY_1V8
VDD_PHY_3V3
GND
GND
GND
GND
VDD_3V3VDD_3V3
GND
GND
GND
GND
GND
PCIE1_TXN
PCIE1_RXN
PCIE1_TXP
PCIE1_RXP
PCIE2_TXN
PCIE2_RXN
PCIE2_TXP
PCIE2_RXP
HDMI_DDC_SDAHDMI_DDC_SCL
HDMI_HPD
HDMI_CEC
HDMI_TXN0HDMI_TXP0
HDMI_TXN1HDMI_TXP1
HDMI_TXN2HDMI_TXP2
HDMI_CLKNHDMI_CLKP
USB1_DNUSB1_VBUS
USB1_DPUSB1_ID
USB2_DNUSB2_VBUS
USB2_DPUSB2_ID
CSI_P1_CKN
CSI_P1_DN0
CSI_P1_CKP
CSI_P1_DP0
CSI_P1_DN1CSI_P1_DP1
CSI_P1_DN2CSI_P1_DP2
CSI_P1_DN3CSI_P1_DP3
CSI_P2_CKN
CSI_P2_DN0
CSI_P2_CKP
CSI_P2_DP0
CSI_P2_DN1CSI_P2_DP1
CSI_P2_DN2CSI_P2_DP2
CSI_P2_DN3CSI_P2_DP3
DSI_CKNDSI_CKP
DSI_DN0DSI_DP0
DSI_DN1DSI_DP1
DSI_DN2DSI_DP2
DSI_DN3DSI_DP3
USB1_TXPUSB1_TXN
USB1_RXPUSB1_RXN
USB2_TXPUSB2_TXN
USB2_RXPUSB2_RXN
HDMI_AUXNHDMI_AUXP
PCIE1_REF_CLKNPCIE1_REF_CLKP
PCIE2_REF_CLKNPCIE2_REF_CLKP
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
CPU PHY
<JW>
<Approver>
<JW>
8 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
CPU PHY
<JW>
<Approver>
<JW>
8 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
CPU PHY
<JW>
<Approver>
<JW>
8 23
____X____
R505 15K 1%
R503 499 1%
i.MX8M - CSI
CSI_P1_VDDHA
CSI_P2_VDDHA
MiMX8MQ7DVAJZxA + MBF25004-15W/2.0P+T725 A1
U101E
MIPI_CSI1_CLK_PB22
MIPI_CSI1_D3_PD21
MIPI_CSI2_D0_PD20
MIPI_CSI2_CLK_PB19
MIPI_CSI1_CLK_NA22
MIPI_CSI1_D3_NC21
MIPI_CSI2_D0_NC20
MIPI_CSI2_CLK_NA19
MIPI_CSI1_D2_PC23
MIPI_CSI1_D0_PB23
MIPI_CSI1_D1_PD22
MIPI_CSI2_D2_PB21
MIPI_CSI2_D1_PB20
MIPI_CSI2_D3_PD19
MIPI_CSI1_D2_NB24
MIPI_CSI1_D0_NA23
MIPI_CSI1_D1_NC22
MIPI_CSI2_D2_NA21
MIPI_CSI2_D1_NA20
MIPI_CSI2_D3_NC19
C5010.1uF10V
R51249.91%DNP
TP501
TP502
R51349.91%DNP
R509100K1%
i.MX8M - PCIe
PCIE0_VPH
PCIE1_VPH
MiMX8MQ7DVAJZxA + MBF25004-15W/2.0P+T725 A1
U101C
PCIE1_REF_PAD_CLK_NK24
PCIE1_REF_PAD_CLK_PK25
PCIE1_TXN_PJ25PCIE1_TXN_NJ24
PCIE1_RXN_PH25PCIE1_RXN_NH24
PCIE1_RESREFG25
PCIE2_REF_PAD_CLK_NF24
PCIE2_REF_PAD_CLK_PF25
PCIE2_TXN_PE25PCIE2_TXN_NE24
PCIE2_RXN_PD25PCIE2_RXN_ND24
PCIE2_RESREFC25
R508100K1%
R504 200 1%
i.MX8M - HDMI
HDMI_AVDDIO
MiMX8MQ7DVAJZxA + MBF25004-15W/2.0P+T725 A1
U101F
HDMI_CECW3
HDMI_HPDW2
HDMI_DDC_SCLR3
HDMI_AUX_PV1HDMI_AUX_NV2
HDMI_DDC_SDAP3
HDMI_REFCLK_NR1
HDMI_REFCLK_PR2
HDMI_TX_P_LN_2N2HDMI_TX_M_LN_2N1
HDMI_TX_P_LN_3M1HDMI_TX_M_LN_3M2
HDMI_REXTP1
HDMI_TX_P_LN_0T1HDMI_TX_M_LN_0T2
HDMI_TX_P_LN_1U2HDMI_TX_M_LN_1U1
R510 0 5%
R506 200 1%
R511 0 5%
R501 200 1%
i.MX8M - USB
USB_P0_VDD33
USB_P0_VPH
USB_P1_VDD33
USB_P1_VPH
MiMX8MQ7DVAJZxA + MBF25004-15W/2.0P+T725 A1
U101B
USB1_VBUSD14
USB2_VBUSD9
USB2_IDC9
USB1_IDC14
USB2_TX_NB9
USB2_DNB10
USB1_RX_PA12
USB1_TX_PA13
USB1_DPA14
USB2_RESREFB11
USB2_RX_NB8
USB2_TX_PA9
USB2_DPA10
USB1_RX_NB12
USB1_TX_NB13
USB1_DNB14
USB1_RESREFA11
USB2_RX_PA8
R502 200 1%
HCSL
Y501
27MHz
VCC6
GND3
Q4
Q5
NC2
OE1
i.MX8M - DSI
DSI_VDDHA
MiMX8MQ7DVAJZxA + MBF25004-15W/2.0P+T725 A1
U101D
MIPI_DSI_CLK_PD16
MIPI_DSI_REXTC17
MIPI_DSI_CLK_NC16
MIPI_DSI_D2_PB18
MIPI_DSI_D0_PB17
MIPI_DSI_D1_PB16
MIPI_DSI_D3_PB15
MIPI_DSI_D2_NA18
MIPI_DSI_D0_NA17
MIPI_DSI_D1_NA16
MIPI_DSI_D3_NA15
VDD_PHY_0V9
PCIE2_TXP
PCIE2_REF_CLKMPCIE2_REF_CLKP
PCIE2_RXPPCIE2_RXM
PCIE2_TXM
HDMI_TXN1HDMI_TXP1
HDMI_TXN2HDMI_TXP2
HDMI_TXN3HDMI_TXP3
HDMI_AUXNHDMI_AUXP
CSI_P2_CKNCSI_P2_CKP
CSI_P2_DN0CSI_P2_DP0
CSI_P2_DN1CSI_P2_DP1
CSI_P2_DN2CSI_P2_DP2
CSI_P2_DN3CSI_P2_DP3
CSI_P1_CKP
CSI_P1_DN0CSI_P1_DP0
CSI_P1_CKN
CSI_P1_DN1CSI_P1_DP1
CSI_P1_DN2CSI_P1_DP2
CSI_P1_DN3CSI_P1_DP3
USB1_VBUSUSB1_DNUSB1_DPUSB1_ID
DSI_CKP
DSI_DN0DSI_DP0
DSI_DN1DSI_DP1
DSI_CKN
DSI_DN2DSI_DP2
DSI_DN3DSI_DP3
PCIE1_TXP
PCIE1_REF_CLKMPCIE1_REF_CLKP
PCIE1_RXPPCIE1_RXM
PCIE1_TXM
HDMI_HPD
HDMI_CEC
HDMI_DDC_SCLHDMI_DDC_SDA
HDMI_TXP0
HDMI_REFCLKNHDMI_REFCLKP
HDMI_TXN0
USB2_VBUSUSB2_DNUSB2_DPUSB2_ID
VDD_PHY_1V8
VDD_PHY_3V3
USB1_TXPUSB1_TXN
USB1_RXPUSB1_RXN
USB2_TXPUSB2_TXN
USB2_RXPUSB2_RXN
USB1_ID
USB2_ID
HDMI_REFCLKN
HDMI_REFCLKP
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
eMMC 5.0 Footprint
# eMMC/TF co-Layout
QSPI-A
Hinge Type MicroSD
# Hinge TYPE# Stitching CAP for Layout
# eMMC/TF co-Layout
Via/TP
MTFC16GAKAECN-2M WTMT53B1024M32D4NQ-062MT25QL256ABA1EW9-0SIT
GND
VDD_3V3
GND
GND
NVCC_NAND_3V3
VDD_3V3
GND
GND
GND
GND
GND
NVCC_SD1_1V8
VDD_3V3
NVCC_SD1_1V8
QSPIA_DATA0 QSPIA_DATA1
QSPIA_DATA2
QSPIA_DATA3
QSPIA_nSS0
QSPIA_SCLK
SD1_DATA2SD1_DATA3
SD1_CMD
SD1_DATA1SD1_DATA0
SD1_nRST
SD1_CLK
SD1_CMD
SD1_STROBE
SD1_DATA1
SD1_DATA4
SD1_DATA0
SD1_DATA3SD1_DATA2
SD1_DATA7SD1_DATA6SD1_DATA5
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
Flash
<JW>
<Approver>
<JW>
9 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
Flash
<JW>
<Approver>
<JW>
9 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
Flash
<JW>
<Approver>
<JW>
9 23
____X____
R6034.7K5%
R617 0 5%
C6030.1uF50V
TP603
C6020.1uF50V
R6014.7K5%
C61822uF
6.3V
TP602
C6170.1uF50V
U603
MT25QL256ABA1EW9
S1
DQ12
W/DQ23
VS
S4
DQ05
C6
HOLD/DQ37
VC
C8
EP
9
C6060.1uF50V
C6144.7uF6.3V
U601B
MTFC16GAKAECN-2M WT
NC_A1A1
NC_A2A2
NC_A8A8
NC_A9A9
NC_A10A10
NC_A11A11
NC_A12A12
NC_A13A13
NC_A14A14
NC_B1B1
NC_B7B7
NC_B8B8
NC_B9B9
NC_B10B10
NC_B11B11
NC_B12B12
NC_B13B13
NC_B14B14
NC_C1C1
NC_C3C3
NC_C7C7
NC_C8C8
NC_C9C9
NC_C10C10
NC_C11C11
NC_C12C12
NC_C13C13
NC_C14C14
NC_D1D1
NC_D2D2
NC_D3D3
NC_D4D4
NC_D12D12
NC_D13D13
NC_D14D14
NC
_E
1E
1
NC
_E
2E
2
NC
_E
3E
3
NC
_E
12
E12
NC
_E
13
E13
NC
_E
14
E14
NC
_F
1F
1
NC
_F
2F
2
NC
_F
3F
3
NC
_F
12
F12
NC
_F
13
F13
NC
_F
14
F14
NC
_G
1G
1
NC
_G
2G
2
NC
_G
12
G12
NC
_G
13
G13
NC
_G
14
G14
NC
_H
1H
1
NC
_H
2H
2
NC
_H
3H
3
NC
_H
12
H12
NC
_H
13
H13
NC
_H
14
H14
NC
_J1
J1
NC
_J2
J2
NC
_J3
J3
NC
_J12
J12
NC
_J13
J13
NC
_J14
J14
NC_K1K1NC_K2K2NC_K3K3NC_K12K12NC_K13K13NC_K14K14NC_L1L1NC_L2L2NC_L3L3NC_L12L12NC_L13L13NC_L14L14NC_M1M1NC_M2M2
RF
U3
E8
RF
U4
E9
RF
U5
E10
RF
U2
E5
RF
U6
F10
NC
_G
3G
3
RF
U7
G10
RF
U1
A7
NC_C5C5
RF
U8
K6
RF
U10
K10
RF
U9
K7
RF
U11
P10
NC
_P
7P
7
NC
_P
14
P14
NC
_P
13
P13
NC
_P
12
P12
NC
_P
11
P11
NC
_P
9P
9
NC
_P
8P
8
NC
_P
2P
2
NC
_P
1P
1
NC_N14N14
NC_N13N13
NC_N12N12
NC_N11N11
NC_N10N10
NC_N9N9
NC_N8N8
NC_N7N7
NC_N6N6
NC_N3N3
NC_N1N1
NC_M14M14
NC_M13M13
NC_M12M12
NC_M11M11
NC_M10M10
NC_M9M9
NC_M8M8
NC_M7M7
NC_M3M3
C6040.1uF50V
C6070.1uF50V
C6054.7uF6.3V
R616 0 5%
C6014.7uF6.3V
U601AMTFC16GAKAECN-2M WT
CLKM6
CMDM5
RSTK5
VDDIMC2
VCCQ1C6
VCCQ5P5
VCCQ2M4
VCCQ4P3VCCQ3N4
VC
C3
J10
VC
C2
F5
VC
C1
E6
VC
C4
K9
VS
S2
E7
VS
S3
G5
VS
S4
H10
VS
S6
K8
VSSQ2N2
VSSQ3N5
VSSQ4P4
VSSQ5P6
VSSQ1C4DAT7
B6 DAT6B5 DAT5B4 DAT4B3 DAT3B2 DAT2A5 DAT1A4 DAT0A3
VS
S1
A6
VS
S5
J5
DSH5
R621 0 5%
C6111uF25 V
C6100.1uF50V
C6130.1uF50V
R6024.7K5%
J601
CAH11-08163-S107
DNP
DAT2P1
CD/DAT3P2
CMDP3
VDDP4
CLKP5
VSSP6
DAT0P7
DAT1P8
S1
S1
S2
S2
S3
S3
S4
S4
R62010K5%
eMMC_CLK
eMMC_nRST
eMMC_CMD
eMMC_DQS
eMMC_VDDIM
eMMC_CLK
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SYS PMIC/PWRDCDC 5V
# 3.38V/8A
Main PWR (5-20V-->3.3V)
Mode selection. Pull MODE low or floatMODE to set auto PFM/PWM mode; pullMODE to VCC to set forced PWM mode.MODE is pulled down internally.
1.55M PD
RSV for Curr Measure
FB=0.6V
FB=0.6V
# GPIO/WDOG PWR OFF->ON
# Reset Button
12RTC_RESET_B3444455666
777POR_B
NVCC_SNVSVDD_SNVS
VDD_SOC/VDDA_0P9VDD_GPUVDD_VPUVDD_DRAMVDD_ARMVDDA_1P8_xxxVDDA_DRAMNVCC_DRAMNVCC_3V3NVCC_1V8
3.3V PHY1.8V PHY0.9V PHY
30.81
0.810.810.810.810.811.621.71
31.65
3.0691.6740.837
3.30.9
0.90.9/1.00.9/1.01.00.9/1.01.81.81.1/1.2/1.353.31.8
3.31.80.9
3.60.99
0.991.11.11.051.11.891.89
3.61.95
3.631.980.99
22
36002000100025004000250502170100450
10050250
SEQ PWR MIN TYP MAX Curr(mA)
mScale850 ADD SPEC V2.0
600mv
SYS PWR SW
Vfb=0.8V
VDD_DRAM Change to 1.0V tosupport 1.6GHz!!!
Change to support ARM OD mode: 0.9/1.0V!!!
PWM_LED: H: 0.9V; L:1.0V
GND
GND
GNDVDD_3V3
VDD_3V3
VDDA_1V8
GND
GND
GND
VSYS
GND
GND GND
DCDC_3V3
NVCC_SNVS_3V3
NVCC_3V3
GND
DCDC_3V3
GND
GND
GND GND
GND
GND
DCDC_5VVSYS
GNDGND
GND
GND
DCDC_3V3
NVCC_DRAM_1V1
GND
GND
VREFDDR
GND
GND
GND
GND
DCDC_3V3
GND
VDD_SOC_0V9DCDC_3V3 GND
GND
GND
GND
VDD_ARM_0V9
DCDC_3V3
VDD_GPU_0V9
VDD_PHY_0V9
VCAM_1V5
VDD_PHY_3V3
VCAM_2V8
VDDA_1V8
VDD_PHY_1V8GND
GND
GND
VDD_1V8
GND
NVCC_DRAM_1V1
VDD_DRAM_0V9
VDD_VPU_0V9
NVCC_SNVS_3V3
GND
GND
GND
GND
GND
NVCC_1V8NVCC_SD1_1V8
NVCC_SNVS_3V3
GND
GND
DCDC_5V
DCDC_3V3
VDD_SNVS_0V9
GND
VDD_SNVS_0V9DCDC_3V3
GNDGND GND
PMIC_nINT
POR_B
PMIC_ON_REQ
I2C1_SDAI2C1_SCL
PMIC_STBY_REQ
PMIC_ON_REQ
PMIC_STBY_REQ
nWDOG
SYS_nRST
PWM_LED
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Wednesday, September 27, 2017
PMIC
<JW>
<Approver>
<JW>
10 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Wednesday, September 27, 2017
PMIC
<JW>
<Approver>
<JW>
10 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Wednesday, September 27, 2017
PMIC
<JW>
<Approver>
<JW>
10 23
____X____
R760100K
C7690.1uF50V
R7171M1%
R704 3.3 1%
DCDC
SW1A/B
SW1C
SW2
SW3A/B
SW4
SWBST
MC34PF4210A1ES
U702C
SW1CIN12
SW1VSSSNS14
SW2IN_123
SW3AFB38SW3AIN
37SW3ALX
36
SW3BFB33SW3BIN
34SW3BLX
35
SW3VSSSNS32
SW4FB19SW4IN
20
SWBSTFB44SWBSTIN
45SWBSTLX
46
SW1AIN7
SW1ALX8
SW1BIN10
SW1BLX9
SW1CFB13SW1CLX11
SW1FB6
SW2FB25SW2LX22
SW4LX21
SW2IN_224
C765 10uF 25V
C749 4.7uF 10V
C755 4.7uF 10V
C757 4.7uF 10V
R724 0 5%
C73422uF10V
R720 10.0K 1%
SH704
U706
MP2263GD
MODE1
VIN2
PG
ND
13
PG
ND
28
EN4
NC5
PG6
BIAS7
SW9
BS
T10
VCC11
AG
ND
12
SS13
FB14
FREQ15
C79747UF4.0V
C72522uF10V
C729 4.7uF 10V
R706 100K
C746 0.47uF 16V
C76122uF10V
C70822uF10V
C73922uF10V
R757 56 DNP
C7991uF25 V
C789 5.6PF25V
R711360K1%
R718 10KDNP
5%
C70322uF35V
R7081.5M
R722 0 5%
D702ZLLS400
AC
R752180K1%
C71022uF25V
C7111uF25 V
C7730.1uF50V
R7099.53K1%
SH708
C79547UF4.0V
R705 499 DNP
C73222uF10V
L701 1.5uH
C762 1uF 25 V
C7190.1uF50V
C758 0.1uF 50V
C735 1uF 25 V
LDO
MC34PF4210A1ES
U702B
VGEN116
VGEN218
VIN340
VHALF29
VIN117
VGEN641
VINREFDDR30
VREFDDR31
VSNVS43
VGEN326
VGEN428VIN2
27
LICELL42
VGEN539
VIN50
D701ZLLS400
AC
C73322uF10V
C70722uF10V
R746191K1%
C770 0.1uF 50V
C72322uF10V
R744 0
C7060.1uF50V
Q7032SK3018
2
13
C754 4.7uF 10V
C70222uF35V
D7041N4148WS
DNP
A C
C774
1uF 25 V
L703 1uH1 2
C7760.1uF50V
C77522uF
10V
SH701
U703
LDCL015MR
EN3
IN1
GND2 ADJ
4
OUT5
R759 56K
C75322uF10V
C7050.22uF
C767 0.1uF 50V
SH709
C7151uF25 V
C763 0.1uF 50V
UM805RE
U704
GN
D1
RESET2
MR3
VC
C4
U707
MP2147GD
VIN18
MODE/VCON6
RAMP4EN
5
PG7
OUT2
SW29SW11
FB3
GND10
VIN211
C7920.1uF50V
R710240K1%
R74810.01%
R763100KDNP
R74727K1%
C747 4.7uF 10V
C7810.022UF
C7160.1uF50V
R70244.2K1%
Q704RYU002N05
2
1 3
R731 0
R714 10K 5%
R723100K
C756 0.47uF 16V
C768 1uF 25 V
TP701
R707100KDNP
C79122uF10V
C764 0.47uF 16V
C7040.1uF50V
C750 0.47uF 16V
C7211000pF50V
R745 1M1%
MP8759GD
U701
VIN1
PG
ND
2
PG3
NC4
VOUT5
MODE6
SW7
BS
T8
VCC9
AG
ND
10
FB11
EN12
U705
MP2147GD
VIN18
MODE/VCON6
RAMP4EN
5
PG7
OUT2
SW29SW11
FB3
GND10
VIN211
SH706
C728 1uF 25 V
C72222uF10V
C7881uF
DNP
25 V
R764715K
1%
L705 1uH1 2
C74122uF10V
C7980.1uF50V
R70110K5%
C7180.1uF50V
C740 4.7uF 10V
R755 0
SH703
SH702
C74222uF10V
R713 100 1%
R715 10K5%
C77210uF35VR703
499K
DNP
C73122uF10V
L709
4.7uH1 2
Q701IRLML6401
1
32
C751 4.7uF 10V
C7930.012uF16VA
B
SW701
SW SPDT
3
2
1
Control
MC34PF4210A1ES
U702A
ICTEST5
INT1
RESETMCU3
SCL54SDA53
SDWN2
STANDBY4VCOREDIG
51
VCOREREF52
VDDIO55
VDDOTP47
PWRON56
VCORE49
GNDREF48
EPGND57 GNDREF115
C712
300PF
DNP
100V
C737 4.7uF 10V
C7801000pF50V
R76110K5%
C736 4.7uF 10V
C730 0.22uF 50V
R749 0
C79022uF10V
C748 4.7uF 10V
C7871uF
C73822uF10V
C7240.1uF50V
R732 10.0K
C7141000pF50V
R743 0
R753360K1%
C75222uF10V
L706
0.47uH1 2
R762 0
R71244.2K1%
C7171uF25 V
C71322uF10V
R721 0 5%
D7051N4148WS
A C
C79447UF4.0V
+C779220uF
10V
R758 6.98K
C7771uF DNP25 V
C70122uF35V
C77110uF35V
R719 0 5%
C7200.1uF50V
R716 0DNP
5%
R756 0 5%
C726 1uF 25 V
TP704
C76022uF10V
C759 4.7uF 10V
Q7022SK3018
2
13
L707 1uH1 2
L704 1uH1 2
L702 1uH1 2
D703ZLLS400
AC
C74422uF10V
C74522uF10V
R725 0 5%
C77822uF10V
L710
0.47uH1 2
C7270.1uF
DNP50V
C743 4.7uF 10V
C70922uF10V
C766 0.1uF 50V
R754 10K 5%
DCDC_5V
PMIC_VCORE
PMIC_VCOREREF
PMIC_VCOREDIG
PMIC_VDDOTP
VCC_5V
PWR_MODE
PMIC_ON
PMIC_ONPWR_MODE
nRST
PMIC_ON
VCC_3V6
nRST
PG_SEQ0
PG_SEQ0
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BMODE[1:0] BOOT TYPE
00
01
10
11
Boot From Fuses
Serial Downloader
Internal Boot (Development)
Reserved
# Boot Device: eMMC/MicroSD
SD Loopback ClockSource Sel (for SDR50and SDR104 only)'0' - through SD pad'1' - direct
BOOT_CFG[14]BOOT_CFG[15] BOOT_CFG[13] BOOT_CFG[12] BOOT_CFG[11] BOOT_CFG[10] BOOT_CFG[9] BOOT_CFG[8]0x470[15:8]
mScale 8Quad Boot ROM Fuse <Default: QSPI BOOT>
4 3 2 07 6 5 1Address
Power Cycle Enable'0' - No power cycle'1' - Enabled via
Port Select:00 - eSDHC101 - eSDHC2
001 - SD/eSD
010 - MMC/eMMC
Infinit-Loop(Debug USE only)0 - Disable1 - Enable
011 - NAND
100 - QSPI
110 - SPI NOR
Pages In Block:00 - 12801 - 6410 - 3211 - 256
Nand_Row_address_bytes:00 - 301 - 210 - 411 - 5
QSPI Instance0 - QuadSPI01 - Reserved
SDR SMP:"000" : Default"001-111"
Port Select:000 - eCSPI1001 - eCSPI2
SPI Addressing:0 - 3-bytes (24-bit)1 - 2-bytes (16-bit)
0x470[15:8]
0x470[15:8]
0x470[15:8]
0x470[15:8]
0x470[15:8]
Others - Reserved for future use0x470[15:8]
Reserved
BOOT_CFG[6]BOOT_CFG[7] BOOT_CFG[5] BOOT_CFG[4] BOOT_CFG[3] BOOT_CFG[2] BOOT_CFG[1] BOOT_CFG[0]
Speed000 - Normal/SDR12001 - High/SDR25010 - SDR50011 - SDR104101 - Reserved for DDR50Others - Reserved
Bus Width:0 - 1-bit1 - 4-bit
Fast Boot:0 - Regular1 - Fast Boot
Bus Width:000 - 1-bit001 - 4-bit010 - 8-bit101 - 4-bit DDR (MMC 4.4)110 - 8-bit DDR (MMC 4.4)Else - reserved.
BOOT_SEARCH_COUNT:00 - 201 - 210 - 411 - 8
USDHC1 IO VOLTAGESELECTION0 - 3.3V1 - 1.8V
USDHC2 IO VOLTAGESELECTION0 - 3.3V1 - 1.8V
Toggle Mode 33MHz Preamble Delay, Read Latency:'000' - 16 GPMICLK cycles.'001' - 1 GPMICLK cycles.'010' - 2 GPMICLK cycles.'011' - 3 GPMICLK cycles.'100' - 4 GPMICLK cycles.'101' - 5 GPMICLK cycles.'110' - 6 GPMICLK cycles.'111' - 7 GPMICLK cycles.'1111'- 15 GPMICLK cycles.
Reserved
0x470[7:0]
0x470[7:0]
0x470[7:0]
0x470[7:0]
0x470[7:0]
Reserved Reserved
Speed00 - Normal01 - High10 - Reserved for HS20011 - Reserved
BT_TOGGLEMODE
HSPHS: Half SpeedPhase Selection0 : select samplingat non-invertedclock1: select samplingat inverted clock
HSDLY: Half SpeedDelay selection0 : one clock delay1: two clock delay
FSPHS: Full SpeedPhase Selection0 : select samplingat non-invertedclock1: select samplingat inverted clock
FSDLY: Full SpeedDelay selection0 : one clock delay1: two clock delay
Reserved Reserved Reserved Reserved
CS select (SPI only):00 - CS#0 (default)01 - CS#110 - CS#211 - CS#3
Reserved Reserved Reserved Reserved Reserved Reserved
SD/eSD
MMC/eMMC
NAND
QSPI
SPINOR
t>POR_B to latch BOOT_MODE
-Internal pullup resistors number changed from 3 res to 1 PU res of 27 kOhm;-Internal pulldown resistor of 90kOhm is always enabled
Part Number: MOLEX 0022272031
FAN PWR
123456
During Power UpDuring Power UpDuring Power UpAfter Power UpAfter Power UpAfter Power Up
H (No press)H (No press)L (Press)H (No press)L (Short Press)L (Long Press)
LLLHHH
HHLHHH
1-4 : OFF; 2-3 : ON1-4 : ON; 2-3 : OFF1-4 : ON; 2-3 : OFF///
010///
101///
Serial DownloaderInternal BootSerial DownloaderNo power key eventPower key eventSystem power down
item 1/2 for system developmentitem 2/3 for system upgrade
Normal power key function
item Power state ONOFF RST OE DIP SW BM1 BM0 Note Description
# should be change on B0 TO
GND
NVCC_SAI1_3V3
NVCC_SNVS_3V3
GND
GND
GND
NVCC_SNVS_3V3
GND
NVCC_JTAG_3V3
GND
GND
NVCC_JTAG_3V3GND
NVCC_JTAG_3V3
VDD_3V3
GND
GND
DCDC_5V
GNDGND
GND
GND
SAI1_RXD0SAI1_RXD1SAI1_RXD2SAI1_RXD3SAI1_RXD4SAI1_RXD5SAI1_RXD6SAI1_RXD7
SAI1_TXD0SAI1_TXD1SAI1_TXD2SAI1_TXD3SAI1_TXD4SAI1_TXD5SAI1_TXD6SAI1_TXD7
ONOFF
BOOT_MODE0
BOOT_MODE1
I2C2_SDAI2C2_SCL
IPOD_nRST
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
BOOT_CFG
<JW>
<Approver>
<JW>
11 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
BOOT_CFG
<JW>
<Approver>
<JW>
11 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
BOOT_CFG
<JW>
<Approver>
<JW>
11 23
____X____
R836 1K
D802ZLLS400
A CR84310
R826 1K DNP
R84410K5%
R817 0 DNP5%
R819
0D
NP
R807
10K
DN
P
R840 1K
R812
10K
DN
P
R805
10K
DN
PR
804
1K
R814
10K
DN
P
R818 0 DNP5%
R831 1K
R809
10K
DN
P
R801
10K
DN
P
R846100K5%
DNP
R828 1K
R806
1K
R829 1K
R845100K5%
DNP
R84710K5%
R816
10K
DN
P
R82410K5%
R841 10K 5%
R820
0D
NP
D801ZLLS400
A C
C8010.1uF50V
R811
10K
DN
P
R821
0D
NP
C8040.1uF50V
R8421M1%
R834 1K
R822
0D
NP
R835 4.7K
C8030.1uF50V
R82310K5%
R825 1K
R813
10K
DN
P
R830 1K
VC
CG
ND
2Y
1Y1A
1OE
2A
2OE
U802
74LVC2G125
6
3
2
7
1
5
48
R827 1K
R802
1K
R808
10K
DN
P
R837 4.7K
U801
UM803RS
GN
D1
VC
C3
RESET2
R815
10K
R803
1K
R838 4.7K
R832 1K
C8020.1uF50V
SW801DHN-04
1 2 3 4
8 7 6 5
R810
10K
DN
P
SW802DHN-02
12
43
J801
CON 2X5
1 23 4
657 89 10
R839 4.7K
R833 1K
J802
HDR 1X3
11
22
33
BT_CFG0
BT_CFG2BT_CFG3
BT_CFG6BT_CFG7
BT_CFG8BT_CFG9BT_CFG10BT_CFG11BT_CFG12BT_CFG13BT_CFG14BT_CFG15
BT_CFG1
BT_CFG5BT_CFG4
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
active switch/redriver
USB3.0/2.0 TYPE-C/HOST
USB TYPE-C
OD
# 5-20V
# 12V
OD
OD
default "L"
VBUS / DCDC Path
USB TYPE-C
USB 3.0 HOST
DC IN: 12V/5A
- +
Receptacle, Upright 90°, Type A
Only DC_IN valid will enable DCDC_5Voutput to USB TYPE-C VBUS
1M OHM PD
1M OHM PD
Curr Ltd: 1A/3.3A
0.86V
4.3V-20V
DC IN>4.9V, Power Path Change
2.1A
default "UFP" mode
TLV3201AIDBVR
OD
VDD_1V8
GND
GND
GND
GND
USB_VBUS
VDD_1V8
DCDC_5V
DCDC_5V
USB_VBUS
DC_IN
GND
VDD_3V3
GND
VDD_3V3
GND
GND
GND
VSYS
GND
GND
GND
GND
DCDC_5V
GND
GND
GNDGND
GND
GND
GND
GND
VDD_3V3
DCDC_5V
GND
DCDC_5V
DCDC_5V
GND
GND
GND
GND
GND
GND
GNDGND
GNDGND
GND
GND
DC_IN
USB_VBUS
USB1_TXNUSB1_TXP
USB1_SS_SEL
USB1_DNUSB1_DP
USB1_RXNUSB1_RXP
I2C1_SDAI2C1_SCL
TCPC_nINT
USB2_DNUSB2_DP
USB2_RXNUSB2_RXP
USB2_TXNUSB2_TXP
USB1_VBUS
USB2_VBUS
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
USB
<JW>
<Approver>
<JW>
12 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
USB
<JW>
<Approver>
<JW>
12 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
USB
<JW>
<Approver>
<JW>
12 23
____X____
CMF+ESD
A1,3,5
A2,4,6
B1,B2,B3
C1,3,5
C2,4,6
PCMF3USB3SU908
A1A2
A3A4
A5A6
B1
B2
B3
C1C2
C3C4
C5C6
Q9052SK3018
2
13
D909
PTVS24VS1UR
AC
R9211K
J901
23K20101#LCP-582LF
GND1A1
VBUS1A4
CC1A5
DP1A6
DN1A7
SBU1A8
VBUS2A9
GND2A12
GND3B12
VBUS3B9
SBU2B8
DN2B7 DP2B6
CC2B5
VBUS4B4
SSTXN2B3 SSTXP2B2
GND4B1
SH1SH1
SH3SH3SH2SH2
SH4SH4
SSTXP1A2
SSTXN1A3
SSRXP1B11
SSRXN1B10
SSRXP2A11
SSRXN2A10
TV
S907
ES
D5B
5.0
ST
1G
12
R912
4.7
KD
NP
C922 0.1uF 50V
D905 PMEG6030ELPAC
Q908
AON7405
3
4
21
5
R919 10.0K1%
C921 0.1uF 50V
R905 4.7K
R9481M1%
R904249K
R91344.2K
1%
C906 0.1uF 50V
Q901 AON7405
3
4
21
5
CMF+ESD
PCMF2USB3SU903
A1A2
A3A4
B1
B2
C1C2
C3C4
-
+
Vs+
Vs- Vref
U910SGM8710YN6G/TR
31
4
62 5
-
+
V+
V-
U909SGM8709YN5G
3
1
4
52
J902
PJ1-021
132
F901
7A
1 2
R91610K5%
C9020.1uF50V
D910BZX585-B3V3
AC
R926 0 5%
C929100UF16V
R942 10.0K 1%
C9350.022uF50V
R906 4.7K
C916 0.1uF50V
R93819.6K1%DNP
R94444.2K
1%
D902A C
D908
PTVS24VS1UR
AC
Q902BSS84LT1
1
32
C92747uF10V
C9131000pF
50V
Q909
AON7405
3
4
21
5
C919 0.1uF 50V
R93644.2K1%
C915 4.7uF10V
R907 4.7K
Q910AON7405
3
4
21
5
C9014.7uF10V
R93210K
DNP
5%
Q9032SK30182
13
TV
S905
ES
D5B
5.0
ST
1G
DN
P1
2
C930100UF16V
C920 0.1uF 50V
C9330.1uF50V
C9260.01UF50V
CMF+ESD
A1,3,5
A2,4,6
B1,B2,B3
C1,3,5
C2,4,6
PCMF3USB3SU902
A1A2
A3A4
A5A6
B1
B2
B3
C1C2
C3C4
C5C6
R930100K1%
R928 0 5%R9473.3K
R940 0 5%
R93724.3K1%
C9114.7uF10V
C9370.47UF50V
R949220K
R911
4.7
KD
NP
C9360.022uF50V
R927 0 5%
R908 4.7K
C9280.1uF50V
TV
S904
ES
D5B
5.0
ST
1G
DN
P1
2
R933249K1%
U906NX5P3290
VIN1A1
VIN2A2
ILIMA3
FLTA4
VC
P1
B1
VC
P2
B2
GN
D1
B3
EN
B4
VC
P3
C1
VBUS3C2
GN
D2
C3
FOC4
VBUS1D1 VBUS2D2
GN
D3
D3
CA
PD
4 R92423.2K1%
R941 0 5%
R92553.6K1%
Q9072SK30182
13
C90310uF35V
R92010K5%
D907B330A
A C
C90947uF10V
R9341K
C914 2.2uF10V
R929 0 5%
VBAT LDO
BYPASS RAIL
INTERNAL LDO
VBUS LDO
BAT
U907
PTN5110DHQ
EN
_S
NK
12
VDD3
BYPASS4
ILIM_5V_VBUS6
I2C_SDA7I2C_SCL8
VCONN_IN12
FAULT_N11
ALERT_N10
DBG_ACC9
EN
_S
RC
16
VBUS15
CC214 CC113
FRS_EN1
SLV_ADDR5
GND17
C92422uF35V
R918
1K 5%
C931100UF16V
C9120.1uF50V
TV
S903
ES
D5B
5.0
ST
1G
12
D901ZLLS400
AC
F902
7A
1 2
Q906IRLML6401 1
3 2
C9250.1uF50V
C9100.1uF50V
C917 0.1uF 50V
C932100UF16V
C9040.1uF50V
R909
4.7
KD
NP
U901
PTN36043
RX_AP_+18
RX_AP_-17
TX_AP_+15
TX_AP_-14
TX_CON_1+6
TX_CON_1-7
RX_CON_1+2
RX_CON_1-3
TX_CON_2+12
TX_CON_2-11
RX_CON_2+9
RX_CON_2-8
SEL16
CH1_SET1/RXDE1
CH1_SET2/TXEQ4
CH2_SET1/TXDE13
CH2_SET2/RXEQ10
VDD1V85
GND19
R94644.2K1%
R93591K
R9031M1%
89
12
76
5
34
J903
USB_TYPE_A
VBUS1
D-2
D+3
GND4
G1S1
G2S2 SSRX-
5
SSRX+6
GND_DRAIN7
SSTX-8
SSTX+9G3S3
G4S4
TV
S902
ES
D5B
5.0
ST
1G
12
C907 0.1uF 50V
R914
10K 5%
R9021.2M1%
C918 0.1uF 50V
R917 10K 5%
R93919.6K1%DNP
C908 0.1uF 50V
U905NX5P3090UK
ENA1
FAULTA2
ILIMA3
VINT1B1
VINT2B2
GN
D1
B3
VINT3C1
VBUS1C2
GN
D2
C3
VBUS2D1
VBUS3D2
GN
D3
D3
R901 4.7K
C9344700pF50V
L901120OHM
21
R910
4.7
KD
NP
R931 10K 5%DNP
D903
A C
D904ZLLS400
A C
R94344.2K
1%
C92322uF35V
C905 0.1uF 50V
SSTXN2
SSTXP1SSTXN1
SSTXP2 USB_DPUSB_DN
SSTXP2SSTXN2
SSTXP1SSTXN1
CC1CC2
SBU1SBU2
USB_DNUSB_DP
DEBUG_ACCESSFRS_EN
FRS_EN
USB_LD_nFLT
CC1CC2
USB_LD_nFLTILIM_5V_VBUS
ILIM_5V_VBUS
EN_SNK
PWR_PATH_EN
VSYS_IN
USB_HOST_RXPUSB_HOST_RXN
USB_HOST_TXNUSB_HOST_TXP
USB_HOST_DNUSB_HOST_DP
USB_HOST_VBUS
EN_SRC
SSRXN2SSRXP2
SSRXN1SSRXP1
ILIM
SSRXP1SSRXN1
SSRXP2SSRXN2
VREF_1V2
VREF_1V2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HDMI data EMI/ESD
HDMI_D2P
HDMI_D2NHDMI_D1P
HDMI_D1NHDMI_D0P
HDMI_D0NHDMI_CLKP
HDMI_CLKNHDMI_CEC
HDMI_DDC_SCLHDMI_DDC_SDA
HDMI_5VHPD
HDMI TYPEA
HDMI 2.0a TX
RC0201FR-07604RL
GND
DCDC_5V
GND
VDD_PHY_1V8GND
VDD_PHY_1V8GND
VDD_3V3
HDMI_CLKP
HDMI_TXP0
HDMI_CLKN
HDMI_TXN0
HDMI_AUXPHDMI_AUXN
HDMI_HPD
HDMI_DDC_SDAHDMI_DDC_SCL
HDMI_CECHDMI_TXP2
HDMI_TXP1
HDMI_TXN2
HDMI_TXN1
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
HDMI
<JW>
<Approver>
<JW>
13 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
HDMI
<JW>
<Approver>
<JW>
13 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
HDMI
<JW>
<Approver>
<JW>
13 23
____X____
C1009 0.1uF 10V
F1001PICOSMDC035S
1 2
C1007 0.1uF 10V
Q1003BNX3020NAKS
5
43
R1011 0DNP
5%
Q1002ANX3020NAKS
2
16
C1008 0.1uF 10V
Q1001BNX3020NAKS
5
43
C10020.1uF50V
R10136041%
R10091.5K1%
Q1001ANX3020NAKS
2
16
D1001ZLLS400
A C
R10126041%
D1N
G_D1
D2P
D0P
G_CLK
G_D2
D1P
D2N
G_D0
D0N
CLKN
SDA
CEC
SCL
G_DDC
Utility
CLKP
TYPE A
GND
+5V
HPD
J1001CON HDMI 1X19
123456789
10111213141516171819
G1G2G3G4
CMF+ESD
PCMF3HDMI2SU1001
A1A2
A3A4
A5A6
B1
B2
B3
C1C2
C3C4
C5C6
R10041.5K1%
C1006 0.1uF 10V
R10021M1%
R10156041%
TV
S1004ES
D5B
5.0
ST
1G
12
C1005 0.1uF 10V
R10146041%
C1003 0.1uF 10V
D1003
ZLLS400
AC
R10166041%
CMF+ESD
PCMF2HDMI2SU1002
A1A2
A3A4
B1
B2
C1C2
C3C4
C1004 0.1uF 10V
TV
S1005ES
D5B
5.0
ST
1G
12
TV
S1003ES
D5B
5.0
ST
1G
12
R10176041%
R100727K1%
C1011 1uF 25 V
Q1004BNX3020NAKS
5
43
R10196041%
C1012 1uF 25 V
C100110uF
DNP
25V
C1010 0.1uF 10V
Q1004ANX3020NAKS
2
16
R10186041%
Q1003ANX3020NAKS
2
16
TV
S1002ES
D5B
5.0
ST
1G
12
Q1002BNX3020NAKS
5
43
HDMI_DDC_SDA_CNHDMI_DDC_SCL_CN
HDMI_CEC_CN
HDMI_TXP2_CN
HDMI_TXP1_CN
HDMI_TXP0_CN
HDMI_CLKP_CN
HDMI_TXN2_CN
HDMI_TXN0_CN
HDMI_TXN1_CN
HDMI_CLKN_CN
HDMI_HPD/HEAC-_CN
HDMI_Utility/HEAC+_CN
HDMI_CLKP_CN
HDMI_TXP0_CN
HDMI_HPD/HEAC-_CNHDMI_Utility/HEAC+_CN
HDMI_CLKN_CN
HDMI_TXN0_CN
HDMI_CLKP_C
HDMI_TXP0_C
HDMI_CLKP
HDMI_TXP0
HDMI_CLKN
HDMI_TXN0
HDMI_AUXPHDMI_AUXN
HDMI_AUXP_CHDMI_AUXN_C
HDMI_TXN0_C
HDMI_CLKN_C
HDMI_TXP1_CN
HDMI_TXP2_CN
HDMI_TXN1_CN
HDMI_TXN2_CN
HDMI_TXP1_C
HDMI_TXP2_CHDMI_TXN2_C
HDMI_TXN1_C
DCDC_5V_CN
HDMI_TXP2
HDMI_TXP1
HDMI_TXN2
HDMI_TXN1DCDC_5V_CN
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
# HP_DET: LOW : REMOVE HIGH : PLUG
MICHSL HSR GND
3.5mm POLE
Audio DAC
24-bit 192kHz Stereo DAC 2Vrms Line Out
HP JACK 3.5mm
2Vrms Line Out, not for Headset!
CTIA standard
GND
GND
VDD_3V3
GND
GND
VDD_3V3
GND
GND
SAI2_TXFSSAI2_TXD
AUD_nMUTE
SAI2_MCLKSAI2_TXC
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
CODEC
<JW>
<Approver>
<JW>
14 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
CODEC
<JW>
<Approver>
<JW>
14 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
CODEC
<JW>
<Approver>
<JW>
14 23
____X____
J1101
SPJ-31060AD
143652R1101 560 5%
TV
S1101
ES
D5B
5.0
ST
1G
12
C11091uF25 V
TV
S1103
ES
D5B
5.0
ST
1G
12
C11044.7uF10V
TV
S1102
ES
D5B
5.0
ST
1G
12
L1104
120OHM
21R1103 0 5%
TV
S1104
ES
D5B
5.0
ST
1G
12
R1104 0 5%
R1102 560 5%R110810K5%
C11032700pF50V
R110910K5%
C11022700pF50V
U1101
WM8524CGEDT
LINEVOUTL1
CPVOUTN2
CPCB3
LINEGND4
CPCA5
LINEVDD6
DACDAT7 LRCLK8 BCLK9 MCLK
10
MUTE11
AIFMODE12
AGND13
VMID14
AVDD15
LINEVOUTR16
C11112.2uF10V
C11101uF25 V
C11014.7uF10V
LINEVDDAVDD
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1.1 V
# 100-Ohm differential pairs
Power-on Strapping Pins
GTX_CLK / RX_CLK 125 MHz at 1000 Mbps, 25 MHz at100 Mbps, and 2.5 MHz at 10 Mbps digital clock input
RGMII 10/100/1000 Ethernet
PHY PIN Definition
RXD0
PHY CFG
RXD1
LED_ACT
RX_DV
RXD2
RX_CLK
RXD3
LED_LINK1000
PHYADDRESS0
PHYADDRESS1
PHYADDRESS2
MODE[0]
MODE[1]
MODE[2]
MODE[3]
INT_SELECT
LED_ACT and RXD1-0 set the lower three bits of thephysical address. The upper two bits of the physicaladdress are set to the default, “00”.
00000001001000110100010101100111101111101111Others
1000 Base-T, RGMII;1000 Base-T, SGMII;1000 Base-X, RGMII, 50Ω;1000 Base-X, RGMII, 75Ω;1000 Base-X/T, TRANS, 50Ω;1000 Base-X/T, TRANS, 75Ω;100 Base-FX, RGMII, 50Ω;100 Base-FX/TX, TRANS, 50Ω;RMII, copper fiber auto-detection;100 Base-FX, RGMII, 75Ω;100 Base-FX/TX, TRANS, 75Ω;Reserved
Default
0
0
1
0
0
0
0
1
Power-on Strapping Pins CFG
0: INT ; 1:GPIO
470pF for LED
EMI Filter Reserved Low Profile Tab-UP RJ45 with Magnetics / LED
OD
OD
Support external25 MHz 1.2 V swing clock input through this pin.
1 Gb/s Link / Active
100Mb/s Link / Active
GND
GND
GND
GND
GND GND
GND
GND
GND
GND
VDD_3V3
ENET_DVDDL_1V1
ENET_VDDH_2V5
NVCC_ENET_2V5
ENET_DVDDL_1V1
GND
ENET_VDDIO_2V5
ENET_VDDH_2V5
GND GND_CHASSIS
VDD_3V3 ENET_VDDH_2V5
GND
GND
GND_CHASSIS
GND
ENET_RXC
ENET_RX_CTL
ENET_RD0
ENET_TXC
ENET_TD0
ENET_TX_CTL
ENET_TD1ENET_TD2ENET_TD3
ENET_RD1ENET_RD2ENET_RD3
ENET_nRST
ENET_nINT
ENET_MDIOENET_MDC
ENET_WoL
ENET_RXCENET_RX_CTL
ENET_RD0
ENET_TXCENET_TD0
ENET_TX_CTL
ENET_TD1ENET_TD2ENET_TD3
ENET_RD1ENET_RD2ENET_RD3
ENET_nRSTENET_MDIOENET_MDC
ENET_nINTENET_WoL
CLKO_25MHz
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
Ethernet
<JW>
<Approver>
<JW>
15 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
Ethernet
<JW>
<Approver>
<JW>
15 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
Ethernet
<JW>
<Approver>
<JW>
15 23
____X____
R1210 0 5%
R1218 10K 5%
R12252.49K
DNP
1%
L1201
120OHM
21
R1209 0 5%
R1219 10K 5%
C1218470PF
DNP50V
R1212 10K DNP5%
C12110.22uF50V
R1220 10K 5%
R1215 10K DNP5%
C12090.22uF50V
C12051uF25 V
L1203
120OHM
21
R1227 0 5%DNP
R1221 10K 5%
C12120.22uF50V
RGMII I/O
VDDH_REG
2.5 V (3.3 V tolerant)
OD
AR8031
U1201
RST2
LX
3
VD
D33
4
XTLO6
XTLI7
AVDDL18
RBIAS9
VD
DH
_R
EG
10
TRXP011
TRXN012
AVDDL313
TRXP114
TRXN115
AV
DD
33
16
TRXP217
TRXN218
AVDDL419
TRXP320
TRXN321
PPS22
LED_ACT23
LED_LINK100024CLK_25M
25 LED_LINK10_10026
RXD327 RXD228
VD
DIO
_R
EG
29
RXD130 RXD031
RX_DV32
RX_CLK33
TX_EN34
GTX_CLK35
TXD036
TXD137
TXD238
TXD339
WOL_INT40
SD41
SON42
GN
D49
MDC1
INT5
SOP43
AVDDL244
SIN45 SIP46
DVDDL47
MDIO48
R1202 270 5%
C12130.22uF50V
R1203 270 5%
L1202
4.7UH
1 2
C122122PF50V
TP1202
C12140.22uF50V
D1201 ZLLS400
AC
R1216 10K 5%
C1217470PF
DNP50V
R12112.37K1%
C1216 1000pf 2KV
C12020.22uF50V
R122410K5%
TP1201
R1207 10K 5%
R1208 1M
C120810uF25V
C12040.22uF50V
R120610K5%
C12011uF25 V
C12070.22uF50V
R1201 0 5%
R122205%
C12031uF25 V
C122022PF50V
R122310K5%
Y1201
25MHz
1 4
32
R120510K5%
R1217 10K 5%
C1219470PF
DNP50V
R12261.2K
DNP
1%
R12041.5K1%
R1214 10K 5%
R1213 10K 5%
Inside RJ45 Jack
J7
J6
J4
J2
1CT:1CT
1CT:1CT
4x75 ohms2KV1000pF
Green LED
Yellow LED
Yellow LED
J8
J5
J3
J1
D-
D+
B-
C-
C+
B+
A-
A+
UTP Side
0.1uF X4
Y
G
Y
G
Green LED
Shield
J1201
HR851178C
1615
1
2
3
4
5
6
7
8
9
10
11
12
13
14
C120610uF25V
ENET_AVDDL_1V1
ENET_SD
ENET_LX
PHYADDRESS2ENET_XTLO
ENET_XTLI
ETH_TRX0_PETH_TRX0_NETH_TRX1_PETH_TRX1_NETH_TRX2_PETH_TRX2_NETH_TRX3_PETH_TRX3_N
LED_LINK10_100
LED_ACT
LED_LINK1000
MODE[1]MODE[3]
MODE[0]
ENET_AVDD33
ENET_VDD33
MODE[2]
PHYADDRESS0PHYADDRESS1
ENET_VDDH_2V5
ENET_VDDIO_2V5
PHYADDRESS0
PHYADDRESS1
LED_LINK1000
MODE[2]
MODE[0]
MODE[1]
MODE[3]
PHYADDRESS2
ENET_nRST
ENET_RX_CTL
ENET_TX_CTLENET_TXCENET_TD0ENET_TD1ENET_TD2ENET_TD3
ENET_RXCENET_RD0ENET_RD1ENET_RD2ENET_RD3
ENET_WoLENET_nINTENET_MDCENET_MDIO
MDCMDIO
PHY_CLKOUTPPS/GPIO
WOL_INT
ETH_TRX3_N
ETH_TRX3_P
ETH_TRX2_N
ETH_TRX2_P
ETH_TRX1_N
ETH_TRX1_P
ETH_TRX0_P
ETH_TRX0_N
ENET_VDDIO_2V5
LINKACTLED_ACT
Link / ActiveLED_LINK1000
LED_LINK10_100
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
WiFi/BT 802.11a/b/g/n/ac + Bluetooth 4.1/ EDR
PCIe MEMS OSC
PU
PD
PD
CPU CLK
NOTE:This component share PCB packageWhen use 9FGV0241 PIN5: GND;PIN7:1.8VWhen use PI6CFGL201BZDIEX PIN5:1.8V;PIN7:3.3V
DO
DI
DO
DI
PD
DO
OD
DO
PD
PU
PD
OD
DO
VDD_3V3
GND
GND
GND
GND
GND
GND
GND
GND
VDD_1V8
GND
GND
GND
GND
GND
GND
GND
VDD_1V8
VDD_1V8
GND GND
VDD_3V3
VDD_3V3
GND
VDD_1V8
VDD_3V3
GND
GND
VDD_3V3
VDD_3V3
GND
GND
GND
SAI3_RXDSAI2_RXD
PCIE1_nCLKREQ
PCIE1_REF_CLKP
PCIE1_REF_CLKN
I2C2_SDAI2C2_SCL
CLK2_NCLK2_P
UART3_CTSUART3_RTS
UART3_RXDUART3_TXD
SAI2_RXFSSAI3_TXFSSAI2_RXCSAI3_TXC
REF_CLK_32K
SAI3_TXD
WL_nPERSTWL_nWAKE
BT_REG_ON
BT_RF_KILLBT_DEV_WAKE
WL_REG_ON
PCIE1_RXPPCIE1_RXN
PCIE1_TXPPCIE1_TXN
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
WiFi/BT
<JW>
<Approver>
<JW>
16 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
WiFi/BT
<JW>
<Approver>
<JW>
16 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
WiFi/BT
<JW>
<Approver>
<JW>
16 23
____X____
C13280.3PF
DNP50V
C13160.01UF50V
R1324561%DNP
C13171uF25 V
R1335 0
L13051nHDNP
12
L13031nHDNP
12
LBEE5U91CQ-TEMP
U1301A
BT_RF_KILL4
PCIE_CLKREQ_L9
PCIE_RST_L10
PCIE_WAKE_L11
GPS_COEX_WOW12
QOW13
BT_WAKEUP_HOST14
BT_LED15
LF_CLK_IN17
ANT_020
BT_EN22
WL_EN23
ANT_129
LTE_PRI31
LTE_SYNC32
LTE_ACTIVE33
BT_UART_TXD35
BT_UART_RXD36
BT_UART_CTS37
BT_UART_RTS38
PCM_SYNC39
PCM_IN40 PCM_CLK41
PCM_OUT42
CLK_REQ_OUT44
GPIO245
GPIO1046
PCIE_TX_P48
PCIE_TX_N49
PCIE_REFCLK_P51
PCIE_REFCLK_N52
PCIE_RX_N54 PCIE_RX_P55
GPIO457GPIO358
GPIO159
GPIO560
GPIO661
GPIO869
GPIO082
GPIO983
GPIO784
R1309 0 5%
E1301
ACM3-5036-A1-CC-S
FEED_13 GND_1
1
GND_22
R1312 0
R1319 0
J1301MXC3N2001
12
3
R1327 0 5%
R13234701%DNP
C132318PF50V
C1325 10uF 25V
C1304 0.1uF 50V
R1337 0
R1336 0
R1329 0
R1313 0
R1348 0 5%
R1304 0 5%
R1321 0
R1325561%DNP
C1305 0.1uF 50V
R1330 0
C1313 0.1uF DNP50V
R1318 0DNP
Q13012SK30182
13
L13041nHDNP
12
Y1301
25MHz
1 4
32
L130815NHDNP
12
R1305 0
L13021nHDNP
12
C1314 0.1uF DNP50V
C13270.1uF50V
R1316 0
R1302 0 5%
TP1301
L1306
120OHM
21
R1344 0DNP
C13151uF25 V
C1326 4.7uF 10V
R1310 0 5%
C13290.3PF
DNP50V
C13210.01UF50V
C1309 4.7uF 10V
R1349 0 5%
R1333 0
L1307
120OHM
21
R1306 0 5%
R1345 0
C13023.9pF
DNP50V
C13201uF25 V
9FGV0241AKLF
U1302
SDATA_3.39
SADR/REF1.84
CKPWRGD_PD22
SCLK_3.38
OE012
OE119
SS_EN_TRI23
X1_251
DIF014
DIF118
DIF013
DIF117
X22
EP
AD
25
GN
D_1
10
GN
D_2
21
GN
DA
15
GN
DD
IG6
GN
DR
EF
5
GN
DX
TA
L24
VD
D1.8
_1
11
VD
D1.8
_2
20
VD
DA
1.8
16
VD
DD
IG1.8
7
VD
DX
TA
L1.8
3
R1315 0
D1301
GREEN LED
A C
R1334 0
R1307 0 5%
R1311 0 5%
R134049.91%DNP
C13013.9pF
DNP50V
C13220.01UF50V
R1355 0
R1331 0
R1308 0 5%
E1302
ACM3-5036-A1-CC-S
FEED_13 GND_1
1
GND_22
R134310K5%
R1350 1K 5%
R1328 0
C13190.01UF50V
R1354 0
C132418PF50V
R134149.91%DNP
R1332 0
D1303ZLLS400
AC
C1308 4.7uF 10V
R1346 0DNP
L130915NHDNP
12
R133905%DNP
R1352 0
R1314 0
D1304ZLLS400
AC
R1317 0
LBEE5U91CQ-TEMP
U1301B
SWREG_IN11
SWREG_IN22
GND13
VDDIO_GPIO15
VDDIO_GPIO06
VDD_3P3_17
VDD_3P3_28
GND216
GND318
GND419
GND521
GND624
VDD_FEM125
VDD_FEM226
GND727
GND828
GND930
GND1034
VDDIO_XTAL43
GND1147
GND1250
GND1353
GND1456
GND1562
SWREG_FB163
SWREG_FB264
GND1665
SWREG_OUT166
SWREG_OUT267
GND1768
GND1870
GND1971
GND2072
GND2173
GND2274
GND2375
GND2476
GND2577
GND2678
GND2779
GND2880
GND2981
GND3085
GND3186
GND3287
GND3388
GND3489
GND3590
GND3691
GND3792
R1356 100K
R13224701%DNP
R1347 0
J1302MXC3N2001
12
3
C1310 4.7uF 10VC13180.01UF50V
R1351 0
R1320 0
R133805%DNP
R134210K5%
R1353 0
R1326 0 5%
L13011.5UH
12
C13074.7uF10V
WIFI_PCIE_RX_PWIFI_PCIE_RX_N
WIFI_PCIE_CLKNWIFI_PCIE_CLKP ANT0_OUT
ANT1 ANT1_OUT
WIFI_PCIE_TX_PWIFI_PCIE_TX_N
GND
GND
GND
GNDANT0
WIFI_PCIE_nCLKREQ
PCIE1_REQ
PCIE1_REF_CLKP
WIFI_PCIE_CLKP
PCIE1_REF_CLKN
WIFI_PCIE_CLKN
WIFI_PCIE_CLKNWIFI_PCIE_CLKP
WIFI_PCIE_nCLKREQ
WIFI_PCIE_REFCLK_NWIFI_PCIE_REFCLK_P
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
M.2 (NGFF) CN
PCIe MEMS OSC
PU
PD
PD
PCIe M.2/NGFF
CPU CLK
1.2 V and 3.6 V 1.65 V and 5.5 V,
3.3V->1.8V Level Shifter
NOTE:This component share PCB packageWhen use 9FGV0241 PIN5: GND;PIN7:1.8VWhen use PI6CFGL201BZDIEX PIN5:1.8V;PIN7:3.3V
PCIe PWR
# Standoff for M.2
# BT_REG_ON'H': on board WiFi/BT'L': M.2 BT enable
#Reserve for compatible design
TMP-WF-31812
GND
GND
VPCIe_3V3
GNDGND GND GND
VDD_1V8
GND
GND
GND
GND
GND
GND
GND
VDD_1V8
GND
VDD_1V8
VPCIe_3V3VDD_1V8
GNDGND
GND
VPCIe_3V3VDD_1V8
GNDGND
GND
VDD_1V8
GND
GND
GND
VDD_1V8
VDD_3V3
VDD_3V3 VPCIe_3V3
GND
GND GND
VPCIe_3V3
VPCIe_3V3
GND
VDD_3V3
GND
VPCIe_3V3
VDD_1V8
I2C2_SDAI2C2_SCL
PCIE2_nCLKREQ
SAI3_TXFSSAI3_TXC
SAI3_TXDSAI3_RXD
UART3_RTSUART3_CTS
UART3_TXDUART3_RXD
PCIE2_REF_CLKP
PCIE2_REF_CLKN
PCIe_nDIS
M2_I2C_SDAM2_I2C_SCL
SD2_CLK
SD2_DATA1SD2_DATA2
SD2_DATA0
SD2_DATA3
SD2_CMD
SD2_nRSTSDIO_WAKE
PCIE2_TXPPCIE2_TXN
PCIE2_RXPPCIE2_RXN
BT_DEV_WAKE
PCIe_nRSTPCIe_nWAKE
USB2_DNUSB2_DP
REF_CLK_32K
PCIe_nDIS
BT_REG_ON
BT_REG_ON
PCIe_nDIS
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Tuesday, September 26, 2017
mini-PCIe
<JW>
<Approver>
<JW>
17 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Tuesday, September 26, 2017
mini-PCIe
<JW>
<Approver>
<JW>
17 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Tuesday, September 26, 2017
mini-PCIe
<JW>
<Approver>
<JW>
17 23
____X____
BH1402.635" LONG
Q14052SK3018
2
13
D1405 ZLLS400AC
C14220.01UF50V
R1432 0 DNP
TP1403
C141239pF50V
R1417 0 DNP
Y1401
25MHz
1 4
32
R1434 0 DNP
C141610uF25V
R141510K5%
Q1402IRLML64011
32
L1401
120OHM
21C14250.01UF50V
R1402 0 5% DNP
R1436 0 DNP
R1421 0
R1455 0
TP1402
R1462515%
C14260.01UF50V
C14380.01UF50V
+ C1417220uF
10V
C1421 0.1uF 50V
R146110K5%
R1448 0
R1459 0 5%
R1443 0R145010K5%
R1401 0 5% DNP
R143710K5%
R145810K5%
R146410K5%
R142505%DNP
D1402ZLLS400
AC
C14311uF25 V
R1442 0
R1424 0
R146022K5%C1401
1uF25 V
D1403ZLLS400
AC
R142749.91%DNP
R1452 0 5%
R14631K5%
DNP
C14351uF25 V
BH1401.635" LONG
NTBA104GU12
U1402
VC
CA
1
A12
A23
A34
A45
GN
D6
B47B38B29B110
OE12
VC
CB
11
R1411 0
BH1405SMTSO-M1.6-2.25ET
R1429 0 DNP
C141039pF50V
Q14012SK30182
13
C14390.1uF50V
TP1406BH1404
.635" LONG
C14340.01UF50V
R1431 0 DNP
R1456 0
R1405 0
C143018PF50V
BH1406SMTSO-M25-2ET
R1449 0
TP1404
+ C1419220uF
10VDNP
C14401uF25 V
C14031uF25 V
+ C1418220uF
10VDNP
R1433 0 DNP
C14150.1uF50V
R141610K5%
C141139pF50V
R141910K5%
R1435 0 DNP
R1454 0DNP
R1447 0
C14241uF25 V
R1422 0
R1418 0 DNP
R1441 0
TP1401
Q14032SK3018
2
13
C14371uF25 V
C1420 0.1uF 50V
C142918PF50V
NTBA104GU12
U1403
VC
CA
1
A12
A23
A34
A45
GN
D6
B47B38B29B110
OE12
VC
CB
11
BH1403.635" LONG
D1404 ZLLS400
AC
C14130.1uF50V
C14140.1uF50V
Q14042SK3018
2
13
R1446 0
L1402
120OHM
21
R142605%DNP
C14320.01UF50V
R1444 0
R1438 0 5%
R1423 0
R142849.91%DNP
R1445 0
C14420.022UF
C14020.01UF50V
C14410.22uF
50V
D1401ZLLS400
AC
9FGV0241AKLF
U1401
SDATA_3.39
SADR/REF1.84
CKPWRGD_PD22
SCLK_3.38
OE012
OE119
SS_EN_TRI23
X1_251
DIF014
DIF118
DIF013
DIF117
X22
EP
AD
25
GN
D_1
10
GN
D_2
21
GN
DA
15
GN
DD
IG6
GN
DR
EF
5
GN
DX
TA
L24
VD
D1.8
_1
11
VD
D1.8
_2
20
VD
DA
1.8
16
VD
DD
IG1.8
7
VD
DX
TA
L1.8
3
R1453 0 5%
TP1407
C14360.01UF50V
M.2 / NGFF
1.8V
1.8V
1.8V
1.8V
KEY E
J1401
CON_MINI CARD_RA
UART_RTS36UART_CTS34
SDIO_DATA013 SDIO_CMD11 SDIO_CLK
9
I2S_SD_IN12I2S_WS10
GND1069
REFCLK_P047
GND1175
I2S_SD_OUT14
I2C_CLK60
VEN_DEF138
ALERT62
VEN_DEF342
USB_D+3
VEN_DEF240
REFCLK_N049
USB_D-5
PET_P035
PET_N037
PER_P041
PER_N043
PERST052
CLKREQ053
PEWAKE055
SDIO_DATA217 SDIO_DATA115
SDIO_WAKE21 SDIO_DATA319
SDIO_RST23 UART_RXD
22UART_WAKE20
UART_TXD32
I2C_DATA58
I2S_SCK8
COEX_TXD48COEX_RXD46COEX344
SUSCLK50
LED216
LED16
W_DISABLE254
REFCLK_N173 REFCLK_P171
3V3_372
3V3_474
W_DISABLE156
PET_P159
PET_N161
PER_P165
PER_N167
UIM_SWP/PERST166
UIM_PWR_SNK/CLKREQ168
UIM_PWR_SRC/PEWAKE170
RESERVED64
GND11
GND27
GND318
GND439
GND533
GND645
GND751
GND857
GND963
3V3_12
3V3_24
R1412 0
R1451100KDNP
R1430 0 DNP
R1457 0DNP
C14230.01UF50V
TP1405
C14331uF25 V
PCIE_REQ
PCIe_nCLKREQ
PCIE2_REF_CLKP
PCIE2_REF_CLKP_CN
PCIE2_REF_CLKN
PCIE2_REF_CLKN_CN
M2_PCM_CLKM2_PCM_SYNCM2_PCM_OUTM2_PCM_IN
M2_UART_TXDM2_UART_RXDM2_UART_CTSM2_UART_RTS
M2_PCM_CLKM2_PCM_SYNCM2_PCM_INM2_PCM_OUT
M2_I2C_SCLM2_I2C_SDA
M2_UART_RXD
M2_UART_TXD
M2_UART_CTSM2_UART_RTS
PCIE2_REF_CLKN_CNPCIE2_REF_CLKP_CN
PCIe_nCLKREQ
M2_USB_DPM2_USB_DN
M2_SD_WAKEM2_SD_nRST
M2_SD_DAT3
M2_SD_DAT0
M2_SD_DAT2M2_SD_DAT1
M2_SD_CMDM2_SD_CLK
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Camera Interface
DSI TS I2CDSI LCD IF Camera/DSI LCD
NULL
NULL NULL
GND
GND
VDD_1V8
VDD_3V3
DCDC_5V
VDD_12V
VDD_1V8
NVCC_3V3
NVCC_3V3VDD_1V8
VDD_1V8
GND
VDD_1V8
VDD_3V3
DCDC_5V
VDD_12V
GND
VDD_1V8
VDD_1V8 VDD_3V3 DCDC_5V
GND
VDD_1V8 VDD_3V3 DCDC_5V
GND
GND
VDD_1V8
VDD_3V3
DCDC_5V
VDD_12V
GND
VDD_1V8
VDD_1V8 VDD_3V3 DCDC_5V
GND
DSI_CKNDSI_CKP
DSI_TS_nINTDSI_BL_PWM
DSI_EN I2C1_SDA
I2C1_SCL
CSI_nRST
CSI_P1_PWDN
CLKO2
CSI_P1_CKNCSI_P1_CKP
CSI_P1_DN0CSI_P1_DP0
CSI_P1_DN1CSI_P1_DP1
CSI_P1_DN2CSI_P1_DP2
CSI_P1_DN3CSI_P1_DP3
CSI_nRST
CSI_P2_PWDN
CLKO2
CSI_P2_CKNCSI_P2_CKP
CSI_P2_DN0CSI_P2_DP0
CSI_P2_DN1CSI_P2_DP1
CSI_P2_DN2CSI_P2_DP2
CSI_P2_DN3CSI_P2_DP3
M2_I2C_SDA
M2_I2C_SCL
DSI_DP0DSI_DN0
DSI_DN1DSI_DP1
DSI_DP2DSI_DN2
DSI_DN3DSI_DP3
I2C_SDA_1V8
I2C_SCL_1V8
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
MIPI/DSI/CSI
<JW>
<Approver>
<JW>
18 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
MIPI/DSI/CSI
<JW>
<Approver>
<JW>
18 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
MIPI/DSI/CSI
<JW>
<Approver>
<JW>
18 23
____X____
R152010K5%
R151010K5%
R152210K
DNP
5%
C15194.7uF6.3V
IPA
SS
_IN
TE
RN
AL
x1
J1502
IPASS MINISAS
GND3A7
GND4A12
GND1A1
GND2A4
GND5A15
GND6A18
RX1_NA6RX1_PA5
RX0_NA3RX0_PA2
SIDEBAND_7A8
RX3_NA17
RX2_NA14RX2_PA13
RX3_PA16
SIDEBAND_3A9
SIDEBAND_4A10
SIDEBAND_5A11
GND7B1
TX0_PB2
TX0_NB3
GND8B4
TX1_PB5
TX1_NB6
GND9B7
SIDEBAND_0B8
SIDEBAND_1B9
SIDEBAND_2B10
SIDEBAND_6B11
GND10B12
TX2_PB13
TX2_NB14
GND11B15
TX3_PB16
TX3_NB17
GND12B18
T1T1
T2T2
T3T3
T4T4
T5T5
T6T6
T7T7
T8T8
D1506 ZLLS400
A C
R150910K5%
IPA
SS
_IN
TE
RN
AL
x1
J1501
IPASS MINISAS
GND3A7
GND4A12
GND1A1
GND2A4
GND5A15
GND6A18
RX1_NA6RX1_PA5
RX0_NA3RX0_PA2
SIDEBAND_7A8
RX3_NA17
RX2_NA14RX2_PA13
RX3_PA16
SIDEBAND_3A9
SIDEBAND_4A10
SIDEBAND_5A11
GND7B1
TX0_PB2
TX0_NB3
GND8B4
TX1_PB5
TX1_NB6
GND9B7
SIDEBAND_0B8
SIDEBAND_1B9
SIDEBAND_2B10
SIDEBAND_6B11
GND10B12
TX2_PB13
TX2_NB14
GND11B15
TX3_PB16
TX3_NB17
GND12B18
T1T1
T2T2
T3T3
T4T4
T5T5
T6T6
T7T7
T8T8
R152310K5%
C15110.1uF50V
C15130.1uF50V
Q15032SK3018
2
1 3
C15240.1uF50V
C15164.7uF6.3V
R152410K
DNP
5%
IPA
SS
_IN
TE
RN
AL
x1
J1503
IPASS MINISAS
GND3A7
GND4A12
GND1A1
GND2A4
GND5A15
GND6A18
RX1_NA6RX1_PA5
RX0_NA3RX0_PA2
SIDEBAND_7A8
RX3_NA17
RX2_NA14RX2_PA13
RX3_PA16
SIDEBAND_3A9
SIDEBAND_4A10
SIDEBAND_5A11
GND7B1
TX0_PB2
TX0_NB3
GND8B4
TX1_PB5
TX1_NB6
GND9B7
SIDEBAND_0B8
SIDEBAND_1B9
SIDEBAND_2B10
SIDEBAND_6B11
GND10B12
TX2_PB13
TX2_NB14
GND11B15
TX3_PB16
TX3_NB17
GND12B18
T1T1
T2T2
T3T3
T4T4
T5T5
T6T6
T7T7
T8T8
R152110K5%
C15120.1uF50V
D1509 ZLLS400A C
R152510K5%
D1501 ZLLS400A C
C15264.7uF6.3V
D1505 ZLLS400A C
C15184.7uF6.3V
C15100.1uF50V
Q15042SK3018
2
1 3
C152510uF
25V
D1504 ZLLS400A C
C15230.1uF50V
C15090.1uF50V
R150510K5%
C15220.1uF50V
D1507 ZLLS400
A C
C15154.7uF6.3V
R150610K5%
C15214.7uF6.3V
D1508 ZLLS400A C
R1501 0
C151710uF
25V
C15140.1uF50V
D1503 ZLLS400A C
R151910K5%
R150810K5%
R1502 0
C152010uF
25V
D1502 ZLLS400A C
R150710K5%
DSI_TS_SCLDSI_TS_SDA
DSI_TS_SDA
DSI_TS_SCL
CSI_I2C_SDA
CSI_I2C_SCL
CSI_I2C_SDACSI_I2C_SCL
CSI_I2C_SDACSI_I2C_SCL
M2_I2C_SDA
M2_I2C_SCL
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MicroSD/Infrared/LED
# Push-Push
STATUS/PWR LED
Inferad Remote Control
Micro-SD
# LDO drop: 50 mV at 100 mA load !!!
SD3.0 IO PWR
SD3.0 PWR
# R1/R2 = (Vo-Vfb)/Vfb
# Default: 3.3V
Vfb=0.8V # 1.8V/3.3V
GND
VSD_3V3
GND
VDD_3V3
GND GND
VDD_3V3
GND
GND
NVCC_SD2
VDD_3V3 VSD_3V3
GND
GNDGND
GND
VDD_3V3
GND
NVCC_SD2
DCDC_3V3
SD2_nCD
SD2_CLK
IR_CAP
SD2_CMD
PWM_LED
SD2_DATA1SD2_DATA2
SD2_DATA0
SD2_DATA3
SD2_nRST
POR_B
SD2_VSELECT
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
SD/IR/LED/BTN
<JW>
<Approver>
<JW>
19 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
SD/IR/LED/BTN
<JW>
<Approver>
<JW>
19 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
SD/IR/LED/BTN
<JW>
<Approver>
<JW>
19 23
____X____
TP1602
Q16012SK3018
2
1 3
R161610K
5%
TV
S1602
ES
D5B
5.0
ST
1G
12
R1619 0 5%
C160647uF10V
R161210K5% Q1605
MMBT3904T
23
1
TVS1601ESD5B5.0ST1G
12
R16091K5%
C16110.1uF50V
Red
Grn
D1601LED_RED-GRN
213
4
C16011uF25 V
C16050.1uF50V
C16020.1uF50V
R1615 0 5%
R1620 0 5%
J1601
CONN_SD_CARD 9
DAT21
CD/DAT32
CMD3
VDD4
CLK5
VSS6
DAT07
DAT18
GND211
DET9
GND110
GND312GND413
R1606 0DNP
1%
C16031uF25 V
R1603 0 5%
R160722K5%
U1602IRM-V538/TR1
GN
D3
VOUT1
VC
C2
SH
IELD
4
R16221K5%
D1602
ES
D9L5.0
ST
5G
DN
PA
C
D1608
ZLLS400
AC
U1601
LDCL015MR
EN3
IN1
GND2 ADJ
4
OUT5
C16101uF25 V
C16070.22uF
50V
C16040.1uF50V
D1603
ES
D9L5.0
ST
5G
DN
PA
C
R1621 0 5%
D1604
ES
D9L5.0
ST
5G
DN
PA
C
Q1602IRLML64011
32C16090.1uF50V
C160847uF10V
R1617 0 5%
R1610475%
Q16042SK3018
2
13
R160510K5%
R1613 0 5% R1614 1K 5%
R1608515%
D1609
ZLLS400
DNP
AC
R1601499K1%
TP1601
D1607
ES
D9L5.0
ST
5G
DN
PA
C
D1605
ES
D9L5.0
ST
5G
DN
PA
C
Q16032SK3018
2
13
R1604160K1%
R1618 0 5%
D1606
ES
D9L5.0
ST
5G
DN
PA
C
R161110K5%
R1602330K
1%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
UART-USB DBG
BMOD TP for MFG TOOL
CPU SODIMM TST/DBG
TP for on-line MFG# CPU ONOFF Button
# System Reset Button
GND
GND
GND
GND
VUSB_REG_3V45
VDD_3V3
GND
VDD_3V3
GND
GND
GND
VBUS_USB_BDG
VDD_3V3
VDD_3V3
GND
GND
GND
USB_VBUS
DC_IN
GND
GND
ONOFF
SYS_nRST
USB1_DNUSB1_DP
BOOT_MODE0BOOT_MODE1
UART1_RXDUART1_TXD
UART2_TXDUART2_RXD
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
Debug UART
<JW>
<Approver>
<JW>
20 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
Debug UART
<JW>
<Approver>
<JW>
20 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
Debug UART
<JW>
<Approver>
<JW>
20 23
____X____
L1703 90OHM
21
4 3R1715 0 5%
C17030.1uF50V
TP1706
C17054.7uF6.3V
TV
S1701ES
D5B
5.0
ST
1G
DN
P1
2
C1707 4.7uF 10V
L1702120OHM
21
U1701
CP2105
REGIN7
VDD6
VIO5
VBUS8
D-4
D+3
RST9
SUSPEND/RI_SCI1
GPIO0_SCI/DCD_SCI24
GPIO1_SCI/DTR_SCI23
GPIO2_SCI/DSR_SCI22
TXD_SCI21
RTS_SCI19
CTS_SCI18
RXD_SCI20
GND2
SUSPEND/RI_ECI17
NC/DCD_ECI/VPP16
GPIO0_ECI/DTR_ECI15
GPIO1_ECI/DSR_ECI14
TXD_ECI13
RXD_ECI12
RTS_ECI11
CTS_ECI10
GND_PAD25
R1712 0 5%
GO
D1702LED ORANGE/GREEN
12
34
R1713 0 5%
R17044.7K5%
J1701MICRO_USB_TYPEB
VBUS1
D-2
D+3
ID4
GND5
S1
S1
S2
S2
S3
S3
S4
S4
S5
S5
S6
S6
C17061uF25 V
TP1709
R17031K5%
TP1707
R17021K5%
TP1708
TP1713
TP1701
R171605%
SW1702TACT SWTICH
1 2
3 4 5 6 7
TP1704
R1701 0DNP
5%
G O
D1703LED ORANGE/GREEN
12
34
TP1711
C17011uF25 V
TP1703
TP1712
R17071K5%
TP1702
R1706 0DNP
5%
R17081K5%
C17040.1uF50V
TP1710
SW1701TACT SWTICH
1 2
3 4 5 6 7
TP1705
D1701ESD7C3.3DT5G
DNP
2 1
3 R1714 0 5%
VBUS_CP210x
TX1_TOGGLERX1_TOGGLE
nSUSPEND0
nSUSPEND1
USB_DBG_DM_CNUSB_DBG_DP_CN
USB_DBG_DP
USB_DBG_DM
UART1_TXDUART1_RXD
UART2_TXDUART2_RXDUSB1_DPUSB1_DN
BOOT_MODE1BOOT_MODE0
UART1_RXD_MCUUART1_TXD_MCU
UART2_RXD_CPUUART2_TXD_CPU
TX0_TOGGLERX0_TOGGLE
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
EXP CN
XF2M-6015-1AH
2.54mm pitch, Reserve for MIC header
Add VDD_3V3 VPWR,VIO
VSYS
GND
GND
VDD_3V3
NAND_DATA[7:0]
SAI1_TXD0SAI1_TXD1SAI1_TXD2SAI1_TXD3SAI1_TXD4SAI1_TXD5SAI1_TXD6SAI1_TXD7
SAI1_TXC
SAI1_TXFS
SAI1_MCLK
SAI1_RXD0SAI1_RXD1SAI1_RXD2SAI1_RXD3SAI1_RXD4SAI1_RXD5SAI1_RXD6SAI1_RXD7
SAI5_MCLK
SAI5_RXC
SAI3_MCLK
SAI5_RXD0SAI5_RXD1SAI5_RXD2SAI5_RXD3
SAI5_RXFS
SAI3_RXC
SAI3_RXDSAI3_RXFS
SAI1_RXCSAI1_RXFS
SPDIF_EXT_CLK
SPDIF_RXSPDIF_TX
I2C3_SDAI2C3_SCL
NAND_nWENAND_nWPNAND_nREADY
NAND_nCE3
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
Expansion CN
<JW>
<Approver>
<JW>
21 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
Expansion CN
<JW>
<Approver>
<JW>
21 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
Expansion CN
<JW>
<Approver>
<JW>
21 23
____X____
R1802 0 DNP
R1803 0
J1801
XF2M-6015-1AH
11
22
33
44
55
66
77
88
99
1010
1111
1212
1313
1414
1515
1616
1717
1818
1919
2020
2121
2222
2323
2424
2525
2626
2727
2828
2929
3030
3131
3232
3333
3434
3535
3636
3737
3838
3939
4040
4141
4242
4343
4444
4545
4646
4747
4848
4949
5050
5151
5252
5353
5454
5555
5656
5757
5858
5959
6060
R1801 0 5%
TP1801
TP804
C180122uF35V
TP803
TP1802
C18020.1uF50V
SAI1_TXD0
SAI1_TXD2SAI1_TXD3
SAI1_TXD1
SAI1_TXD4SAI1_TXD5SAI1_TXD6SAI1_TXD7
SAI1_TXC
SAI1_TXFS
SAI1_MCLK
SAI1_RXD0
SAI1_RXD2SAI1_RXD3SAI1_RXD4
SAI1_RXD1
SAI1_RXD5SAI1_RXD6SAI1_RXD7
SAI5_MCLK
SAI5_RXC
SAI3_MCLK
SAI5_RXD1SAI5_RXD2SAI5_RXD3
SAI5_RXD0SAI5_RXFS
SAI3_RXC
SAI3_RXDSAI3_RXFS
SAI1_RXCSAI1_RXFS
SPDIF_TXSPDIF_RX
NAND_DATA7NAND_DATA6
NAND_DATA4NAND_DATA5
SAI3_MCLK
SAI3_RXC
SAI3_RXFSSAI3_RXD
SPDIF_EXT_CLK
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NOTE:
Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
NOTE
<JW>
<Approver>
<JW>
22 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
NOTE
<JW>
<Approver>
<JW>
22 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
C
Monday, September 25, 2017
NOTE
<JW>
<Approver>
<JW>
22 23
____X____
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ccmsrcgpcmix.src_system_rstsjc.sjc_gpucr1_reg[30]
sjc.sjc_gpucr3_reg[14]
sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]
sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]sjc.sjc_gpucr1_reg[11]
Alt7 Special EN
TEST_MODEBOOT_MODE0BOOT_MODE1JTAG_MODJTAG_TRST_BJTAG_TDIJTAG_TMSJTAG_TCKJTAG_TDORTCPMIC_STBY_REQPMIC_ON_REQONOFFPOR_BRTC_RESET_BGPIO1_IO00GPIO1_IO01GPIO1_IO02GPIO1_IO03GPIO1_IO04GPIO1_IO05GPIO1_IO06GPIO1_IO07GPIO1_IO08GPIO1_IO09GPIO1_IO10GPIO1_IO11GPIO1_IO12GPIO1_IO13GPIO1_IO14GPIO1_IO15ENET_MDCENET_MDIOENET_TD3ENET_TD2ENET_TD1ENET_TD0ENET_TX_CTLENET_TXCENET_RX_CTLENET_RXCENET_RD0ENET_RD1ENET_RD2ENET_RD3SD1_CLKSD1_CMDSD1_DATA0SD1_DATA1SD1_DATA2SD1_DATA3SD1_DATA4SD1_DATA5SD1_DATA6SD1_DATA7SD1_RESET_BSD1_STROBESD2_CD_BSD2_CLKSD2_CMDSD2_DATA0SD2_DATA1SD2_DATA2SD2_DATA3SD2_RESET_BSD2_WPNAND_ALENAND_CE0_BNAND_CE1_BNAND_CE2_BNAND_CE3_BNAND_CLENAND_DATA00NAND_DATA01NAND_DATA02NAND_DATA03NAND_DATA04NAND_DATA05NAND_DATA06NAND_DATA07NAND_DQSNAND_RE_BNAND_READY_BNAND_WE_BNAND_WP_BSAI5_RXFSSAI5_RXCSAI5_RXD0SAI5_RXD1SAI5_RXD2SAI5_RXD3SAI5_MCLKSAI1_RXFSSAI1_RXCSAI1_RXD0SAI1_RXD1SAI1_RXD2SAI1_RXD3SAI1_RXD4SAI1_RXD5SAI1_RXD6SAI1_RXD7SAI1_TXFSSAI1_TXCSAI1_TXD0SAI1_TXD1SAI1_TXD2SAI1_TXD3SAI1_TXD4SAI1_TXD5SAI1_TXD6SAI1_TXD7SAI1_MCLKSAI2_RXFSSAI2_RXCSAI2_RXD0SAI2_TXFSSAI2_TXCSAI2_TXD0SAI2_MCLKSAI3_RXFSSAI3_RXCSAI3_RXDSAI3_TXFSSAI3_TXCSAI3_TXDSAI3_MCLKSPDIF_TXSPDIF_RXSPDIF_EXT_CLKECSPI1_SCLKECSPI1_MOSIECSPI1_MISOECSPI1_SS0ECSPI2_SCLKECSPI2_MOSIECSPI2_MISOECSPI2_SS0I2C1_SCLI2C1_SDAI2C2_SCLI2C2_SDAI2C3_SCLI2C3_SDAI2C4_SCLI2C4_SDAUART1_RXDUART1_TXDUART2_RXDUART2_TXDUART3_RXDUART3_TXDUART4_RXDUART4_TXD
tcu.TEST_MODEccmsrcgpcmix.BOOT_MODE[0]ccmsrcgpcmix.BOOT_MODE[1]cjtag_wrapper.MODcjtag_wrapper.TRST_Bcjtag_wrapper.TDIcjtag_wrapper.TMScjtag_wrapper.TCKcjtag_wrapper.TDOsnvsmix.RTCccmsrcgpcmix.PMIC_STBY_REQsnvsmix.PMIC_ON_REQsnvsmix.ONOFFsnvsmix.POR_Bsnvsmix.RTC_POR_Bgpio1.IO[0]gpio1.IO[1]gpio1.IO[2]gpio1.IO[3]gpio1.IO[4]gpio1.IO[5]gpio1.IO[6]gpio1.IO[7]gpio1.IO[8]gpio1.IO[9]gpio1.IO[10]gpio1.IO[11]gpio1.IO[12]gpio1.IO[13]gpio1.IO[14]gpio1.IO[15]gpio1.IO[16]gpio1.IO[17]gpio1.IO[18]gpio1.IO[19]gpio1.IO[20]gpio1.IO[21]gpio1.IO[22]gpio1.IO[23]gpio1.IO[24]gpio1.IO[25]gpio1.IO[26]gpio1.IO[27]gpio1.IO[28]gpio1.IO[29]gpio2.IO[0]gpio2.IO[1]gpio2.IO[2]gpio2.IO[3]gpio2.IO[4]gpio2.IO[5]gpio2.IO[6]gpio2.IO[7]gpio2.IO[8]gpio2.IO[9]gpio2.IO[10]gpio2.IO[11]gpio2.IO[12]gpio2.IO[13]gpio2.IO[14]gpio2.IO[15]gpio2.IO[16]gpio2.IO[17]gpio2.IO[18]gpio2.IO[19]gpio2.IO[20]gpio3.IO[0]gpio3.IO[1]gpio3.IO[2]gpio3.IO[3]gpio3.IO[4]gpio3.IO[5]gpio3.IO[6]gpio3.IO[7]gpio3.IO[8]gpio3.IO[9]gpio3.IO[10]gpio3.IO[11]gpio3.IO[12]gpio3.IO[13]gpio3.IO[14]gpio3.IO[15]gpio3.IO[16]gpio3.IO[17]gpio3.IO[18]gpio3.IO[19]gpio3.IO[20]gpio3.IO[21]gpio3.IO[22]gpio3.IO[23]gpio3.IO[24]gpio3.IO[25]gpio4.IO[0]gpio4.IO[1]gpio4.IO[2]gpio4.IO[3]gpio4.IO[4]gpio4.IO[5]gpio4.IO[6]gpio4.IO[7]gpio4.IO[8]gpio4.IO[9]gpio4.IO[10]gpio4.IO[11]gpio4.IO[12]gpio4.IO[13]gpio4.IO[14]gpio4.IO[15]gpio4.IO[16]gpio4.IO[17]gpio4.IO[18]gpio4.IO[19]gpio4.IO[20]gpio4.IO[21]gpio4.IO[22]gpio4.IO[23]gpio4.IO[24]gpio4.IO[25]gpio4.IO[26]gpio4.IO[27]gpio4.IO[28]gpio4.IO[29]gpio4.IO[30]gpio4.IO[31]gpio5.IO[0]gpio5.IO[1]gpio5.IO[2]gpio5.IO[3]gpio5.IO[4]gpio5.IO[5]gpio5.IO[6]gpio5.IO[7]gpio5.IO[8]gpio5.IO[9]gpio5.IO[10]gpio5.IO[11]gpio5.IO[12]gpio5.IO[13]gpio5.IO[14]gpio5.IO[15]gpio5.IO[16]gpio5.IO[17]gpio5.IO[18]gpio5.IO[19]gpio5.IO[20]gpio5.IO[21]gpio5.IO[22]gpio5.IO[23]gpio5.IO[24]gpio5.IO[25]gpio5.IO[26]gpio5.IO[27]gpio5.IO[28]gpio5.IO[29]
tcu.TEST_MODEccmsrcgpcmix.BOOT_MODE[0]ccmsrcgpcmix.BOOT_MODE[1]cjtag_wrapper.MODEcjtag_wrapper.TRST_Bcjtag_wrapper.TDIcjtag_wrapper.TMScjtag_wrapper.TCKcjtag_wrapper.TDOsnvsmix.RTCccmsrcgpcmix.PMIC_STBY_REQsnvsmix.PMIC_ON_REQsnvsmix.ONOFFsnvsmix.POR_Bsnvsmix.RTC_RESET_Bgpio1.IO[0]gpio1.IO[1]gpio1.IO[2]gpio1.IO[3]gpio1.IO[4]gpio1.IO[5]gpio1.IO[6]gpio1.IO[7]gpio1.IO[8]gpio1.IO[9]gpio1.IO[10]gpio1.IO[11]gpio1.IO[12]gpio1.IO[13]gpio1.IO[14]gpio1.IO[15]enet1.MDCenet1.MDIOenet1.RGMII_TD3enet1.RGMII_TD2enet1.RGMII_TD1enet1.RGMII_TD0enet1.RGMII_TX_CTLenet1.RGMII_TXCenet1.RGMII_RX_CTLenet1.RGMII_RXCenet1.RGMII_RD0enet1.RGMII_RD1enet1.RGMII_RD2enet1.RGMII_RD3usdhc1.CLKusdhc1.CMDusdhc1.DATA0usdhc1.DATA1usdhc1.DATA2usdhc1.DATA3usdhc1.DATA4usdhc1.DATA5usdhc1.DATA6usdhc1.DATA7usdhc1.RESET_Busdhc1.STROBEusdhc2.CD_Busdhc2.CLKusdhc2.CMDusdhc2.DATA0usdhc2.DATA1usdhc2.DATA2usdhc2.DATA3usdhc2.RESET_Busdhc2.WPrawnand.ALErawnand.CE0_Brawnand.CE1_Brawnand.CE2_Brawnand.CE3_Brawnand.CLErawnand.DATA00rawnand.DATA01rawnand.DATA02rawnand.DATA03rawnand.DATA04rawnand.DATA05rawnand.DATA06rawnand.DATA07rawnand.DQSrawnand.RE_Brawnand.READY_Brawnand.WE_Brawnand.WP_Bsai5.RX_SYNCsai5.RX_BCLKsai5.RX_DATA[0]sai5.RX_DATA[1]sai5.RX_DATA[2]sai5.RX_DATA[3]sai5.MCLKsai1.RX_SYNCsai1.RX_BCLKsai1.RX_DATA[0]sai1.RX_DATA[1]sai1.RX_DATA[2]sai1.RX_DATA[3]sai1.RX_DATA[4]sai1.RX_DATA[5]sai1.RX_DATA[6]sai1.RX_DATA[7]sai1.TX_SYNCsai1.TX_BCLKsai1.TX_DATA[0]sai1.TX_DATA[1]sai1.TX_DATA[2]sai1.TX_DATA[3]sai1.TX_DATA[4]sai1.TX_DATA[5]sai1.TX_DATA[6]sai1.TX_DATA[7]sai1.MCLKsai2.RX_SYNCsai2.RX_BCLKsai2.RX_DATA[0]sai2.TX_SYNCsai2.TX_BCLKsai2.TX_DATA[0]sai2.MCLKsai3.RX_SYNCsai3.RX_BCLKsai3.RX_DATA[0]sai3.TX_SYNCsai3.TX_BCLKsai3.TX_DATA[0]sai3.MCLKspdif1.OUTspdif1.INspdif1.EXT_CLKecspi1.SCLKecspi1.MOSIecspi1.MISOecspi1.SS0ecspi2.SCLKecspi2.MOSIecspi2.MISOecspi2.SS0i2c1.SCLi2c1.SDAi2c2.SCLi2c2.SDAi2c3.SCLi2c3.SDAi2c4.SCLi2c4.SDAuart1.RXuart1.TXuart2.RXuart2.TXuart3.RXuart3.TXuart4.RXuart4.TX
ccmsrcgpcmix.ENET_PHY_REF_CLK_ROOTpwm1.OUTwdog1.WDOG_Busdhc1.VSELECTusdhc2.VSELECTm4.NMIenet1.MDCenet1.MDIOenet1.1588_EVENT0_INenet1.1588_EVENT0_OUTusb1.OTG_IDusb2.OTG_IDusb1.OTG_PWRusb1.OTG_OCusb2.OTG_PWRusb2.OTG_OC
"INPUT=enet1.TX_CLKOUTPUT=ccmsrcgpcmix.ENET_REF_CLK_ROOT"
enet1.TX_ER
enet1.RX_ER
qspi.A_SCLKqspi.A_SS0_Bqspi.A_SS1_Bqspi.B_SS0_Bqspi.B_SS1_Bqspi.B_SCLKqspi.A_DATA[0]qspi.A_DATA[1]qspi.A_DATA[2]qspi.A_DATA[3]qspi.B_DATA[0]qspi.B_DATA[1]qspi.B_DATA[2]qspi.B_DATA[3]qspi.A_DQSqspi.B_DQS
sai1.TX_DATA[0]sai1.TX_DATA[1]sai1.TX_DATA[2]sai1.TX_DATA[3]sai1.TX_DATA[4]sai1.TX_DATA[5]sai1.TX_BCLKsai5.RX_SYNCsai5.RX_BCLKsai5.RX_DATA[0]sai5.RX_DATA[1]sai5.RX_DATA[2]sai5.RX_DATA[3]sai6.TX_BCLKsai6.TX_DATA[0]sai6.TX_SYNCsai6.MCLKsai5.TX_SYNCsai5.TX_BCLKsai5.TX_DATA[0]sai5.TX_DATA[1]sai5.TX_DATA[2]sai5.TX_DATA[3]sai6.RX_BCLKsai6.RX_DATA[0]sai6.RX_SYNCsai6.MCLKsai5.MCLKsai5.TX_SYNCsai5.TX_BCLKsai5.TX_DATA[0]sai5.TX_DATA[1]sai5.TX_DATA[2]sai5.TX_DATA[3]sai5.MCLKgpt1.CAPTURE1gpt1.CAPTURE2gpt1.COMPARE1gpt1.CLKgpt1.COMPARE2gpt1.COMPARE3pwm4.OUTpwm3.OUTpwm2.OUTpwm1.OUTuart3.RXuart3.TXuart3.CTS_Buart3.RTS_Buart4.RXuart4.TXuart4.CTS_Buart4.RTS_Benet1.MDCenet1.MDIOenet1.1588_EVENT1_INenet1.1588_EVENT1_OUTpwm4.OUTpwm3.OUTpwm2.OUTpwm1.OUTecspi3.SCLKecspi3.MOSIecspi3.MISOecspi3.SS0uart1.CTS_Buart1.RTS_Buart2.CTS_Buart2.RTS_B
sai1.TX_SYNCsai1.TX_SYNCsai1.TX_SYNCsai4.MCLK
sai6.RX_BCLKsai6.RX_DATA[0]sai6.RX_SYNCsai1.TX_SYNC
sai6.TX_BCLKsai6.TX_DATA[0]sai6.TX_SYNC
sai1.TX_BCLK
sai5.RX_SYNCsai5.RX_BCLKsai5.RX_DATA[0]sai5.RX_DATA[1]sai5.RX_DATA[2]sai5.RX_DATA[3]sai5.MCLK
gpt2.CLKgpt3.CLKpcie1.CLKREQ_Bpcie2.CLKREQ_B
pcie1.CLKREQ_Bpcie2.CLKREQ_B
sai5.TX_SYNCsai5.TX_BCLKsai5.TX_DATA[0]
sai1.RX_SYNC
sai1.TX_DATA[4]
coresight.TRACE_CLKcoresight.TRACE_CTLcoresight.TRACE[0]coresight.TRACE[1]coresight.TRACE[2]coresight.TRACE[3]coresight.TRACE[4]coresight.TRACE[5]coresight.TRACE[6]coresight.TRACE[7]coresight.EVENTOcoresight.EVENTIcoresight.TRACE[8]coresight.TRACE[9]coresight.TRACE[10]coresight.TRACE[11]coresight.TRACE[12]coresight.TRACE[13]coresight.TRACE[14]coresight.TRACE[15]
anamix.REF_CLK_32Kanamix.REF_CLK_24Mwdog1.WDOG_ANYsdma1.EXT_EVENT[0]sdma1.EXT_EVENT[1]ccmsrcgpcmix.PMIC_READYusdhc1.CD_Busdhc1.WPusdhc2.RESET_Bsdma2.EXT_EVENT[0]
ccmsrcgpcmix.PMIC_READYsdma2.EXT_EVENT[1]pwm2.OUTpwm3.OUTpwm4.OUTgpio1.IO[16]gpio1.IO[17]gpio1.IO[18]gpio1.IO[19]gpio1.IO[20]gpio1.IO[21]gpio1.IO[22]gpio1.IO[23]gpio1.IO[24]gpio1.IO[25]gpio1.IO[26]gpio1.IO[27]gpio1.IO[28]gpio1.IO[29]gpio2.IO[0]gpio2.IO[1]gpio2.IO[2]gpio2.IO[3]gpio2.IO[4]gpio2.IO[5]gpio2.IO[6]gpio2.IO[7]gpio2.IO[8]gpio2.IO[9]gpio2.IO[10]gpio2.IO[11]gpio2.IO[12]gpio2.IO[13]gpio2.IO[14]gpio2.IO[15]gpio2.IO[16]gpio2.IO[17]gpio2.IO[18]gpio2.IO[19]gpio2.IO[20]gpio3.IO[0]gpio3.IO[1]gpio3.IO[2]gpio3.IO[3]gpio3.IO[4]gpio3.IO[5]gpio3.IO[6]gpio3.IO[7]gpio3.IO[8]gpio3.IO[9]gpio3.IO[10]gpio3.IO[11]gpio3.IO[12]gpio3.IO[13]gpio3.IO[14]gpio3.IO[15]gpio3.IO[16]gpio3.IO[17]gpio3.IO[18]gpio3.IO[19]gpio3.IO[20]gpio3.IO[21]gpio3.IO[22]gpio3.IO[23]gpio3.IO[24]gpio3.IO[25]gpio4.IO[0]gpio4.IO[1]gpio4.IO[2]gpio4.IO[3]gpio4.IO[4]gpio4.IO[5]gpio4.IO[6]gpio4.IO[7]gpio4.IO[8]gpio4.IO[9]gpio4.IO[10]gpio4.IO[11]gpio4.IO[12]gpio4.IO[13]gpio4.IO[14]gpio4.IO[15]gpio4.IO[16]gpio4.IO[17]gpio4.IO[18]gpio4.IO[19]gpio4.IO[20]gpio4.IO[21]gpio4.IO[22]gpio4.IO[23]gpio4.IO[24]gpio4.IO[25]gpio4.IO[26]gpio4.IO[27]gpio4.IO[28]gpio4.IO[29]gpio4.IO[30]gpio4.IO[31]gpio5.IO[0]gpio5.IO[1]gpio5.IO[2]gpio5.IO[3]gpio5.IO[4]gpio5.IO[5]gpio5.IO[6]gpio5.IO[7]gpio5.IO[8]gpio5.IO[9]gpio5.IO[10]gpio5.IO[11]gpio5.IO[12]gpio5.IO[13]gpio5.IO[14]gpio5.IO[15]gpio5.IO[16]gpio5.IO[17]gpio5.IO[18]gpio5.IO[19]gpio5.IO[20]gpio5.IO[21]gpio5.IO[22]gpio5.IO[23]gpio5.IO[24]gpio5.IO[25]gpio5.IO[26]gpio5.IO[27]gpio5.IO[28]gpio5.IO[29]
ccmsrcgpcmix.EXT_CLK1ccmsrcgpcmix.EXT_CLK2
anamix.xtal_okanamix.xtal_ok_lvccmsrcgpcmix.INT_BOOTccmsrcgpcmix.EXT_CLK3ccmsrcgpcmix.EXT_CLK4ccmsrcgpcmix.WAITccmsrcgpcmix.STOP
ccmsrcgpcmix.OUT0ccmsrcgpcmix.OUT1ccmsrcgpcmix.OUT2ccmsrcgpcmix.CLKO1ccmsrcgpcmix.CLKO2
ccmsrcgpcmix.OBSERVE0ccmsrcgpcmix.OBSERVE1ccmsrcgpcmix.OBSERVE2ccmsrcgpcmix.WAITccmsrcgpcmix.STOPccmsrcgpcmix.EARLY_RESETccmsrcgpcmix.SYSTEM_RESET
ccmsrcgpcmix.TESTER_ACK
ccmsrcgpcmix.BOOT_CFG[0]ccmsrcgpcmix.BOOT_CFG[1]ccmsrcgpcmix.BOOT_CFG[2]ccmsrcgpcmix.BOOT_CFG[3]ccmsrcgpcmix.BOOT_CFG[4]ccmsrcgpcmix.BOOT_CFG[5]ccmsrcgpcmix.BOOT_CFG[6]ccmsrcgpcmix.BOOT_CFG[7]
ccmsrcgpcmix.BOOT_CFG[8]ccmsrcgpcmix.BOOT_CFG[9]ccmsrcgpcmix.BOOT_CFG[10]ccmsrcgpcmix.BOOT_CFG[11]ccmsrcgpcmix.BOOT_CFG[12]ccmsrcgpcmix.BOOT_CFG[13]ccmsrcgpcmix.BOOT_CFG[14]ccmsrcgpcmix.BOOT_CFG[15]
sjc.FAILsjc.ACTIVEsjc.DE_Bsjc.DONEusdhc1.TEST_TRIGusdhc2.TEST_TRIGecspi1.TEST_TRIGecspi2.TEST_TRIGqspi.TEST_TRIGrawnand.TEST_TRIGocotp_ctrl_wrapper.FUSE_LATCHEDcaam_wrapper.RNG_OSC_OBScsu.CSU_ALARM_AUT[0]csu.CSU_ALARM_AUT[1]csu.CSU_ALARM_AUT[2]csu.CSU_INT_DEB
observe_mux.OUT[0]observe_mux.OUT[1]observe_mux.OUT[2]observe_mux.OUT[3]observe_mux.OUT[4]
sim_m.HMASTLOCKsim_m.HPROT[0]sim_m.HPROT[1]sim_m.HPROT[2]sim_m.HPROT[3]sim_m.HADDR[0]sim_m.HADDR[1]sim_m.HADDR[2]sim_m.HADDR[3]sim_m.HADDR[4]sim_m.HADDR[5]sim_m.HADDR[6]sim_m.HADDR[7]sim_m.HADDR[8]sim_m.HADDR[9]sim_m.HADDR[10]sim_m.HADDR[11]sim_m.HADDR[12]sim_m.HADDR[13]sim_m.HADDR[14]
sim_m.HADDR[15]sim_m.HADDR[16]sim_m.HADDR[17]sim_m.HADDR[18]sim_m.HADDR[19]sim_m.HADDR[20]sim_m.HADDR[21]sim_m.HADDR[22]sim_m.HADDR[23]sim_m.HADDR[24]sim_m.HADDR[25]sim_m.HADDR[26]sim_m.HADDR[27]sim_m.HADDR[28]sim_m.HADDR[29]sim_m.HADDR[30]sim_m.HADDR[31]sim_m.HBURST[0]sim_m.HBURST[1]sim_m.HBURST[2]sim_m.HRESPsim_m.HSIZE[0]sim_m.HSIZE[1]sim_m.HSIZE[2]sim_m.HWRITEsim_m.HREADYOUTtpsmp.CLKtpsmp.HDATA_DIRtpsmp.HTRANS[0]tpsmp.HTRANS[1]tpsmp.HDATA[0]tpsmp.HDATA[1]tpsmp.HDATA[2]tpsmp.HDATA[3]tpsmp.HDATA[4]tpsmp.HDATA[5]tpsmp.HDATA[6]tpsmp.HDATA[7]tpsmp.HDATA[8]tpsmp.HDATA[9]tpsmp.HDATA[10]tpsmp.HDATA[11]tpsmp.HDATA[12]tpsmp.HDATA[13]tpsmp.HDATA[14]tpsmp.HDATA[15]tpsmp.HDATA[16]tpsmp.HDATA[17]tpsmp.HDATA[18]tpsmp.HDATA[19]tpsmp.HDATA[20]tpsmp.HDATA[21]tpsmp.HDATA[22]tpsmp.HDATA[23]tpsmp.HDATA[24]tpsmp.HDATA[25]tpsmp.HDATA[26]tpsmp.HDATA[27]tpsmp.HDATA[28]tpsmp.HDATA[29]tpsmp.HDATA[30]tpsmp.HDATA[31]
Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7Alt6 Special EN
NAME
ccmsrcgpcmix.src_system_rst
sjc.sjc_gpucr3_reg[14]sjc.sjc_gpucr3_reg[14]
~ccmsrcgpcmix.src_en_system_clk
ccmsrcgpcmix.src_system_rstccmsrcgpcmix.src_system_rstccmsrcgpcmix.src_system_rstccmsrcgpcmix.src_system_rstccmsrcgpcmix.src_system_rstccmsrcgpcmix.src_system_rstccmsrcgpcmix.src_system_rstccmsrcgpcmix.src_system_rst
ccmsrcgpcmix.src_system_rstccmsrcgpcmix.src_system_rstccmsrcgpcmix.src_system_rstccmsrcgpcmix.src_system_rstccmsrcgpcmix.src_system_rstccmsrcgpcmix.src_system_rstccmsrcgpcmix.src_system_rstccmsrcgpcmix.src_system_rst
i.MX8M IOMUX
PIN LIST 2.0Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
Custom
Monday, September 25, 2017
IOMUX
<JW>
<Approver>
<JW>
23 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
Custom
Monday, September 25, 2017
IOMUX
<JW>
<Approver>
<JW>
23 23
____X____Drawing Title:
Size Document Number Rev
Date: Sheet of
Page Title:
Designer:
Drawn by:
Approved:
Microcontroller Product Group6501 William Cannon Drive WestAustin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH-29615 PDF: SPF-29615 B1
mScale850 EVK
Custom
Monday, September 25, 2017
IOMUX
<JW>
<Approver>
<JW>
23 23
____X____
