T4 Sequential systems - UAH
Transcript of T4 Sequential systems - UAH
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Departamento de AutomáticaUniversidad de Alcalá
Fundamentals of Computer Technology
Contents
�Basic Concepts
� Latches and flip-flops
�Registers
�Counters
Unit 4. Sequential Systems
Bibliography
• Digital fundamentals.Thomas Floyd. Prentice-Hall.
• Digital Design.M. Morris Mano. Prentice-Hall
� Introduction to Digital Logic Design.John P. Hayes. Addison-Wesley
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Departamento de AutomáticaUniversidad de Alcalá2
Fundamentals of Computer Technology
Basic concepts
Sequential circuit. Circuit in which the outputs in a concrete instant are function of the inputs in that instant and the state of the circuit, i.e., they store information
� Therefore a sequential system is formed by two different blocks: a combinational system to process information and a memory system to store it.
Generally, feedback circuits are present in sequential systems.
Sistema dememoria
(biestables)
Sistemacombinacional
ENTRADAS SALIDAS
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Fundamentals of Computer Technology
Latches and flip -flops (I)
� Information is stored in binary, and the basic memory elements are latches and flip-flops which store just one bit of information.
� They are elementary logical circuits that can remain in one of the two possible states (Q=0 or Q=1) and switch among them depending on the triggering inputs.
� There are many types, but the general scheme is:
EstadoQ
Entradasde disparo Salidas
Q
Q
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Classification:Depending on triggering method:
R-S J-K D T
Depending on triggering synchronization:� Synchronous. Switching among states occurs in synchrony with a
clock signal� Asynchronous. Switching among states can occurs in any moment; it
just depend on the triggering inputs.
Depending on the form of the triggering signal:� Level-triggered. Triggering and change of state occurs when a low or
high level is detected in the inputs.
� Edge-triggered (synchronous flip-flops): Triggering and change of state occurs just when the clock changes from low to high (rising edge) or from high to low (falling edge).
Latches and flip-flops (I)Latches and flip -flops (II)
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R-S NOR
Tabla de excitación
Rt St Qt+1
0 0 Qt 0 1 1 1 0 0 1 1 I
R=S=1: Q is not determined. Not valid input
R
S Q
Q
R
SQ
Q
Latches and flip-flops (I)Latches and flip -flops (III)
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RS-NAND
R=S=0: Q is not determined. Not valid input
Tabla de excitación
Rt St Qt+1
0 0 I 0 1 0 1 0 1 1 1 Qt
S
Q
Q
R
S
R Q
Q
Latches and flip-flops (I)Latches and flip -flops (IV)
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R-S synchronous
� Level-triggered
S
R Q
QS
R
Clk
Q
Q S
R Q
Q
Q
Q
Clk
S
R Q
QS
R
Clk
Q
Q S
R Q
Q
Q
Q
Clk
Latches and flip-flops (I)Latches and flip -flops (V)
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R-S synchronous with asynchronous inputs CL and PR
Tabla de excitaciónPr Cl S R Clk Qt+1
0 1 X X X 11 0 X X X 00 0 X X X X1 1 0 0 Qt
1 1 1 0 11 1 0 1 01 1 1 1 X
S
R Q
Q
Q
Q
Clk
CL
PR
Latches and flip-flops (I)Latches and flip -flops (VI)
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R-S Master-Slave
It solves timing problems that can give rise to wrong outputs by reducing the switching moment of the flip-flop to transitions of the clock (rising or falling edges)
� Example: falling edge
S
R Q
QS
R
Clk
S
R Q
Q
Q
Q
MAESTRO
Clk'
ESCLAVO
S
R Q
Q
Q
Q
> Clk
S
R
Latches and flip-flops (I)Latches and flip -flops (VII)
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Asynchronous J-K Flip-flop
Like R-S, but removing undetermined situations using feedback
J ~ S y K ~ R.
J
K Q
Q
Q
Q
S
R Q
Q
Q
QJ
K Q
Q
J
K
Tabla de excitación
Jt Kt Qt+1
0 0 Qt
0 1 0
1 0 1
1 1 tQ
Latches and flip-flops (I)Latches and flip -flops (VIII)
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Synchronous J-K Flip-flop
� Level-triggered
� Edge-triggered
Q
Q
J
K
Clk
J
K Q
Q
Q
Q
Clk
S
R Q
QJ
K
Clk
S
R Q
Q
Q
Q
MAESTRO
Clk'
ESCLAVOJ
K Q
Q
Q
Q
> Clk
J
K
Latches and flip-flops (I)Latches and flip -flops (IX)
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T flip-flop
J
K Q
Q
Q
Q
> Clk
T
Clk
Tabla de excitación
Tt Clk Qt+1
0 Qt
1 tQ
T
Q
Q
Q
Q
> Clk
Latches and flip-flops (I)Latches and flip -flops (X)
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� D latch (level-triggered)
D
Q
Q
Q
Q
Clk
S
R Q
Q
Q
Q
Clk
D
Clk
Tabla de excitación
Dt Clk Qt+1
X 0 Qt
D 1 D
� D flip-flop (edge-triggered)
D
Q
Q
Q
Q
> Clk
S
R Q
Q
Q
QD
Clk> Clk
Tabla de excitación
Dt Clk Qt+1
D D
Latches and flip-flops (I)Latches and flip -flops (XI)
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Registers (I)
Register : Circuit that can store binary information, generally a word
(n bits: 4, 8, 16, 32, 64…).
It is formed by flip-flops connected by different ways depending on the type:
Basic types:
� Storing registers
� Shift registers
� Counters
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Fundamentals of Computer Technology
Storing Register: it works like a small memory; just stores bits. Operations: read and write
Depending on the triggering: LatchesFlip-flops
D Q
> CLK
CLR
D Q
> CLK
CLR
D Q
> CLK
CLR
D Q
> CLK
CLR
CLK
CLR
E3
E2
E1
E0
S3
S2
S1
S0
MSB ............................................ LSB
Registers (II)
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Shift register. Besides storing information, it can shift it by moving bits
between connected flip-flops or latches
Types (depending on input-output)
� Serial Input - Serial Output
� Serial Input - Parallel output
� Parallel Input - Serial Output
� Parallel Input - Parallel output
Registers (III)
ENTRADADE DATOS
SERIE
SALIDADE DATOS
SERIE
S/Sn bits
ENTRADADE DATOS
SERIE
S/Pn bits
SALIDADE DATOSPARALELO
SALIDADE DATOS
SERIE
ENTRADADE DATOSPARALELO
P/Sn bits
SALIDADE DATOSPARALELO
ENTRADADE DATOSPARALELO
P/Pn bits
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Types (depending on shifting):
� Open
� Right shift
� Left shift
� Ring
� Right shift
� Left shift
Registers (IV)
E S
ES
SE
ES
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Shift register with serial input – serial output
Registers (V)
CLK
E
S
CLR
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D Q
> CLK
D Q D Q D Q
CLK
E S
CLR CLR CLR CLR
CLR
> CLK > CLK > CLK
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Registers (VI)
Shift register with serial input – parallel output
CLK
CLR
E
1 2 3 4 5 6 7 8 9 10 11 12 13 14
S0
S1
S2
S3
D Q
> CLK
D Q D Q D Q
CLK
E
CLR CLR CLR CLR
CLR
S0
S1
S2
S3
ENTRADA SERIE
SALIDA PARALELO
> CLK > CLK > CLK
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Shift register with parallel input – serial output
Registers (VII)
D
Q
Q
> CLK
CLR
PRS
E0
D
Q
Q
E1
D
Q
Q
E2
D
Q
Q
E3
CLK
SALIDA SERIE
Control (S/L)
CLR
PRS PRS
CLR CLR
PRS
ENTRADA PARALELO
> CLK > CLK > CLK
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Shift register with parallel input - parallel output
Registers (VIII)
D
Q
Q
> CLK
ENTRADASERIE
D
Q
Q
E0CONTROL
CLK
D
Q
Q D
Q
Q
E1 E2 E3
S0 S1 S2 S3
> CLK > CLK > CLK
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Universal shift register
Registers (IX)
C1 C0 Operation
0 0
0 1 Right shift
1 0
1 1 Load
D Q
> CLK
CLR
D Q
> CLK
CLR
D Q
> CLK
CLR
D Q
> CLK
CLR
A B C D
C1
C0
SRI
CLK
CLR
SLI
QA QB QC QD
Keeps the state. No op
Left shift
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� Circuit that “counts” and “remembers” the number of pulses it receives from an external signal or clock
� It is formed by a chain of flip-flops whose n outputs represent the count in binary
� Classifications:
� Synchronism:
� Asynchronous / synchronous
� Counting way:
� Up / Down
� Maximum count:
� Binary / N-modulus
Counters (I)
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Counters (II)
Asynchronous up binary counter
J
Q
Q
> CLK
K
CLK
'1'CLR
J
Q
Q
> CLK
K'1'
CLR
QA
J
Q
Q
K'1'
CLR
QB
J
Q
Q
K'1'
CLR
QC QD
CLR
> CLK > CLK
Q A
CLK
Q B
Q C
Q D
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
f
f/2
f/4
f/8
f/16
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001
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Counters (III)
Asynchronous down binary counter
Q A
CLK
Q B
Q C
Q D
123456789101112131415 0 15
f
f/2
f/4
f/8
f/16
0000 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 1111
0
J
Q
Q
> CLK
K
CLK
CLR
J
Q
Q
> CLK
K
'1'
CLR
Q A
J
Q
Q
K CLR
QB
J
Q
Q
K CLR
QC QD
CLR
> CLK > CLK
'1' '1' '1'
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Synchronous up binary counter
Counters (IV)
J
Q
Q
K
CLK
'1'
CLR
J
Q
Q
K
QA
J
Q
Q
K
J
Q
Q
K
QC QDQB
> CLK > CLK
CLR
> CLK
CLR
> CLK
CLR
CLR
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10-modulus counter N (Up, Asynchronous)
Counters (V)
J
Q
Q
> CLK
K
CLK
'1'CLR
J
Q
Q
> CLK
K'1'CLR
QA
J
Q
Q
K'1'CLR
QB
J
Q
Q
K'1'CLR
QC QD
> CLK > CLK
QD QC QB QA 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1
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