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www.ict.tuwien.ac.at Institute of Computer Technology /99 Example-driven Interconnect Synthesis for Heterogeneous Coarse-Grain Reconfigurable Logic Clifford Wolf, Johann Glaser , Florian Schupfer, Jan Haase, Christoph Grimm
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Example-driven Interconnect Synthesis for Heterogeneous Coarse-Grain
Reconfigurable Logic
Clifford Wolf, Johann Glaser,Florian Schupfer, Jan Haase, Christoph Grimm
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Overview
Ultra-Low-Power Electronics Reconfigurable Modules
• Structure
• TR-FSM
• Design of Reconfigurable Modules
Interconnect Generation• Interconnect Topology
• Optimization Algorithm
• Evaluation Results
Full Design Flow Summary
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Ultra-Low-Power Electronics
Application: WSN Node in a SoC CPU as Master Sleep, Wakeup Offload-Engines Multiple Modules Reconfigurable
• Various Applications
• Adapt to Environment
WSN Node
SoC
CPU RF
GPIOMem
RTC ADC
Sens
or
Power Mgmt.
SoC
WSN Node
Power Mgmt.
ADC
GPIO
RF
Mem
CPU
RTC
Sens
or
Inte
rfac
eSe
nsor
Comm.Intf.
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Reconfigurable Logic
Development• Pre-Silicon vs. Post-Silicon
Fine-Grain vs. Coarse-Grain Heterogeneous Domain Specific
• Application Class
Reconfigurable Circuit
Manufacturing
Application 1
Bitstream
Application n
Bitstream
Pre-Silicon
Post-Silicon
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Structure
Interface FSM+D
➔ Control, Data, Arithmetic
Cell Types• FSM
• Memory
• Add, Subtract, |A-B|, ...
Reconfigurable• Routing
• Cells
ResetClk
Intr
Bus
Config
Param
FSM
|A-B| >P
I/O
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Transition-based Reconfigurable FSM
ISM
OPR
NSR
ISM
ISMnT1
nSIn
nTm
nT2
nO
Sel
ect
Next StateSR
Clk
En
En
En
IPG
IPG
IPG
SSG
SSG
SSG
OPR
NSR
OPR
NSR
Inputs State
Outputs
Reconfigurable Cell Focus on Transition Transition Row
• SSG: State Selection Gate
• ISM: Input Switching Matrix
• IPG: Input Pattern Gate
• NSR: Next State Register
VHDL Silicon-proven
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Design
Pre-Silicon Phase Define Application Class Specify Example Applications “Common Denominator” Pre-Silicon limits
Post-Silicon Design Space Future Applications
• Might need more Resources
➔ Oversizing• Additional Cell Instances
• Allow more Connections
Application Class
ReconfigurableLogic
App 1 App 2 App 3
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Connection Topology
Connection Types• e.g. Bit, Byte, Word
Requirements• Random Connections
• Simple Characterization
• Allow Optimization
• Limit Optimization
• Oversizing
• Synthesizable
Tree Topology
Parallel Trees• All Ports in all Trees
• Alternate Position
• Routing in any Tree
C C C C C C C C
Switch Switch Switch
Switch
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InterSynth: Overview
Post-Silicon• Input
− Internal Representation
− Netlist
• Output− Configuration Bitstream
Automatic Interconnect Generation and Optimization
Pre-Silicon• Input
− Example Netlists
− Cell Types
− Connection Types
• Output− Synthesizable RTL Code
− Configuration Bitstreams
− Static Timing Analysis Rules
− LaTeX TikZ Image
− Internal Representation
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InterSynth: Algorithm
Degrees of Freedom• Number of Cells per Type
• Interconnect Resources
• Mapping of Cells in Netlist (“Nodes”) to Physical Cells
• Placement of Physical Cells in Interconnect Tree
Optimization Steps• Optimize Cell Placement
• Node-to-Cell Mapping
• Repeat Until no Further
Improvement
Optimization AlgorithmModified Kernighan-Lin algorithm
Optimization GoalMinimize Interconnect Resources
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Digital Filters Application Class
• Simple Digital Filters
• Cell Types− Adders
− Scalers
− Delays
• Netlists for Pre-Silicon− biquad-df2
− fir4-df1
− fir4-df2
• Extra Netlist for Post-Silicon− biquad-df1
• 2 Parallel Interconnect Trees
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Digital Filters Example
Post-Silicon Netlist: biquad-df1
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Digital Filters Example
Higher Order Filters• Combine two Stages
• 16 different Netlists
• Pre-Silicon: 2-4 Examples enough
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Full Design Flow
Pre-Silicon Phase After InterSynth
• Synthesizable HDL− Instantiate Cells
− Reconfigurable Routing
• SoC Integration
• Synthesis
• Place and Route
• Chip
Input of InterSynth• Example Netlists
• Cell Library P&R
Synthesis
InterSynth
Net-list 1
Net-list 2 Cell
Library
App 1 App 2 App 3
Net-list 3
SoC
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Full Design Flow
Specification• Easy to translate to netlist
• No new type of description
• Verifiable➔ VHDL, Verilog
Special Synthesis• Coarse Grain
• Identify Cells
• FSM Extraction
• Bitstream Generation
P&R
Synthesis
InterSynth
CellLibrary
App 1 App 2 App 3
SoC
Net-list 1
Net-list 2
Net-list 3
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yosys
Yosys Open SYnthesis Suite Extensible RTL Synthesis Verilog (VHDL will follow) Coarse-grain and Fine-grain Focus on easy extensibility
• Preserve HDL Information
• Structure− Frontend
− Multiple Passes
− Backend
Currently under development
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yosys Abstract HDL Constructs RTLIL
• RTL Intermediate Language
• Simple Internal Representation
• Modified by Synthesis Passes
Passes• Transformation of
High-Level Constructs toLow-Level Constructs
• Optimization
• Coarse-Grain Mapping
Verilog HDL Code
Frontend
AST Representation
AST Synthesis
RTLIL Representation
Backend
Output Netlist
Passes
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Full Design Flow
Example Applications Coarse Grain Synthesis Cell Library Verification
• Simulation
• Equivalence Checking
• Wrapper
• Configuration
Pre-Silicon Post-Silicon P&R
Synthesis
InterSynth
Net-list 1
Net-list 2 Cell
Library
App 1 App 2 App 3
Net-list 3
SoC
yosys→ Coarse-Grain Mapping
EC
Sim
Sim
Sim
Sim
Sim
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Summary
Ultra-Low-Power Electronics CPU Offload-Engines Reconfigurable Modules Interconnect Generation Coarse-Grain Synthesis Full Design Flow
Future Work• yosys VHDL Frontend
• More on Coarse-Grain Synthesis
