System in Package and Chip-Package-Board Co-Design
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Transcript of System in Package and Chip-Package-Board Co-Design
The EDA Lab
System in Package and Chip-Package-Board Co-Design
Progress Report
Jia-Wei Fang, Kuan-Hsien Ho, and Yao-Wen Chang
The Electronic Design Automation Laboratory
Graduate Institute of Electronics Engineering
National Taiwan University
August 14, 2008
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Outline
․ System in Package Introduction Problem Formulation Extensions
․ Placement and Routing for Chip-Package-Board Co-Design Considering Differential Pairs
Introduction Problem Formulation Placement and Routing Algorithm Experimental Results Conclusions
․ Schedule
System in Package (SiP)
․ Can get higher deign performance and is easier for implementation than that of Systems on Chip (SoC)
․ Place multiple dies/flip-chips on the same package Stack specific dies Locate fingers around each group of dies
․ Connect nets among dies, flip-chips, and the package
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Die
Bonding wire
Finger
Ball
BGA package
Package wire
StackedDies
Through silicon via
Metal layersFlip-chip
Ball
Pad
SiP Problem Formulation
․ Problem: Given dies with pads, flip-chips with balls, a PGA/BGA package
with pins/balls, a netlist containing pre- and free-assignment nets, and design constraints
Place dies, corresponding fingers of dies, and flip-chips on the PGA/BGA package, then assign signals and route wires among dies, flip-chips, and the package
․ Objectives: Maximize routability Minimize total wirelength under the design constraints
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Extensions
․ Package placement to Multiple dies placement
․ Ball arrangement to Finger arrangement
․ Signal assignment for fingers and pins to Signal assignment for pads and pins Pre-assignment and free-assignment signal routing
․ Differential-pair routing to Other routing constraints
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Outline
․ System in Package Introduction Problem Formulation Extensions
․ Placement and Routing for Chip-Package-Board Co-Design Considering Differential Pairs
Introduction Problem Formulation Placement and Routing Algorithm Experimental Results Conclusions
․ Schedule
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Chip-Package-Board Co-Design
DieBonding wireFinger
BGAPinBump ball
PCB
PCB wire
Package wire
Metal layers
Top metal layer
Differential Pairs
․ Differential-Pair (DP) routing is a popular technique for high-speed PCB designs due to its noise immunity, EMI reduction, and ground bounce insensitivity
․ However, the signal pair should be transmitted in close proximity with similar wirelength to simultaneously absorb the noise
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Problem of Chip-Package-Board Co-Design
․ Problem: Given a die with fingers, a placement of components with pins, the
numbers of BGA and PCB metal layers, and a netlist Generate and place the package and then assign signals and route
wires from component pins to fingers via bump balls, considering differential pairs
․ Objectives: Maximize routability Minimize package size, total wirelength, and the number of vias
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Design Flow
Global Routing Detailed Routing
Routing Result Output
No
Yes
Layer Assignment
CPB Placement
Any-Angle RoutingRouting Network Construction
Package and PCB Routing
Bump-Ball Arrangement
Package Placement
Routed & Minimized?
Die (Fingers), Components (Pins)# Layers, Netlist, Design Rules
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Bump-Ball Arrangement
․ Determine package size (can get the minimum rectangle size)
․ # bump balls of (r-1) rings < # fingers < # bump balls of r rings
ring r
ring r-1
Fingers
Bump ball
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Package Placement
․ Apply linear programming (LP) to determine the location of the package
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1
3 4
q
p r
(x1, y1)
(x2, y2)
(xc, yc)
(xp, yp)
xboundary
yboundary
c Package Center
Pin
X=0
y=0
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Global Routing (1/2)
․ Two types of nets Type 1: from a finger to a bump ball Type 2: from a finger to a component via a bump ball
․ Apply LP to do global routing Multi-sources Single sink
f1
f2
f3
b4
b5
b6
b1
b2
b3
BGAPCB ChipPre-assigned signals Only given a netlist
b
a
c
s2
s1
Use s2 to choose only the bump pads for Type 1
t
Netlist: 1, 2, 3
Finger
es1_p1
Ball
Pin
p1
p2
na
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Global Routing (2/2)
․ Two types of nets Type 1: from a finger to a bump ball Type 2: from a finger to a component via a bump ball
․ Apply LP to do global routing Multi-sources Single sink
f1
f2
f3
b4
b5
b6
b1
b2
b3
Pin
p1
p2
BGAPCB Chip
g
h
s2
t
Netlist: 1, 2, 3
s1
Finger
Only given a netlist
․ The signal pair should be transmitted in close proximity and similar wirelength
․ Apply LP to route the differential pairs DP constraints
Σ Σ Ψi_j(ei_g - ej_h) = 0
Σ Σ Ψi_jΨg_h(ei_g - ej_h) = 0
Differential-Pair Routing
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34
34
34
34
s3
s4
DP node
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34
34
34
s3
s4
Bounding box
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Layer Assignment
․ In global routing, integrate all metal layers into one layer
․ Model the layer assignment as a flow network to distribute nets into each layer after global routing
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3
2
1
3
2
BGA Chip
Finger
Ball
1
3
2
l
r
Layer 1
Layer 2
ts
Flow network
es2
es1 elt
ert
e1l
e2r
Can only route 2 wires in one layer
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Detailed Routing (1/2)
․ The PCB routing does not allow any routing path with an acute angle
The router should check every turning point to avoid any acute angle
Once an acute corner is detected, the two adjacent net segments can be cut off to generate two obtuse angles
Acute angle
Turn
Original routing path
Min. spacing ring
: Pins
: Bump balls
Detailed Routing (2/2)
GIEE, NTU 18
Minimum spacing ring
Parallelogram
: DP pins : Pins : Bump balls: DP bump balls
Global Routing Result Detailed Routing Result
Experimental Settings
․ C++ programming language
․ 2.8 GHz AMD Opteron Linux workstation
․ 8 GB memory
․ Benchmark – 5 real industry designs
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Circuits # Components#Pins
(DP/BGA)#Fingers
#Nets
(multi-/2-pin)
#Metal layers
(BGA/PCB)
CPB 1 2 74 (6/59) 150 513 676
CPB 2 1 126 (8/58) 260 646 812
CPB 3 3 192 (16/93) 429 639 1156
CPB 4 3 380 (28/274) 720 657 1156
CPB 5 4 683 (36/460) 1024 1024 1600
Circuits#DP violations
#Integer variables/constraints
CPU times (s)
SAR WG Ours WG Ours SAR WG Ours
CPB1 1/3 0/3 0/3 670/8430 45/135 2 510 6
CPB2 2/4 0/4 0/4 426/4938 35/105 5 456 16
CPB3 5/8 0/8 0/8 1106/13288 83/249 9 9737 34
CPB4 10/14 0/14 0/14 6010/69892 302/906 21 75641 195
CPB5 11/18 N/A 0/18 7968/100831 396/1188 96 3*105 366
Comp. 29/47 N/A 0/47 100%/100% 5%/1%
Experimental Results
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Circuits#Bump balls (L/W) Routability (%) Wirelength (mm)
SAR Ours SAR WG Ours SAR WG Ours
CPB1 208 (17/17) 159 (16/15) 76 100 100 643 1005 997
CPB2 352 (27/25) 275 (25/24) 84 100 100 1614 2033 2040
CPB3 488 (35/34) 453 (35/33) 79 100 100 4924 6789 6780
CPB4 864 (42/42) 740 (41/40) 87 100 100 10028 12263 12248
CPB5 1128 (53/53) 1075 (53/52) 80 N/A 100 21580 N/A 29402
Comp. 100% 89% 81 N/A 100
Conclusions
․ We have developed the first placer and router for chip-package-board design, considering
Package size, Package placement, Differential pair routing, Total wirelength, and Routability optimization
․ Experimental results have shown that our placement and routing algorithm is very effective, robust, and flexible
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Schedule
․ Problem of Chip-Package-Board Co-Design Stage 1 (1/2008 – 4/2008): done
Literature survey Development of a placement and routing algorithm
considering the objectives Stage 2 (5/2008 – 7/2008): done
Implementation of the placement and routing algorithm Stage 3 (8/2008 – 9/2008): done
Optimization of the objectives Stage 4-1 (9/2008 – 11/2008)
GUI generation and integration of all functions Paper writing and documentation
Stage 4-2 (9/2008 – ) Extensions for Etron Designs