System Design and Modeling With Simulink

7/27/2019 System Design and Modeling With Simulink

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System Design & ModelingSystem Design & Modeling

withwith MATlabMATlab // SimulinkSimulink

Project Results and Solutions withinProject Results and Solutions within

Research and EducationResearch and Education

- A VLSI- System - Prototyping Test-bed -Real-time Analysis & Visualization

Dr. Alfred Blaickner

Email: [email protected]

6/8/2002Dr.A.Blaickner, email: [email protected] 2

Overview

System Design Cycle & DSP/FPGA-test-bed

Project & Research Activities

Communication Systems

Signal Processing Systems & EducationMATlab Solutions

VLSI - Emulation / Prototyping-test-bed

Conclusion


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Motivation

System - Design

Necessary due to non-linear behavior of many

subsystems and reduced word-length effects

System design - important step prior to VHDL -

coding, synthesis and VLSI - implementation

System - Design with MATlab

Floating point m odels- most efficient & fastest

solution for early analysis & performance results

Bit- t rue and cycle accu ratemodeling techniques

have been developed for the presented projects


Define concept, a mathematical model, get suitable numeric algorithms

Design of a floating point model at system level

MATlab, System-C, Co-Centric, Cossap, SPW

Map floating point model to a constrained equivalent bit-true and cycle

accurate version - minimize data path processing / shared-architecture

Verify and optimize until functionality full-filled

Map the design manually to a hardware description

language VHDL / HDL (today) ...System-C (future ?)

Synthesize, place and route - HW / SW- Co-design cyclesget test-vectors, back-annotate, optimize and verify

System Design Cycle - Overview


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System - Design Level (ML, SysC)

Idea and concept

Mathematical model

Numerical algorithm

Numerical simulation model;

Bit-true & cycle accurate model

Mapping to architecture - manually

Behavioral- / RTL- Level (HDL, SysC)

Behavioral architecture description

RTL architecture description

E.g: Data bus, MUX, ADD, MUL, REG -

pipeline;

Implementation (Route & Place)

ASIC, FPGA, DSP, Embedded - Systems

System Simulation (ML, Msim, SysC)

Simulation and back annotation to prev.

DS

R

DSPASIC



MATlab based modeling and VHDL-generation

Libraries and toolbox for VHDL/HDL generation

Easy usage for automatic generation of various VHDL/HDL

designs of filters & arithmetic functions (MUL, CORDIC, .. ;)

E.g. half-band filters, arbitrary filter chains

Bit-true and bus accurate

modeling techniques

Most important prior to

architecture mapping

Get first accurate hardware results

Bit - True

Remove zero Values

Matlab Filter

Design Tool

Coefficint Array

ReadCoeffRam.m

RunHalfBandDez.m

MakePackage.m

HB_Filter_Pkg.vhd

- Create Input data vector- Write test patter in data file

- Filter data

- Write result file


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Hardware / Software - Co-design

Device under Test is directly embedded

in design- & test- environment

Shortened design cycles and rapidprototyping

DSP -PC_b o a r d

ALTERA -FPGA1.5 mil. gates)

I/O Interfaces

Testvectors



System Architecture Integration & SynthesisArchitectural mapping and synthesis

T VHDL / C++ / System-C; Cooperation with CAE-Vendors

System ImplementationT Target is currently a modular DSP/FPGA VLSI-emulator - RT-test-bed

HW/SW-co-design and co-verificationT Real-time analysis and control with MATlab / MEXfile- Interface plus

pattern generator / high-speed-digital-IO

T In future with both SystemC and MATlab

Embedded Parallel Processing DSP/FPGAScaleable multi-processing architecture

T Modular DSP(Sharc)- and FPGA(Apex)-based system

C++ based system controlT Real-time test vector and verification environment

T Seamless integration to industry standard compact PCI-bus system


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WidebandRF frontend

WidebandRF frontend

DisplayCTRL

CCD-Interface

SYSTEM CONTROL

cPCI-BusCLK-Ref

JTAG-BusPPORT

Prog./Analyze

BITSI

LVDS

LVDS

ParPort

ParPort

SerPort

SerPort

SerPort

SerPort

ParPort

ParPort

ParPort

ParPort

ParPort

ParPort

BITSI

BITSI

BITSI

DSP-array / QUADsharc 21160FloatPnt-processing / Baseband processing /Adaptivefiltering / Source- / Channel coding /Signal processing

FPGA-arrayInteger- / Channelprocessing /FilteringSignalprocessing /VLSI emulation

A/D - modulesAnalogto digitalconversion

Frontend / BackendUp-/down-conversionSpecific analogelectronics

NT-Workstation-BSystem - DesignVHDL - SynthesisHW/SW-Co-design

NT-Workstation-ASystem - ControlRealtime - TestVisualization

Vector-GenFast-IO

MV-IF (Prog.)MV-Analyzer

JTAG-IF (ICE)

QuadSHARC 21160Fast-ADC (2 Chan)

Fast-DAC (2 Chan)PCI-BUS-Bridge (NI)

PCI-Bus PCI-Bus

PASS Programable ArraySystemSimulator, design by Dr. A. Blaickner

FPGAmoduleAPEX

400/600/1000

FPGAmoduleAPEX

400/600/1000

FPGAmoduleAPEX

400/600/1000

FPGAmoduleAPEX

400/600/1000

DSPSHARC21160

DSPSHARC21160

DSPSHARC21160

DSP

SHARC21160

ADC

ADC

DAC

DAC

Author:Dr. A.Blaickner

DSP/FPGA-based - VLSI-emulator

FPGAs

2 x 1.5mil.

Gates

System-Clk:

50-100 Msps

DSPs

4x21161 ADI-

Sharc

~1.2 MflopsIO-Bandwidth

~320 Mbyte/s



Communications & Signal ProcessingT Software Definable Radio Transceiver Design (GSM / UMTS)

T System Level Design MATlab & System-C

T System Architecture Integration and Synthesis

T Embedded Parallel Processing Systems DSP/FPGA based

Projects done with MATlab / COSSAP (1991-1999)T FFTs, CORDICs, f-Synth., f/t/p-Synchronizers, TDMA burst modem

T Trained / blind equalization subsystem for broadband channels

T FSK/M-QAM-modems, Wireless networking / MC - modem (OFDM)

T Viterbi codec (radix - 4(2) ) // RS-codes, GF-arithmetic

T DVB- Receiver and FFT/IFFT - modeling, optimization, implement.

T Pipe-lined- FFT, multi-rate filters, half-band- / Avg.- / CIC-filters

T Bit-true modeling and DSP/FPGA- implementation, VLSI-emulation


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Recent Projects on Software Definable TransceiversDigital Channel Processing

T Programmable pulse-shaping and multi-rate filters

T Polynomial based re-sampling interpolation filters (Farrow / Poly-phase)

T Digital frequency synthesis, frequency translation, pipelined- CORDICs

Digital Baseband ProcessingT Pulse-shaping, equalization, correlation, FFT-processing, modulation

detection, synchronization, phase looked & control loops, system ctrl;

System Level Design with SystemC & MATlabFloating point system model

T System simulation and verification Matlab / System-C

Bit-true system model architectural mappingT Bit-true simulation and co-verification CoCentric / SystemC / Matlab

Behavioral- / RTL- HW-description and synthesisT Mapping to a real-time DSP/FPGA - VLSI emulator (test-bed)


Communication Systems - Status

Telecommunication systems - a current status

Multiple standards - fixed system solutions

Various dedicated VLSI - implementations

Next generation system architectures - 3G/4G

UMTS / HIPERLANT Air-interface: WCDMA / TD-CDMA, 384 Kbit/s ... 2 Mbit/s, (QPSK,FDD,TDD)

T 54Mbit: OFDM, QAM

WLAN - IEEE802.11a/b, HIPERLAN, Home-RFT 2Mbit: DSSS, FHSS

T 11Mbit: DSSS (CCK), OFDM, QAM

Digital Broadcasting - DVB, MMDST Air-interface: OFDM, QAM

Coding: Viterbi, Trellis, Turbo, Reed-Solomon or concatenated


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Software Radio - Motivation

Software radio and base-station concepts

Ideal digital software radio receiver

Realistic software receiver architecture

Single system provides various air-interfaces - modulation / coding

Suitable technology: FPGAs, 2 mil. logic gates - e.g. Apex, VirtexT Sufficient system performance and logic capacity for channel processing

T Re-configurable and scaleable over LVDS, Remote re-programming service

T In contrast to DSP-solutions no limits for parallel structures (e.g decoding)

T A system per chip solutions, designed to exact requirements, no overhead

T Cost is comparable to dedicated VLSI-products e.g. band-pass processing

T Limitations: power budget - small terminals, but combine VLSI & FPGA area

Library of scaleable communication sub-modulesT Modulator units, channel-processing, frequency-synthesis, mixer, NCO, data-filter,

interpolator, equalizer, FEC, FFT, adaptive filter, CORDICs, parallel- / bit-serialversions;


Software Radio - Motivation

Conventional coherent digital receiver architecture

Generic software radio receiver architectures

WidebandRF frontend

Digital IFchannelselection

Digital IFchannelselection

Basebandprocessing

Basebandprocessing

System control unit

ADC

Datastream 1

Datastream 2..stream M

I/Q

I/Q


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Radix-2/4Viterbi Codec

Branch andpath metriccalculation

Arbitrarycodingschemes



Electromagnetic Field

Visualization

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0

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X-axis

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Y-axis

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Y-axis

Iso-Surface / Intensity - f(x,y)


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Digital Signal Processing

Z-domain - IIR-band-pass filterImpulse response

Magnitude spectra

z-plane

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Real Part

ImaginaryPart

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ImaginaryPart

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0 50 100 150 200 250 3000

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Tsig

Gain

Time

0 50 100 150 200 250 300-0.5

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1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3-0.5

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Z-domainIIR-band-pass

3-dim plot


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0 50 100 150 200 250 3000

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Gain

Time

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1 2 3 4 5 6 7 8 9-2

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Z-domain - FIR- Averaging FilterImpulse response

Magnitude spectra

z-plane

-150 -100 -50 0 50 100 150-10

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ImaginaryPart

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ImaginaryPart

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Z-domain3-dim plot


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Base-band QAM-Modulator

4..256 QAM

Eye- / Scatter-Plot

QAM-Phasor - Plot


Some MATlab Solutions

MatLab Script ProgrammingVector- / Matrix - multiplexer function (switch)

RESULTab=[((SELseq==0).*DATAa + (SELseq>0).*DATAb);

Vector- / Matrix - comparator functionT re=(mod(hi,128)-128*(hi>127)); im=(mod(lo,128)-128*(lo>127));

Compact FSK-modulator & up-converter functionT Fnyq=0.5/Ssym;Wcar=Eta*(2*pi*Fnyq);Nco=cumsum(real(DatFil)); DatMod=exp(j*Wcar*Nco);

Structure based parameter lists - e.g. complex plot functionT TX.For=struct('Typ',{'Time'},'Sty',{'Stem','ReIm','ReIm','Cplx'});

TX.Dat=struct('Dat',{BinSrc,DatMap,DatFil},'Lab',{'Bsrc','Dmap,'Dfil'}); CplxPlot(TX);

Decimation Filter CoreT CoefRAM_ptr=COFidx+[1:1:COlen]; %Calc final index pointer vector Cram

PRODvec=DataDLYLIN.*CoefRAM(CoefRAM_ptr);%Multiply DlyLine Cvec, do for p 0..pnSUMpart=sum(PRODvec,2); SUMsca=SUMpart; %Accumulate all partial products p0..pnDatInt(Ridx)=SUMsca; Ridx=Ridx+1; %Copy to filter result vector

Adaptive Filter CoreT for k=1:LOPlen; FilRes(k)=PolyIntp(DatInp(k:k+15).',

LPcof(PPcof(1+NCOmu(k),:))); end;


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Some MATlab Solutions

Real-time Hardware InterfaceMEX - file programming

// ------- MEX gateway function ------------------------------------------------------

void mexFunction( int nlhs, mxArray *plhs[], int nrhs, const mxArray *prhs[])

{

double Sps; //Samples per second from Patgen

double SplsRd; //Samples to read ...

if(nrhs!=3) mexErrMsgTxt("usage: DataOut=PATio.... ");

if(!mxIsNumeric(prhs[0])||!mxIsDouble(prhs[0])||... !=1) {mexErrMsgTxt("Input..");}

Sps = mxGetScalar(prhs[0]); /* get the scalar input x */

SplsRd = mxGetScalar(prhs[1]); /* get the scalar input x */

DataInp = mxGetPr(prhs[2]); /* create a pointer to the input matrix y */

NoCol = mxGetN(prhs[2]); /* get the dimensions of the matrix input y */

plhs[0] = mxCreateDoubleMatrix(1, (int)SplsRd, mxREAL); /* set the output pointer */

DataOut = mxGetPr(plhs[0]); /* create a C pointer to copy of output matrix */PATio...(Sps,SplsRd,DataInp,NoCol,DataOut); /* call the C subroutine */

mxSetPr(plhs[0], DataOut); /* Load the new matrix data into plhs[0]. */

}


Conclusion

MATlab based Design of Digital Systems for Applications in the

Communications and Signal Processing Area

E.g. Channel coding, Synchronization units, EqualizationT High speed data transmission, typical system rate 50 ..100 Msps

T M-QAM, OFDM, FHSS, DSSS, ;

Typical application in 3G/4G SystemsT WLAN, UMTS, HIPERLAN, SET-TOP-BOX, xDSL, HFC, HOME-NETworks

HW/SW- co-design and prototyping of complex data path arithmetic

Re-programmability and re-use of standardized hardware proofed

Programmable array system simulator - P.A.S.S.

Digital modem / frequency synthesis / signal processing in general

Questions ???

System Design and Modeling With Simulink

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