Synthesis Test Programmable Logic

joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

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SynthesisTest

Programmable Logic


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RTL Synthesis

Behavioural Behavioural synthesis

RTL RTL synthesis

Logic Place and route

Layout

VHDL was intended for documentation and simulation.

More and more used for design. It’s only possible to synthesise a subset.

VHDL and Verilog are the most common HDL (Hardware Description Languages). VHDL is the most growing.

Synthesis of hardware corresponds to compiling software.

VHDL

Synthesis(+constraints)

Library Reports


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RTL Synthesis, Synthesis and Optimisation

Synthesis

Generic schematics

Optimization + technology mapping

Netlist (+reports)

Result OK?

RTL-VHDL

LibraryTiming and area constraints

Not OK

Optimise for Area or Speed

# of gates Speed (ns)

Fastest 487 4,5

Smalest area 69 10,8


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RTL Synthesis, Constraints

Constraints:• Design rules• Timing constraints• Area constraints

If we design wholly synchronous, only the timing

constraints have to be specified for the I/O pins at

top level (+ clock frequency)!

Always to be specified•Clock inputs and their period• Input delays relative to the clock• Output delays relative to the clock• Pin-to-pin delays• Any false path

• Supply voltage•Temperature range

This can be done in Leonardo. Do this in the project. Show differences

between speed optimised and area optimised.


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Timing constraints

What can we do if we find that the delays are too long compared to clock period? We have set-up violation!

• Choose a faster circuit. But if only one data path is too slow this may be uneconomical.

• We can use pipelining. Se later

&

&clk (50 ns)

Max delay <Tclk-Tsetup-Tdelay-clock scewTclk = 50 nsclock scew = 0,5 nsTsetup = 1 ns

Tdelay = 1 ns

Max delay < 50-1-1-0,5=47,5


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Input and output delay

input delay

&

&

clk (50 ns)

d_in

setup 1 nsmax delay?


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False path

&

&

a

&

&

&

&

b

False path

Some paths have no impact on timing e.g. test inputs / outputs. The path shall be excluded from constraints! False path

command.


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Hold violation

Minimum timing constraints are not always enough! There are always both routing delays and clock skews. In this example

there is a hold violation of 0,1 ns. Optimizing tool must solve it.

How?

clk clk skew 0,5 ns

routing delay 0,1 ns

Hold time 0,1 ns after clockDelay time 0,4 ns


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Hold violation

Optimizer adds a delay!

If we don’t have hold time violation it’s possible to write like this:a(7 downto 1)<=a(6 downto 0);

clk clk skew 0,5 ns

routing delay 0,1 ns

Hold time 0,1 ns after clockDelay time 0,4 ns

delay 0,2 ns


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Design methods, Pipelining

What can we do if we find that the delays are too long compared to clock period? We have set-up violation!

• Choose a faster circuit. But if only one data path is to slow this may be uneconomical.

• We can use pipelining.

&

&clk (20 ns)

delay (30 ns)Problem Tdelay>Tclk-Tsetup


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Design methods, Pipelining• Pipelining: we divide the delay into two or more steps where each step is

short enough to avoid set-up violation.• But we introduce latency! More clock cycles are required.• The clock frequency can be increased.• The throughput increases.• We have to pay with more “silicon”.

&

clk (20 ns)

&

delay (15 ns) delay (15 ns)

No set-up violation


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Verification of designs

Verification methods

• Formal verification (mathematical methods). Equivalent checkers. Compare two designs. Compare design with executable specification. Coming!

• Simulations of design entities from components to systems. Test benches are used.

• Static timing analysis

• Prototypes in FPGAs for ASIC designs


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Verification, Testbenches in VHDL. There are three verification steps during development:• The behavioural model verification• The RTL VHDL model verification• Gate level verification both before and after layout

Testbenches can be used in all three steps. Simulations!

VHDL behavioural

model

VHDL RTL model

Gate level e.g. VITAL

VHDL test bench

simulations

Simulation outputs e.g. test vectors to be used in Tests


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Verifying the design

Testbench

VHDL comp ”signal gener.”

VHDL comp ”logic analyser”

Computer VHDL ”prototype”

A B

Verification with a testbench (A and B) in the computer

Inputs+outputs = functional test vectors


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TestWe test physical components and systems (SoC / MCM / PCB) to find faults related to production processes

Internal faultsBonding faults

Package faults


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Test

More complex circuits will require longer test times

Combi-national

net

1

25

225 combinations => 3 seconds at 10 MHz

Combi-national

net

1

50

250 combinations => 3 years at 10 MHz


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Test

More complex circuits will require longer test times

Sequential net

50 states

1

25

250+25=275 combinations => 114 million years at 10 MHz!


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Testable

If a circuit shall be testable every node in the circuit must be:

• Controllable: An internal node is controllable if it can be driven to any value.

• Observable: An internal node is observable if its value can be predicted and propagated to a circuit output for it to be checked.


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Fault models

&

&

+stuck to one

stuck to zero

break

short circuit

short circuit


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Test patterns

The inputs and outputs to and from a test object are called TEST VECTORS.

Test vectors

FunctionalFrom Test benches

From ATPGAutomatic Test Pattern Generator

ATPG = Theoretical methods to give high fault

coverage


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Structured method, Scan technique

Com-binational

logic

RegisterScan_in

Clk

Test

Scan_out

Model for sequential logic. Compare with a state machine!


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Scan cell

ck q

d

reset

scan_in

ck q

scan_enable

d

reset

From scan_out on previous FF

To scan_in on next FF

Common scan_enable

Synthesis tool

Test vectors from ATPG


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Design rules for ATPG (examples)

• Include scan cells• This can be automatically

done by synthesis tools for ASICs

scan_in Q

clk

scan_enable

D

reset

1

• Avoid combinational feed back (asynchronous design)

2

Not controllable!


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• Not controllable clock3

• Not controllable clock (gated clock)4

clk

clk

Not controllable!

Not controllable!


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• Not controllable asynchronous reset5

• No clock on data input6

resetclk

clk


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Test of “systems”. Boundary scan

PCB with high density of components and MCM (Multi Chip Modules) are hard to test with conventional methods

(test fixtures with needles)

Comp 1

BS

cells

Comp 2

BS

cells

Comp 3

BS

cells

Comp 4

BS

cells

Boundary Scan:

Every IO-pin shall have an alternative function: A Boundary Scan Cell. The BS-cells in different circuits are connected in chains. Test pattern can be shifted in and shifted out (controllabe and observable)


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Test of “systems”. Boundary scan

Boundary Scan:

Many circuits have built in BS (e.g. FPGAs) The standard for BS is IEEE 1149 (JTAG)

Instructions to the BS cells are shifted in to the BS Engine (TAP-controller = State machine).

(TDI, TDO, TMS, TCK)

Comp 1

BS

cells

Comp 2

BS

cells

Comp 3

BS

cells

Comp 4

BS

cells

TAP

TAP TAP

TAP


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VHDL source

Compiler/Simulator

Synthesis

Place & Route

Load circuit

Xilinx CPLD/FPGA

Mentor Leonardo

Mentor HDL Design Browser

Mentor Modelsim

Xilinx Foundation

Netlist (.edif)Logical blocks

Use physical blocks and inter connections Bit map for

programmable links


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FPLD = Field Programmable Logic Device.

FPGA = Field Programmable Gate Array. >1 milj gates!

PLD = Programmable Logic DeviceCPLD = Complex PLD. <10k gatesSoPC = System on Programmable Chip

ASIC = Application Specific Integrated CircuitGate Array = Prefabricated wafer with logic+added

interconnections (metal layers). Vol > 10kStandard Cell = Library with components (e.g. gates,

multiplexors, flip-flops). Precompiled on transistor level. Vol >100k

Full Custom = Transistor level design. Used for analog circuits.

SoC = System on Chip. Processors and logic on chip.

Customer Integrated Circuits

ASIC

Gate Array

Std Cell

Full Custom

(F)PLD

FPGA PAL

CPLD PLDSoC SoPC


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PLD technology

Flash RAM AntifuseFuse

Fuse: Oldest technique. Metal links are used as connection points and they are broken by programming currents.

Flash: Flash ROM cells are used to control the transistors at the connection points. Non volatile and reprogrammable. Used in CPLDs. 10k gates.

RAM: Static RAM cells are used to control the transistors at the connection points. Volatile and must have external memory for data pattern. Used in the biggest FPGA (milions of gates).

Antifuse: Antifuses are created when currents flow through a amorphous silicon connection wich is transferred from an insolator to a connector. Non volatile and used in medium sized FPGA.

Programmable logic


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PLD technology

Flash RAM AntifuseFuse

on

off

Product term

Connection

Floating gate transistors

Connection

RD/WR

Connector 1

Connector 2

Data

SRAM memory

off

on

amorphous Si

crystaline Si

Transferred from amorphous to crystaline Si by current injection


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Some slides from this book from Xilinx


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• Two programmable planes

• Any combination of ANDs/ORs

• Sharing of AND terms across

multiple ORs

• Highest logic density available to user

• High Fuse count, slower than PLAs

• Programmable Logic Array - PLA


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• One programmable plane – AND /

Fixed OR

• Finite combinations of ANDs / ORs

• Medium logic density available to user

• Lower Fuse count, Faster than PLAs

(at this time fabricated on 10 µm process

• Programmable Array Logic - PAL


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• Central, Global Connect

• Simple, Deterministic Timing

• Easily routed

• PLD Tools add only interconnect

• Wide, fast complex gating

50 - 200 gates

Interconnects gates Flip-Flops


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PLD structures

PALMacrocell

LUT

I1 I2

and

and

O1= (I1 and not I2) or (not I1 and I2)

Macrocell

or O1=1


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PLD structuresCPLD Xilinx 9572

(used in labs)

I/O Blocks

I/O

I/O

I/O

I/O

GCK

Block 1Macrocell

1 to 18

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18

Block 2Macrocell

1 to 18

36

18

Block 3Macrocell

1 to 18

36

18

Block 4Macrocell

1 to 18

36

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Switch matrix

.

.

.

.

.


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PLD structures

PALMacrocell

LUT

Addr I1 I2 O1

0 0 0 0

1 1 0 1

2 0 1 1

3 1 1 0

O1= (I1 and not I2) or (not I1 and I2)

LUT1(16*1 bit mem) LUT = LookUpTable

16 product terms /LUT

O1FF1

LUT1

IO

IO

IO

IOLUT2

I1I2

Programmable LUTs and programmable routing

PLD structures FPGA Xilinx Spartan X10 (used in projects)


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• Channel Based Routing

• Post Layout Timin

• Tools more complex than CPLDs

• Fine grained

• Fast register pipelining

Interconnects Gates


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ASIC/FPGA

0,6m 0,35m 0,25m 0,13m

250kkr

1000kkr

10 000kkr

NRE=Non Recurring Cost(mask cost)

Non recurring=engångs

NRE

process

ASIC

FPGA

0,09m 0,045m

20 000kkr

Synthesis Test Programmable Logic

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