Synthesis Six Sigma Process Corners

© Copyright AgO Inc 20111

Synthesis


100X Faster Simulation and Six Sigma Optimization


SoC Design Objectives

Respin avoidance• Analog circuits are responsible for ~ 50% of IC design re-spins• Re-spins can mean missing market windows and unbudgeted costs

Achieving design specification• Meeting or beating performance while minimising cost of implementation• Managing greater complexity in operating and power saving modes

Maximising yield• Validating greater numbers of process, voltage and temperature corners• Efficiently centering design across all PVT corners using Monte Carlo

Design porting• Moving existing circuit designs to similar technologies• Re-centering design to meet constraints of new technology


Analog Design Flow

• Design methodology has changed little over the years• Manual, iterative design with many SPICE runs

Define topology &

resize devices

Physical layout& adjust

ExtractionLayout verification

Designspecification &

constraints

Spice

Spice


Massively Parallel Optimization

Feasibility Global Optimization Centering Database

Description• DC Operation• Increase Margin• Quick check• Best Design

Space

Description• Single Corner• Meet

performance• Monte Carlo• Ready for Center

Description• All Corners• Rapid Size• Ready for P&R

Description• Conflict• Change Priority• System Analysis

AgO Optimization Strategy


AnXplorer Goals

• Quickly size W/L a circuit in a given technology• Explore suitability of different design options • Robust design over PVT & Monte Carlo• Support all types of devices• Explore results using database• Optimize production yield


AgO Design Methodology

AnXplorer automates device sizing

Define topology

Physical layout& adjust

ExtractionLayout verification

Designspecification &

constraints

Feasibility

Global

Centering


Process Porting

Vendor A

Vendor B

Common challenge• Port existing design in technology X (say

180 nm) to technology Y (in 180 nm)• Ensure that original design goals are met

AnXplorer approach

• Start with original sized circuit• Define variable ranges for target circuit• “One click” command• Optimises and centers with new PVT

corners

Vendor Node Porting


Prioritized Design Objectives

• Most tools support weight-based prioritisation for multiple objectives– Designer often unsure of relative weights – bad

design practice• AnXplorer supports hierarchical design objectives

– User defines relative priority • AnXplorer achieves important objectives before

optimizing low priority signals


Implicit Objectives

• Imposes implicit objectives on conditions of devices at DC operating point

• Customizable Implicit objectives• Detects common sub-circuits and

imposes constraints on their operating conditions

• Ensures a robust DC • Available for MOS devices only

Examples of sub-circuits:• transistors in

saturation• transistors in linear

region• current mirrors• level shifters• differential pairs• voltage reference• current mirror

banks• etc


Core Optimization Technology

Early Optimisation tools• Frequently relied on traditional

convex/gradient methods• These are known to have difficulty

with multiple local minima

AnXplorer• Based on advanced Evolutionary

algorithm• Capable of finding global minimum in

presence of many local minima• Successfully optimised tough tests

Rastrigin’s function• logarithmic partitioning of design

space

Supports both simulation-based optimization & equation-based optimization


Multiple Local Minimum

12


Trade-off Analysis Database

• Finds multiple design points satisfying design objectives

• Creates exploration database for post-optimization analysis– Database stores all explored design points– Query language or GUI

• Useful for trade-off analysis with conflicting objectives

• Useful for “what-if” analysis


Industry Standard Formats

AnXplorer

Design objectives Un-sized circuit

Schematics

Sized and centerednet list

Exploration database for

Trade off analysis

Definition of Design variables

Compatible with existing design flows


Design Environment

• Spice Simulators– Cadence – Synopsys – Mentor – Multi-threading support

• Operating system– 64 Bit Red Hat RHEL 5


Differentiation• Push bottom integrated technology• Robust Circuits to maximise yield –Monte Carlo• Implicit objectives for stable DC operation• Hierarchical design objectives• Trade-off analysis database• Industry standard simulators• Advanced Evolutionary Algorithm


Demo and License

Hillol Sarkar

[email protected]

Synthesis Six Sigma Process Corners

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