SynthesisSynthesis

Presented by: Ms. Presented by: Ms. Sangeeta L. MahaddalkarSangeeta L. Mahaddalkar

ME(Microelectronics) Sem IIME(Microelectronics) Sem II

Subject:Subject: ASIC Design and FPGA

Topics DiscussedTopics Discussed

Introduction to SynthesisIntroduction to Synthesis Synthesis processSynthesis process Synthesis ToolsSynthesis Tools Guidelines for codingGuidelines for coding Synthesis examplesSynthesis examples

SYNTHESISSYNTHESIS

Automatic method of converting a higher level Automatic method of converting a higher level of description of the design into an optimized of description of the design into an optimized gate level description given standard cell library gate level description given standard cell library (Technology library) and certain design (Technology library) and certain design constraintsconstraints

Synthesis tools convert Synthesis tools convert High Level descriptionsHigh Level descriptions (HDL Description) into (HDL Description) into gate level netlistsgate level netlists

Gate level netlist synthesisGate level netlist synthesis

Technology Library

High Level Description

Constraints

Gate Level Netlist

Synthesis

Timing,Area,

Testability, Power

VHDL,Verilog

Standard cell library – logic

gates, macrocells

SYNTHESIS PROCESSSYNTHESIS PROCESS

VHDL RTL Description

Unoptimized Boolean Description

Optimized Boolean Description

Gate Level Netlist

Translate

Optimize

Map to Gates

Created by user

Created by synthesis tool

Synthesis Process …Synthesis Process …

TranslationTranslation– Converting from Converting from RTL Description to boolean RTL Description to boolean

equivalent descriptionequivalent description

– IF, CASE, LOOP , Conditional signal IF, CASE, LOOP , Conditional signal assignment statements, Selected signal assignment statements, Selected signal assignment statements are converted to their assignment statements are converted to their boolean equivalent form.boolean equivalent form.

Synthesis Process…Synthesis Process…

Boolean Optimization Boolean Optimization – convert an unoptimized boolean description into optimized convert an unoptimized boolean description into optimized

boolean formboolean form– Quine-McCluskey AlgorithmQuine-McCluskey Algorithm was used earlier was used earlier– Presently Presently Espresso heuristic logic minimizerEspresso heuristic logic minimizer is a standard is a standard

tool for optimizationtool for optimization– Logic optimization algorithms generally work either on the Logic optimization algorithms generally work either on the

structuralstructural (SOP, factored form) or (SOP, factored form) or functionalfunctional (BDD) (BDD) representation of the circuit. representation of the circuit.

Mapping to GatesMapping to Gates– Takes logically optimized boolean description created by Takes logically optimized boolean description created by

optimization step and uses logical and timing information optimization step and uses logical and timing information from technology library to build a netlistfrom technology library to build a netlist

SYNTHESIS TOOLSSYNTHESIS TOOLS Software tools for logic synthesis targeting ASICs

– Design Compiler by Synopsys – Encounter RTL Compiler by Cadence Design System – BuildGates an older product by Cadence Design System – BlastCreate by Magma Design Automation – BooleDozer Logic synthesis tool by IBM

Software tools for logic synthesis targeting FPGAs– Encounter RTL Compiler by Cadence Design System – Leonardo Spectrum and Precision (RTL/Physical) by Mentor

Graphics – Synplify (PRO / Premier) by Synplicity – BlastFPGA by Magma Design Automation – Quartus II integrated Synthesis by Altera – XST (delivered within ISE) by Xilinx – DesignCompiler Ultra and IC Compiler by Synopsys – IspLever by Lattice Semiconductor

Synthesis from VHDL / VERILOGSynthesis from VHDL / VERILOG

1. 1. Layout synthesisLayout synthesis

2. 2. Logic synthesisLogic synthesis

3. 3. RTL synthesisRTL synthesis

4. 4. High Level SynthesisHigh Level Synthesis

5. 5. System SynthesisSystem Synthesis

Coding for SynthesisCoding for Synthesis VHDL and Verilog are hardware description VHDL and Verilog are hardware description languages and simulation languages that were languages and simulation languages that were not not originally intended as inputs to synthesis. originally intended as inputs to synthesis.

Therefore, many hardware description andTherefore, many hardware description andsimulation constructs are not supported by simulation constructs are not supported by

synthesis tools. synthesis tools.

VHDL and Verilog semantics are well defined for VHDL and Verilog semantics are well defined for design simulation. The synthesis design simulation. The synthesis tools must tools must

adhere to these semantics to ensure that designs adhere to these semantics to ensure that designs simulate the same way before and after synthesis. simulate the same way before and after synthesis.

Guidelines to be followed to create code that Guidelines to be followed to create code that simulates the same way before and after synthesis.simulates the same way before and after synthesis.

1.1. Omit the Wait for StatementOmit the Wait for Statement

eg. Wait for 20 ns; eg. Wait for 20 ns; - VHDL construct- VHDL construct # 20 ns;# 20 ns; - Verilog construct - Verilog construct

This statement This statement does not synthesize to a componentdoes not synthesize to a component. . In order to describe a similar “wait-for-time effect” that can be synthesized, we need to describe it as an FSM state that self-loops until a counter (set or reset at an earlier state) reaches a count value that translates to the desired wait time needed (Count value decided based on the clock speed).

Guidelines contd …Guidelines contd …

2.2. Omit the ...After clause or Delay StatementOmit the ...After clause or Delay Statement

...After XX ns statement in VHDL code....After XX ns statement in VHDL code. Delay assignment in Verilog code. Delay assignment in Verilog code.

eg.eg. Q <=0 after 20 ns;Q <=0 after 20 ns; - VHDL- VHDL assign #20 Q=0;assign #20 Q=0; - Verilog- Verilog

These statements are usually These statements are usually ignored by the synthesis ignored by the synthesis tool. tool.

Guidelines contd …Guidelines contd …

3.3. Omit Initial ValuesOmit Initial Values Do not assign signals and variables initial Do not assign signals and variables initial

values because values because initial values are ignoredinitial values are ignored by most synthesis tools. by most synthesis tools.

Eg. do not use initialization statements likeEg. do not use initialization statements like signal sum : integer := 0; signal sum : integer := 0; - VHDL- VHDL initial sum = 1’b0;initial sum = 1’b0; - Verilog- Verilog

Guidelines contd …Guidelines contd …4.4. Order and Group Arithmetic FunctionsOrder and Group Arithmetic Functions

The ordering and grouping of arithmetic functions can influence The ordering and grouping of arithmetic functions can influence design performance. design performance.

eg.eg. ADD1 <= A1 + A2 + A3 + A4; ADD1 <= A1 + A2 + A3 + A4; --Statement 1Statement 1

ADD1 <= (A1 + A2) + (A3 + A4); ADD1 <= (A1 + A2) + (A3 + A4); --Statement 2Statement 2

The first statement The first statement cascades three adderscascades three adders in series. in series.

The second statement creates The second statement creates two adders in paralleltwo adders in parallel: A1 + A2 : A1 + A2 and A3 + A4. In the second statement, the two additions are and A3 + A4. In the second statement, the two additions are evaluated in parallel and the evaluated in parallel and the results are combined with a third results are combined with a third adderadder. .

RTL simulation results are the same for both statements, RTL simulation results are the same for both statements, however, the second statement results in a however, the second statement results in a faster implementationfaster implementation

Guidelines contd …Guidelines contd …

5.5. Don’t Mix positive and negative edge Don’t Mix positive and negative edge triggered flipflops in a designtriggered flipflops in a design

It may introduce inverters and buffers in It may introduce inverters and buffers in the clock tree. This the clock tree. This can add clock skewscan add clock skews in in the circuit.the circuit.

library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity t12 is Port ( a,b,c,d,e : in std_logic;

o : out std_logic);end t12;

architecture Behavioral of t12 is signal temp:std_logic;

begin process(a,b,c,d,e) begin temp<=a xor b; temp<=temp xor c; temp<=temp xor d; temp<=temp xor e; end process; o<=temp;

end Behavioral;

Wrong Hardware Inferred

Logic Synthesis ExamplesLogic Synthesis Examples

Examples…Examples…library IEEE;library IEEE;

use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_1164.ALL;

entity t12 isentity t12 is

Port ( a,b,c,d,e : in std_logic;Port ( a,b,c,d,e : in std_logic;

o : out std_logic);o : out std_logic);

end t12;end t12;

architecture Behavioral of t12 isarchitecture Behavioral of t12 is

beginbegin

process(a,b,c,d,e)process(a,b,c,d,e)

variable temp:std_logic;variable temp:std_logic;

beginbegin

temp:=a xor b;temp:=a xor b;

temp:=temp xor c;temp:=temp xor c;

temp:=temp xor d;temp:=temp xor d;

temp:=temp xor e;temp:=temp xor e;

o<=temp;o<=temp;

end process;end process;

end Behavioral;end Behavioral;

Correct Hardware Inferred

Combinational Logic SynthesisCombinational Logic Synthesis

library IEEE;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_1164.ALL;entity t12 isentity t12 is Port ( a,b,clk : in std_logic;Port ( a,b,clk : in std_logic; o : out o : out

std_logic);std_logic);end t12;end t12;

architecture combinational of t12 isarchitecture combinational of t12 isBeginBeginprocess(clk,a,b)process(clk,a,b)BeginBegin

o<=a and b and clk;o<=a and b and clk;end process;end process;end combinational;end combinational;

2 Input AND gate with enable

Sequential Logic SynthesisSequential Logic Synthesis

library IEEE;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_1164.ALL;entity t12 isentity t12 is Port ( a,b,clk : in std_logic;Port ( a,b,clk : in std_logic; o : out std_logic);o : out std_logic);end t12;end t12;

architecture sequential of t12 isarchitecture sequential of t12 isBeginBeginprocess(clk,a,b)process(clk,a,b)BeginBegin

if(clk'event and clk='1')thenif(clk'event and clk='1')then o<= a and b;o<= a and b;end if;end if;

end process;end process;end sequential ;end sequential ;

Note: Here we are assigning on edge of clk . Hence it infers a Flipflop

Latch inferenceLatch inference

library IEEE;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_1164.ALL;entity t12 isentity t12 isPort ( a,b,clk : in std_logic;Port ( a,b,clk : in std_logic; o : out std_logic);o : out std_logic);end t12;end t12;

Architecture latch of t12 isArchitecture latch of t12 is beginbeginprocess(clk,a,b)process(clk,a,b)beginbegin if(clk='1')thenif(clk='1')then

o<= a and b;o<= a and b;end if;end if;

end process;end process;end latch;end latch;

Note: Here we are assigning on level of clk . Hence it infers a latch

Mux Coding - Latch InferredMux Coding - Latch Inferred

module mux(a,b,sel, o);module mux(a,b,sel, o); input a,b,sel;input a,b,sel; output o;output o; reg o;reg o; always @(a or b or sel)always @(a or b or sel) beginbegin

case(sel)case(sel) 1'b0: o<=a;1'b0: o<=a;

endcaseendcase endendendmoduleendmodule

Note: Here one of the inputs is not assigned to output. Hence Latch inferred

Mux Coding - Latch Inferred…Mux Coding - Latch Inferred…

module mux(a,b,sel, o);module mux(a,b,sel, o);

input a,b,sel;input a,b,sel;

output o;output o;

reg o;reg o;

always @(a or b or sel)always @(a or b or sel)

beginbegin

casex(sel)casex(sel)

1'b0: o<=a;1'b0: o<=a;

1'b1: o<=b;1'b1: o<=b;

endcaseendcase

endend

endmoduleendmodule

Note: casex statement used. Latch inferred

Correct Mux InferredCorrect Mux Inferred

module mux(a,b,sel, o);module mux(a,b,sel, o); input a,b,sel;input a,b,sel; output o;output o; reg o;reg o; always @(a or b or sel)always @(a or b or sel) beginbegin case(sel)case(sel) 1'b0: o<=a;1'b0: o<=a; 1'b1: o<=b;1'b1: o<=b; default: o<=1’bx;default: o<=1’bx; endcaseendcase endend endmoduleendmodule

Regitered Decoder SynthesisRegitered Decoder Synthesismodule mux(clk,reset,data,q);module mux(clk,reset,data,q);

input clk,reset;input clk,reset;

input [1:0]data;input [1:0]data;

output [3:0]q;output [3:0]q;

reg [3:0] q; reg [3:0] q;

wire [1:0] d; wire [1:0] d;

always @(posedge clk) always @(posedge clk)

if (reset) q <= 4'b0;if (reset) q <= 4'b0;

elseelse

case (data) case (data)

2'b00 : q <= 4'b0001; 2'b00 : q <= 4'b0001;

2'b01 : q <= 4'b0010; 2'b01 : q <= 4'b0010;

2'b10 : q <= 4'b0100; 2'b10 : q <= 4'b0100;

2'b11 : q <= 4'b1000; 2'b11 : q <= 4'b1000;

default : q <= 4'b0000; default : q <= 4'b0000;

endcaseendcase

endmoduleendmodule

ReferencesReferences

VHDL – Programming By examples –VHDL – Programming By examples –Douglas L. PerryDouglas L. Perry

en.wikipedia.org/wiki/en.wikipedia.org/wiki/LogicLogic__synthesissynthesis Application Specific IC’s – M.J. SmithApplication Specific IC’s – M.J. Smith