Synthesis for Test Virendra Singh Indian Institute of Science Bangalore [email protected] IEP on...

9
Synthesis for Test Virendra Singh Indian Institute of Science Bangalore [email protected] IEP on Digital System Synthesis @ IIT Kanpur

Transcript of Synthesis for Test Virendra Singh Indian Institute of Science Bangalore [email protected] IEP on...

Page 1: Synthesis for Test Virendra Singh Indian Institute of Science Bangalore virendra@computer.org IEP on Digital System Synthesis @ IIT Kanpur.

Synthesis for Test

Virendra SinghIndian Institute of Science

[email protected]

IEP on Digital System Synthesis @ IIT Kanpur

Page 2: Synthesis for Test Virendra Singh Indian Institute of Science Bangalore virendra@computer.org IEP on Digital System Synthesis @ IIT Kanpur.

Dec 20,2007 SfT@iitk 2

Testability

Objective

• Improve

• Controllability

• Observability

• Reduction in sequential depth

Page 3: Synthesis for Test Virendra Singh Indian Institute of Science Bangalore virendra@computer.org IEP on Digital System Synthesis @ IIT Kanpur.

Dec 20,2007 SfT@iitk 3

Controllability

+

*-

a

R (b)

Primary input

R(c)

+ *

-

R(a)

R(b)

Primary input

R(c)

0

1

2

0

1

2

R = (b,c, …)

Not directly controllable

R = (a,b,c, …)

Directly controllable

Page 4: Synthesis for Test Virendra Singh Indian Institute of Science Bangalore virendra@computer.org IEP on Digital System Synthesis @ IIT Kanpur.

Dec 20,2007 SfT@iitk 4

Observability

R2(z)

R1 = (….,w,x, …)

Not directly observable

+ *

-

t

t+1

t+2

*

R1(w)

R2(y)R1(x)

t+3

+

*-

t

t+1

t+2

*

R1(w)

R1(y)

R1(x)

t+3R1(z)

Page 5: Synthesis for Test Virendra Singh Indian Institute of Science Bangalore virendra@computer.org IEP on Digital System Synthesis @ IIT Kanpur.

Dec 20,2007 SfT@iitk 5

Sequential Depth Reduction

R2(z)

*1

*2-

t

t+1

t+2

+

R1(w)

R2(y)

R1(x)

t+3

R2(v)R3(s)

R3(u)

R2(z)

*1 *2

-

t

t+1

t+2

+

R1(w)

R2(y)R1(x)

t+3

R2(v)

R3(s)

R3(u)

Page 6: Synthesis for Test Virendra Singh Indian Institute of Science Bangalore virendra@computer.org IEP on Digital System Synthesis @ IIT Kanpur.

Dec 20,2007 SfT@iitk 6

Mobility Path

* * * +

*

*

* + <

--

1 2

3

4

5

6

7

8

9

10

11

TIME 1

TIME 2

TIME 3

TIME 4

Page 7: Synthesis for Test Virendra Singh Indian Institute of Science Bangalore virendra@computer.org IEP on Digital System Synthesis @ IIT Kanpur.

Dec 20,2007 SfT@iitk 7

Mobility Path

* *

*

+

-

-

TIME 1

TIME 2

TIME 3

TIME 4

Page 8: Synthesis for Test Virendra Singh Indian Institute of Science Bangalore virendra@computer.org IEP on Digital System Synthesis @ IIT Kanpur.

Dec 20,2007 SfT@iitk 8

Mobility Path SchedulingMobility_path_scheduling(G){

1. ASAP_scheduling(G);

2. ALAP_scheduling(G);

3. Update_op_slack_and_mobility(G);

4. While (unscheduled_op(G) ≠ 0){

5. Pk = next_min_mobility_path(G);

6. partial scheduling(Pk, G);

7. testMP(Pk, G); /analyze testability on Pk

8. }

9. }

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Dec 20,2007 SfT@iitk 9

Mobility Path Schedulingpartial_scheduling(Pk,G){

1. For each (operation o on Pk)

2. if (o.earliest = o.latest) // mobility becomes 0

3. o.active = o.earliest // assign schedule

4. Update_op_slack_and)mobility(G);

5. While (unscheduled_op (Pk) ≠ 0){

6. (o, o.ll_cycles) = next_op_with _least_no_light_load_cycles(Pk, G);

7. o.active = most_preferred_cycle(o.ll_cycles, G);