Switching Theory and Logic Design
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Transcript of Switching Theory and Logic Design
![Page 1: Switching Theory and Logic Design](https://reader036.fdocuments.us/reader036/viewer/2022081507/577cce591a28ab9e788dd40c/html5/thumbnails/1.jpg)
Switching Theory and Logic Design
Combinational Logic Design
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Overview
• Introduction• Design using conventional logic gates– Adder– Subtractor– Multiplier– Magnitude Comparator
• Encoder• Decoder• Multiplexer• De-Multiplexer
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Introduction
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Combination Logic Example
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Design using conventional logic gatesAdders-Half Adder
0 + 0 = 00 + 1 = 11 + 0 = 11 + 1 = 10
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Design using conventional logic gatesAdders-Full Adder
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Design using conventional logic gatesFull Adder-Using 2 Half Adders
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4-bit Binary Adder or Ripple Carry Adder
• Addition of n-bit numbers requires a chain of n full adders or a chain of one-half adder and n-1 full adders
• If we use Classical method, then 29 = 512 entries for 9-inputs in truth table as seen in half and full adders
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Adders-Carry Propagation• In ripple carry adder the propagation delay in each stage will add up to the final stage.• Pi (Carry Propagate)and Gi (carry generate) settle to steady-state after propagating
through respective gates.• Form input Ci to output Ci + 1carry propagates through AND and OR.• In n-bit adder, 2n gates for carry between input and output• To reduce carry propagation Carry Lookahead logic is widely used
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4-bit Carry stage
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4-bit Carry Lookahead Adder
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Design using conventional logic gatesSubtractor-Half subtractor
0 + 0 = 00 + 1 = 1 with barrow 11 + 0 = 11 + 1 = 0
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Design using conventional logic gatesSubtractor-Full subtractor
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4-bit Adder-Subtractor
If M=0 and Co=0, then above circuit acts as 4-bit adder If M=1 and Co=1, then above circuit acts as 4-bit subtractor
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Binary Multiplier-(2-bit by 2-bit)
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Binary Multiplier-(4-bit by 3-bit)
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Magnitude Comparator• It is a combination circuit which compares two numbers A and B.• A = B, A > B, A < B
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4-bit Magnitude Comparator
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Encoders• An Encoder has 2^n (or fewer) input and n outputs• An example of octal to binary encoder is discussed below• encode discussed below has limitation that only one input must be active• Ambiguity between all input 0’s and Do
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Priority Encoder
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Four Input Priority Encoder
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Decoders
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Decoder (2 to 4)- Active Low• Decoder given here has
• Active low Enable (E) input• Active low outputs (D0, D1,D2, D3)• Active high inputs (A and B)
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Decoder (3 to 8)
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Decoder (4 to 16)
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Combination Logic Design
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Multiplexer
• 2^n inputs• n selection lines• 1 output
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Multiplexer (2 to 1)
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Multiplexer (4 to 1)
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Multiplexer (Quadruple 2 to 1)
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Combinational Logic Design (Eg.1)
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Combinational Logic Design (Eg.2)
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Design using conventional logic gatesAdders-Half Adder
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Design using conventional logic gatesAdders-Full Adder
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Design using conventional logic gatesFull Adder-Using 2 Half Adders
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Design using conventional logic gatesSubtractor-Half Subtractor
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Design using conventional logic gatesSubtractor-Full Subtractor
D=A XOR B XOR CBOR_out = A’ B + (A XOR B)’ B_in
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4 to 2 Encoder
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2 to 4 Decoder
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Decoder