1

Switched Doherty PAs for 3G

Thomas Apel

2300 NE Brookwood Parkway

Hillsboro, OR 97124

2

Outline

• Introduction and motivation

• Pros and Cons

• Background: Stepped bias and switched periphery

• Switched Doherty

• Example PAs

• Performance improvement techniques

• Test data

• Tristate switched Doherty PA in BiHEMT process

• Conclusion

3

Why Use Switched Doherty PAs?

• CDMA talk-time is strongly influenced by PA current

• Average PA current is dependent on power efficiency

at low power levels (in addition to full power PAE)

• Improvement in low power PAE requires:

– a reduction in supply voltage OR

– an increase in load impedance

(compared to full power levels)

• Load impedance can be changed explicitly (switched)

or implicitly (periphery switching)

• The results reported here use implicit load control to

improve low power efficiency

4

Pros and Cons

• Switched Doherty PAs are not easy to implement

– Z inverter (Zo and insertion phase)

– Delay line (Zo and insertion phase)

– Interstage branch impedances

– ALL MUST BE CORRECT- consistent with final stage segmentation

• Performance advantages include:

– High PAE in both low and high power modes

– No insertion phase discontinuity during mode change

– Increased load insensitivity and superior 3rd order reverse IMD due to quadrature operation in high power mode

– All periphery is used in high power mode

– External load impedance is same as conventional PA

5

Background: Conventional PA with Stepped Bias

• 1st GENERATION

CONVENTIONAL PA

• 1-BIT CONTROL

• ONLY DC QUIESCENT

REDUCTION IN LOW MODE

• POOR LOW MODE PAE DUE

TO MISMATCH

TQ7632

Z Load

Z int

LP

RF output

RF input

BASE BIAS-1

BASE BIAS-2

+ Vreg

+ Vcc

+ Vreg

Hi/Lo Step

6

Background : Conventional PA with Switched Periphery

RF output

RF input

BASE BIAS-1

BASE BIAS-2

+ Vreg

+ Vcc

+ Vreg

Hi/Lo Step

BASE BIAS-2A

+ Vreg

Z Load

Z int

LP

TQ7634

• 2nd GENERATION

CONVENTIONAL PA

• 1-BIT CONTROL

• BETTER LINEARITY IN LOW

MODE THAN STEPPED BIAS

• POOR LOW MODE PAE DUE

TO MISMATCH

7

Switched Periphery Load Sharing

Z LOAD

M · Z

LO

AD

LO

AD

Q2

Q1

(open)

LO

AD

Q2

Q1

Z L

OA

D

Z LOAD

M · Z _M - 1

LOAD

HIGH POWER MODE LOW POWER MODE

8

Switched Doherty Load Sharing

Z LOAD

M · Z

LO

AD

LO

AD

Q2

Q1

(open)

LO

AD

Q2

Q1

Z L

OA

D

Z LOAD

M · Z _M - 1

LOAD

M · Z LOAD M2 · Z LOAD

Zo =M · Z LOAD

= 90°

Zo =M · Z LOAD

= 90°

HIGH POWER MODE LOW POWER MODE

9

CDMA Load Sharing Prototype

Z

INV

ER

TE

R

18

4.5 Q1

Q2

6

Z0 = 18

18

DELAY

LINE

Z

INV

ER

TE

R

(open)

4.5 Q1

Q2

72

4.5

Z0 = 18

DELAY

LINE

HIGH POWER MODE LOW POWER MODE

10

Constant-K LC Impedance Inverter

L= Z0/

0, C= (

0 Z

0)-1

C C

L

11

M-derived LC Impedance Inverter

Cs

L

Ls

Cs

Ls

L= Z0/

0, Ls= Z

0(3

0)-1, Cs= 3(4

0Z

0)-1

TRAP RESONANCE SET TO 2nd HARMONIC

12

Switched Periphery to Switched Doherty

+ Vcc-1

DE

LA

Y

LIN

E

RF output

+ BIAS-A

Z

INV

ER

TE

R

+ BIAS-B

RF output

+ Vcc-1

+ BIAS-B

+ BIAS-A

SWITCHED

PERIPHERY

SWITCHED

DOHERTY

13

Switched Doherty PA

RF output

RF input

BASE BIAS-1

BASE BIAS-2

+ Vreg

+ Vcc

+ Vreg

Hi/Lo Step

BASE BIAS-2A

+ Vreg

DE

LA

Y

LIN

E

Z

INV

ER

TE

R

14

Low Power Mode

RF output

RF input

BASE BIAS-1

BASE BIAS-2

+ Vreg

+ Vcc

+ Vreg

Hi/Lo Step

BASE BIAS-2A

+ Vreg

DE

LA

Y

LIN

E

Z

INV

ER

TE

R

OFF

OFFOFF

15

Low Power Mode

RF output

RF input

BASE BIAS-1+ Vreg

+ Vcc

BASE BIAS-2A

+ Vreg

Z

INV

ER

TE

R

OPTIMUM PERIPHERY

AND

OPTIMUM LOAD

16

Contrast with Other Techniques

DUAL PATH ARCHITECTURE HIGH POWER MODE

SWITCHED DOHERTY IS DUAL PATH

SPECIAL CASE

BASE BIAS-2A

BASE BIAS-2B

RF output

(~ 4 )

Z0 ~

17

Z

INV

ER

TE

R

Z0 ~

17

Z

INV

ER

TE

R

BASE BIAS-2A

BASE BIAS-2B

OFF OFFRF output

(~ 4 )

ZL ~ 70

17

Contrast with Other Techniques (continued)

SWITCHED DUAL PATH DISTORTION IN HIGH POWER MODE

Z

INV

ER

TE

R

ZIN ~ 0

ZL =

RF output

(~ 4 )

BASE BIAS-2A

BASE BIAS-2B

OFF OFFHigh RF

Voltage

Z0 ~

17

Z

INV

ER

TE

R

BASE BIAS-2A

BASE BIAS-2B

RF output

(~ 4 )

D

S

Switch

Control

18

Isolation at Interstage Split

RF output

+ Vcc-1+ BIAS-A

DE

LA

Y

LIN

E

Z

INV

ER

TE

R

+ BIAS-B

+ Vcc-1

DE

LA

Y

LIN

E

RF output

+ BIAS-A

Z

INV

ER

TE

R

+ BIAS-B

NO ISOLATION WITH ISOLATION

19

PCS 1ST Generation Switched Doherty

• 1120 x 1200 um2

• 6480 um2 final

• 550 um2 driver

• external 2nd

harmonic tuning

20

PCS 2ND Generation Switched Doherty

• 1170 x 1230 um2

• 6480 um2 final

• 550 um2 driver

• internal 2nd

harmonic tuning

21

Cellular 2ND Generation Switched Doherty

• 1120 x 1470 um2

• 6480 um2 final

• 550 um2 driver

• internal 2nd

harmonic tuning

22

FISHBONE BASE Geometry for Low CBC

• 75% of STANDARD CELL CBC

• 57% of HAIRPIN CELL Rb’

• SOA is 2X HAIRPIN CELL

• >1 dB gain increase

• >2 % ha increase

23

Low Inductance Base Manifold

LO

W

Zo L

INE

LO

W

Zo L

INE

Large base LB ± D LB Low LB ± D LB Low LB ± D LB

EQ

UIV

AL

EN

T

• Lateral manifold contributes to LB

• A low Zo transmission line can reduce LB

• This is realized with METAL-2 / BCB / METAL-1 stack

• Increased shunt capacitance is parasitic result

• Lumped equivalent model is convenient

24

Low Interconnect L from Low Zo Lines Z

o (

)

L (

nH

/mm

)

C (

pF

/mm

)

WIDTH (mm) WIDTH (mm)

INCREMENTAL L and C

100 um GaAs

100 um GaAs

1.3 um BCB

1.3 um BCB

CHARACTERISTIC Zo

100 um GaAs

1.3 um BCB

25

Low Zo Base Manifold - PCS Band

LOW POWER CELLS HIGH POWER CELLS

26

Low Zo Base Manifold - Cellular Band

LOW POWER

CELLS

HIGH POWER CELLS

27

Improved Inductors

Split Line Spiral

Single Layer

Broadside Coupled

Split Line Spiral

• Standard overlay increases L but looses Q

• Split and split-overlay increase Q

• Split singles loose area efficiency

• Split-overlay and hybrids are the best overall for good Q with area efficiency

28

Cellular CDMA Performance

29

PCS CDMA Performance

30

UMTS Cellular WCDMA (Rel.99)

31

UMTS PCS WCDMA (Rel.99)

32

UMTS Cellular WCDMA (HSDPA)

33

UMTS PCS WCDMA (HSDPA)

34

Improvement: Tristate Switched Doherty

• Tristate (2-bit) power control.

• Build on switched Doherty (2-state) core

• No Vref needed -- PA operates directly from Vbatt.

• Enabled with logic interface (< 100uA control)

• Back compatible into standard sockets Vref pin is replaced by “ENABLE” logic input.

• Quiescent currents: – 6 mA ! ultra low power mode,

– 25 mA low power mode, and

– 78 mA high power mode.

35

Approach

• Switched Doherty PA core in HBT

• VREF elimination with pHEMT current sources for HBT bias circuits

• Low current logic pHEMT

• RF switch in pHEMT

BiHEMT process enables integrated solution:

36

BiHEMT: Co-integration of HBT and pHEMT

37

Tristate PA Module with pHEMT and HBT Chips

38

HBT PA Size Reduced from Original Switched Doherty

• Builds on original architecture

• HBT PA area is substantially reduced due to

removal of complex bias and control circuitry

• Type-1 or type-6 current mirrors are designed

to be driven by the Bias-Control chip

TRISTATE HBT PA

ORIGINAL SWITCHED DOHERTY

39

Switched Doherty PA Core (2 state)

RF output

RF input

BASE BIAS-1

BASE BIAS-2

+ Vreg

+ Vcc

+ Vreg

Hi/Lo Step

BASE BIAS-2A

+ Vreg

DE

LA

Y

LIN

E

Z

INV

ER

TE

R

40

Tristate Switched Doherty PA

RF output

RF input-1

BASE BIAS-1

BASE BIAS-2

+ Vcc

V-Mode-1

BASE BIAS-2A

DE

LA

Y

LIN

E

Z

INV

ER

TE

R

BASE BIAS-ULP

+ V_enable

(Vreg)

V Mode-2

+ V_enable

(Vreg)

+ V_enable

(Vreg)

+ V_enable

(Vreg)

RF input-2

V Mode-2

41

Ultra-Low Power Mode

RF output

Z

INV

ER

TE

R

BASE BIAS-ULP

+ V_enable

(Vreg)

V Mode-2

RF input-2

RF input-1

BASE BIAS-1

BASE BIAS-2

+ Vcc

V-Mode-1

BASE BIAS-2A

DE

LA

Y

LIN

E

+ V_enable

(Vreg)

+ V_enable

(Vreg)

+ V_enable

(Vreg)

V Mode-2

OFFOFF

OFFOFF

OFF

42

Simplified View of RF Loading in Tristate PA

2-state

Tristate

• Switched Doherty 2-state core

• Ultra-low power mode uses

load from low power mode

• RF input switch drives single

cell in ultra-low mode

43

Separate pHEMT and HBT Chips

pHEMT BIAS / CONTROL HBT POWER AMPLIFIER

44

Bias Control PA Interface

45

E/D pHEMT Bias Control with HBT PA

+ VBATT

I2B REF

Vbe ULP REF

IULP mirror

Vbe 2A REF

I2A mirror

Vbe 1 REF

I1 mirror

I2A REFI1 REF

MODE (2)

MODE (1)

ENABLE

InGaP HBT PA Bias Mirrors

E/D pHEMT

Bias Control

with

RF Input Switch

RF IN

OUT-2

OUT-1

Vbe 2B REF

I2B mirrorVbias

(to HBT)

IULP REF

46

Standard HBT Bias Reference Circuits

VREF required

in each case

47

Elimination of VREF

TYPE-I BIAS MIRROR

REFERENCE CIRCUITS

• Current density is mirrored

in RF (biased) device

• I REF set by (V REF – Vbe)/RSENSE

• Precise control of VREF required

• Low ZSOURCE requires high

I MIRROR (and high I REF)

• Current density is mirrored

in RF (biased) device

• I REF set by independent of V REF

by current source

• Low Z SOURCE is easily obtained

since current flows from Vcc (V BAT)

48

Current Sources for Bias Circuits

• pHEMT I MAX is well behaved (epi dependent)

• s < 7% (3s = 20%)

• Geometry scaled to set current

=

D

S

D m

od

e

I REF

IG

49

IG Pull-up for Imax Operation of Reference FET

• IG < 1 mA

• IG is dependent on Idss (a wide distribution)

• s = 16% (3s = 48%)

• Tight control of IG is not important

D

D m

od

eD

mo

de

SD

mo

de

D m

od

e

IG = =

50

PA Enable

• VREF PIN used

• Logic interface

• VREF not needed

51

High Mode Quiescent Current

0.0

10.0

20.0

30.0

40.0

50.0

60.0

70.0

80.0

90.0

100.0

-10 30 90 -10 30 90 -10 30 90 -10 30 90 -10 30 90

2.80 3.15 3.50 3.85 4.20

2.80

3.15

3.50

3.85

4.20

SN (All) Vmode1 (V) 0.30 Vmode2 (V) 0.30

I_total (mA)

Vcc1, Vbias, Venable (V) Temp (C)

Vbatt-2 (V)

52

Low Mode Quiescent Current

0.0

5.0

10.0

15.0

20.0

25.0

30.0

35.0

-10 30 90 -10 30 90 -10 30 90 -10 30 90 -10 30 90

2.80 3.15 3.50 3.85 4.20

2.80

3.15

3.50

3.85

4.20

SN (All) Vmode1 (V) 3.00 Vmode2 (V) 0.30

I_total (mA)

Vcc1, Vbias, Venable (V) Temp (C)

Vbatt-2 (V)

53

Ultra-Low Mode Quiescent Current

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

-10 30 90 -10 30 90 -10 30 90 -10 30 90 -10 30 90

2.80 3.15 3.50 3.85 4.20

2.80

3.15

3.50

3.85

4.20

SN (All) Vmode1 (V) 3.00 Vmode2 (V) 3.00

I_total (mA)

Vcc1, Vbias, Venable (V) Temp (C)

Vbatt-2 (V)

54

Tristate Switched Doherty PA Data

• Switched Doherty performance

extended to ultra-low power mode

• Quiescent current typically below

6 mA in ultra-low mode

• Ultra-low mode supports up to

+12 dBm with -40 dBc ACPR

55

BiHEMT Tristate Switched Doherty

1st GENERATION SWITCHED

DOHERTY CORE

2nd GENERATION

SWITCHED DOHERTY

CORE

56

Conclusion

• Switched Doherty PAs have been realized in both PCS and Cellular bands for linear operation.

• Power efficiency and linearity are quite good in both high and low power operation.

• Basic switched Doherty architecture has been extended to Tristate operation with extremely low quiescent current in the lowest power mode

• BiHEMT process enables integration of pHEMT and HBT circuitry in Tristate PA

• Several techniques to improve performance have also been presented:

– A new HBT geometry provides reduced CBC

– Use of low Zo interconnect structures to reduce inductance in base feed manifold

– Use of composite split-line and overlay (broadside coupled) inductors for better area efficiency and good Q

• CDMA talk-time is significantly increased.

57

Acknowledgements

Yulung Tang

Tarun Juneja

Brian MCNamara

Tim Kramer

Marla Hammond

Jeff Damm

Eric Reavis