Surfliner: Distortion-less Electrical Signaling for Speed of Light On- chip Communication Hongyu...
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Transcript of Surfliner: Distortion-less Electrical Signaling for Speed of Light On- chip Communication Hongyu...
Surfliner: Distortion-less Electrical Signaling for Speed of Light On-chip CommunicationHongyu Chen, Rui Shi, Chung-Kuan Cheng
Computer Science and EngineeringUniversity of California, San Diego
David M. HarrisHarvey Mudd College
Outline• Introduction• Surfliner
• Overview• Theory• Implementation• Simulation Results
• Applications• Conclusions
Introduction• On-chip Global Interconnect trend
• Major Concerns: Speed, Power, Cost
0
40
80
120
160
200
180 150 130 100 90 80 70 65 57 50Process Technology Node (nm)
Dela
y (p
s)
1mm Global I nterconnect with Scattering(source: I TRS Roadmap 2004)
FO4 I nverter Delay (Estimated by0.36*Ldraw)
1mm distortionless Transmission Line (Speedof Light)
Introduction• ITRS roadmap: Wall of Global Interconnect
• Delay (Speed of Light 5ps/mm)• Power Density (> ½)• Clock Skew:Variations (5GHz)
Wire optimization is getting harder and harder !
Introduction• Existing on-chip signaling techniques
• Pre-emphasis and Equalization, Dally, VLSI 1998
• Modulating to High-frequency domain; S. Wong, JSSC 2003.
• Non-linear transmission line; Afshari, Hajimiri, CICC 2003.
• Differential pair with discharging scheme, Horowitz, SVLSI 2003
Previous Works
Modulating to High-frequency domain; S. Wong, JSSC 2003.
Previous works
Differential pair with discharging scheme, Horowitz, SVLSI 2003
Surfliner - Overview• Speed-of-the-light on-chip communication
• < 1/5 Delay of Traditional Wires• Low Power Consumption
• < 1/5 Power Consumption• Robust against process variations
• Short Latency• Insensitive to Feature Size
Surfliner - Theory
RΔl LΔlGΔl CΔl
RΔl LΔlGΔl CΔl …
i(z,t)
RΔl LΔl RΔl LΔl
Differential Lossy Transmission Line Surfliner
RΔl LΔlCΔl
RΔl LΔlCΔl …
i(z,t)
RΔl LΔl RΔl LΔl
Current loss through shunt capacitance Frequency dependent phase velocity (speed) and attenuation
Add shunt conductance to compensate current loss R/G = L/CFlat from DC Mode to Giga HzTelegraph Cable: O. Heaviside in 1887.
Theory (Telegrapher’s Equation)• Telegrapher’s equation:
),(),(),(
),(),(),(
tzGVdttzdVC
dztzdI
dttzdILtzRI
dztzdV
• Propagation Constant:
jCjGLjR ))((
• Wave Propagation: zjzeVzV 0)(
• Alpha and Beta corresponds to attenuation and phase velocity. Both are frequency dependant
Theory (Distortionless Line)• Set G=RC/L• Frequency Independent speed and attenuation:
LCCLR ,//
• Characteristic impedance: (pure resistive)
CLZ /0 • Phase Velocity (Speed of light in the media)
cLCv /1• Attenuation:
zZR
ezA 0)(
Digital Signal Response
Eye Diagram
• Injected 1.0V voltage falls to 365mv over a 2cm wire
120 stage, 2.1ps jitter
Speed, Power, Variations• Speed of Light: 5ps/mm or 50ps/cm• Power: 10mW at >GHz• Conductance variation = 10%, f=10MHz~1
0GHz• Phase velocity variation < 1%• Attenuation variation < 1%
Implementation• Add shunt conductance between differential w
ires
• Resistors realized by serpentine unsilicided poly, diffusion resistors, or high resistive metal
Simulation Results• Configuration of wires
• Characteristic Impedance (at 10GHz) : 39.915 Ohm
• Inductance: 0.22nH/mm Capacitance: 141fF/mm
• Attenuation: 253mv magnitude at receiver’s end (assuming 1V at sender’s end)
• Using Microstrip (free space above the wires): impedance can be improved to 52.8Ohm
Simulation Results (Settings)• Agilent ADS Momentum extract 4-port S-
parameters• HSpice: Transient analysis• Assume 1023 bit pseudo random bit
sequence (PRBS)• 15GHz clock• 10% of clock period transition slope for each
rising and falling edge
Simulation Results
4 Stages 120 Stages
Simulation ResultsJitter and silicon area usage
#Stages 4 10 20 40 80 120 160Jitter (ps) 27 9.5 5.4 4.2 3.9 2.1 2.08
Area (um2) 0.52 3.25 13.0 52 208 468 832
Power w/ different width and separation
(w, s) (um) (3,3) (4,4) (5,4) (10,5)Power (mW) 4.98 3.62 3.02 2.13
Attenuation 0.307 0.415 0.496 0.60
Applications of Surfliner1.Clock distributions
2. Data communications: Buses Between CPUs, DSPs, Memory Banks
Application of Surfliner3. High Performance Low Power Wafer Packaging
IC IC IC
Distortionless On-Wafer Transmission Lines for Data Communication and Clock Distributions
CoupledCapacitors
Differential Driver Sense-amps
Conclusions• Feasibility of Implementing Distortionless
Transmission Line for On-Chip Communication
• Advantages of Surfliner• Speed of Light• Low Power (independent with data rate)• High throughput
• Limitation of Surfliner• Require wide metal wires• Static power consumption
Conclusions• Applications
• Global data communication• High Speed Clock• Wafer Scale Packaging
• Future Directions• Explore the design space of wire configurations
and sender/receiver circuitry• Quantify the design trade-offs for surfliner• Innovative communication architectures