SuperI/O PC87351EB Reference Manual€¦ · 2.6 SOFTWARE CONFIGURATION ... • PC87351 hardware...
Transcript of SuperI/O PC87351EB Reference Manual€¦ · 2.6 SOFTWARE CONFIGURATION ... • PC87351 hardware...
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420521694-001
SuperI/OPC87351EB
Reference Manual
®
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SuperI/O
PC87351EBReference Manual
Part Number: 420521694-001
May 1998
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PRELIMINARY
iv
REVISION RECORD
REVISION RELEASE DATE SUMMARY OF CHANGES
1.0 March 1998 First release.
1.1 May 1998 Minor Changes.
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v
PREFACE
Thank you for your interest in National Semiconductor’s PC87351 SuperI/O device.
The PC87351 Evaluation Board (PC87351EB) is designed to demonstrate the basic I/O functions ofthe PC87351. It also demonstrates an implementation of the PC87351 on a low chip-count, low-costPCB.
This Reference Manual provides the information you need to get acquainted with the PC87351, andto develop your own applications.
We at National Semiconductor want you to make the fullest use of your PC87351EB. If you haveany questions, please contact your nearest Regional Marketing Office, as listed on the back cover.
PC, PS/2 are registered trademarks of International Business Machines Corporation.
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PC87351EB Reference Manual CONTENTS-vii
CONTENTS
Chapter 1 OVERVIEW
1.1 INTRODUCTION ....................................................................................................... 1-1
1.2 MANUAL ORGANIZATION ....................................................................................... 1-2
1.3 BOARD FEATURES.................................................................................................. 1-2
1.4 PHYSICAL DESCRIPTION OF BASE BOARD ......................................................... 1-4
1.5 PHYSICAL DESCRIPTION OF EXTENSION BOARD.............................................. 1-7
Chapter 2 INSTALLATION AND CONFIGURATION
2.1 INTRODUCTION ....................................................................................................... 2-1
2.2 UNPACKING ............................................................................................................. 2-2
2.3 SYSTEM REQUIREMENTS ...................................................................................... 2-2
2.4 SYSTEM INSTALLATION ......................................................................................... 2-4
2.5 HARDWARE CONFIGURATION............................................................................... 2-5
2.5.1 DIP Switch Setup ........................................................................................... 2-6
2.5.2 Base Board Jumper Setup ............................................................................ 2-6
JP2 ................................................................................................................ 2-6JP4 ................................................................................................................ 2-6
2.5.3 Extension Board Jumper Setup ..................................................................... 2-7
JP1-4, JP6-7, JP9 ......................................................................................... 2-7JP4 ................................................................................................................ 2-9JP5 ................................................................................................................ 2-9JP7 ................................................................................................................ 2-9JP8 ................................................................................................................ 2-9JP10 ............................................................................................................ 2-10JP11 ............................................................................................................ 2-10JP12 ............................................................................................................ 2-10VDD............................................................................................................. 2-10JP14 ............................................................................................................ 2-10VBAT ........................................................................................................... 2-11VSB ............................................................................................................. 2-11JP17 ............................................................................................................ 2-11JP18-23, 25 ................................................................................................. 2-11JP24 ............................................................................................................ 2-11
2.5.4 KBC Connection to the Motherboard ........................................................... 2-11
2.5.5 KBC Automatic Hardware Configuration ..................................................... 2-12
2.6 SOFTWARE CONFIGURATION ............................................................................. 2-12
2.6.1 Configuring the PC87351 to Work in Parallel IRQ Mode ............................. 2-12
Without the KBC.......................................................................................... 2-12
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CONTENTS-viii PC87351EB Reference Manual
With the KBC............................................................................................... 2-13
2.6.2 Easyreg Software Utility .............................................................................. 2-14
2.6.3 PC87351 Reset ........................................................................................... 2-14
2.6.4 Configuration Register Access .................................................................... 2-14
Chapter 3 THEORY OF OPERATION
3.1 INTRODUCTION ....................................................................................................... 3-1
3.2 STANDARD ISA BUS ADD-ON CONNECTOR ........................................................ 3-1
3.3 GLUE LOGIC............................................................................................................. 3-1
3.4 DEBUG RESET CIRCUIT ......................................................................................... 3-3
3.5 PC87351 CHIP .......................................................................................................... 3-3
3.6 BATTERY CIRCUIT .................................................................................................. 3-3
3.7 FDC ........................................................................................................................... 3-3
3.8 UART1 AND UART2 ................................................................................................. 3-4
3.9 INFRARED ................................................................................................................ 3-4
3.10 PARALLEL PORT ..................................................................................................... 3-5
3.11 FAN CONTROL CIRCUIT ......................................................................................... 3-5
3.12 ISP............................................................................................................................. 3-6
3.13 GPIO PORTS AND PME........................................................................................... 3-7
3.13.1 GPIO1 ........................................................................................................... 3-7
3.13.2 GPIO2 ........................................................................................................... 3-8
3.13.3 PME Connector ............................................................................................. 3-8
3.14 PS/2 KEYBOARD AND MOUSE CONNECTORS .................................................... 3-9
3.15 KBC CONNECTOR ................................................................................................... 3-9
3.16 TEST CONNECTORS............................................................................................. 3-10
Chapter 4 SPECIFICATIONS
4.1 INTRODUCTION ....................................................................................................... 4-1
4.2 PHYSICAL SPECIFICATIONS.................................................................................. 4-1
4.3 BASE BOARD CONNECTORS................................................................................ 4-1
4.3.1 SERIAL1 Connector, J1 ................................................................................ 4-2
4.3.2 SERIAL2 Connector, J2 ................................................................................ 4-2
4.3.3 KBC Connector, J4 ....................................................................................... 4-2
4.3.4 Mouse Connector, J6 ................................................................................... 4-3
4.3.5 KBD Connector, J7 ........................................................................................ 4-4
4.3.6 Standby Power Connector, J8 ....................................................................... 4-4
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PC87351EB Reference Manual CONTENTS-ix
4.3.7 FDC Connector, J10 ...................................................................................... 4-4
4.3.8 IRFE Connector, J12 ..................................................................................... 4-5
4.3.9 Parallel Port Connector, J13 .......................................................................... 4-6
4.3.10 ISA XT and AT Connectors, P1 and P2 ........................................................ 4-6
4.4 EXTENSION BOARD CONNECTORS...................................................................... 4-6
4.4.1 PME Connector, J1 ....................................................................................... 4-6
4.4.2 Fan Connector, J2 ......................................................................................... 4-7
4.4.3 GPIO2 Connector, J3 .................................................................................... 4-7
4.4.4 GPIO1 Connector, J4 .................................................................................... 4-7
4.4.5 ISP Connector, J10 ....................................................................................... 4-8
4.5 CURRENT REQUIREMENTS ................................................................................... 4-8
Appendix A BASE BOARD SCHEMATIC DIAGRAMS
Appendix B EXTENSION BOARD SCHEMATIC DIAGRAMS
Appendix C BILL OF MATERIALS
Appendix D PAL EQUATIONS
INDEX
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FIGURES-x PC87351EB Reference Manual
FIGURES
Figure 1-1. PC87351EB Features ............................................................................................ 1-4Figure 1-2. PC87351EB Base Board Component-Side Layout ............................................... 1-5Figure 1-3. PC87351EB Base Board Print-Side Layout .......................................................... 1-6Figure 1-4. PC87351EB Extension Board Component-Side Layout ........................................ 1-7Figure 1-5. PC87351EB Extension Board Print-Side Layout ................................................... 1-8Figure 2-1. PC87351 Chip Evaluation System ........................................................................ 2-1Figure 3-1. ISA Bus and X-Bus Data Architecture ................................................................... 3-2Figure 3-2. Fan Control Circuit ................................................................................................. 3-6Figure 3-3. ISP Block ............................................................................................................... 3-7Figure 3-4. GPIO1 Circuit ........................................................................................................ 3-8
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PC87351EB Reference Manual TABLES-xi
TABLESTable 2-1. Jumper Default Settings on Base Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4Table 2-2. Jumper Default Settings on Extension Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4Table 2-3. Base Address Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6Table 3-1. PME1/RING Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8Table 3-2. PME2/SUSP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9Table 4-1. PC87351EB Connector List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1Table 4-2. SERIAL1 Connector, J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2Table 4-3. SERIAL2 Connector, J2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2Table 4-4. KBC Connector, J4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2Table 4-5. Mouse Connector, J6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3Table 4-6. KBD Connector, J7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4Table 4-7. Standby Power Connector, J8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4Table 4-8. FDC Connector, J10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4Table 4-9. IRFE Connector, J12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5Table 4-10. Parallel Port Connector, J13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6Table 4-11. PME Connector, J1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6Table 4-12. Fan Connector, J2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7Table 4-13. GPIO2 Connector, J3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7Table 4-14. GPIO1 Connector, J4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7Table 4-15. ISP Connector, J10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8Table 4-16. Max Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
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PC87351EB Reference Manual OVERVIEW 1-1
Chapter 1
OVERVIEW
1.1 INTRODUCTION
The PC87351EB is an evaluation board for the PC87351 SuperI/O chip. Thischip integrates the traditional I/O devices of a PC motherboard with additionalPlug and Play functionality, Infrared, Serial IRQ and Fan support.
The PC87351EB comprises a base board, and an extension board on whichthe PC87351 SuperI/O chip is mounted.
The PC87351EB enables you to evaluate the following functions, or modules,of the PC87351 in their natural environment:
• ISA interface
• PC87351 external connections
• PC87351 hardware configuration
• Floppy Disk Controller (FDC), up to 1 MB/sec
• 16550 serial port 1
• Enhanced serial port 2, software compatible with 16550
• Infrared (IR) port (supporting IrDA, Sharp, TV Remote)
• Parallel Port, IEEE 1284 compatible (including ECP/EPP)
• Keyboard Controller (KBC) compatible with 8042
• PS/2 mouse and PS/2 keyboard support
• Two General Purpose I/O (GPIO) ports. GPIO1 with 8 bits, and GPIO2 with3 bits
• System wake-up events detection for energy-saving system
• Two fan speed controls
• Motherboard Plug and Play interface
• VSB standby power pin to minimize battery drainage
Certain features of the PC87351 chip are not supported directly on-board.Figure 2-1 shows the working environment.
Advanced Chip Features
The PC87351 chip supports some of the newest emerging standards in the PCworld:
• The Plug and Play standard, driven by Microsoft and Intel, allows a Plug andPlay BIOS, or an operating system, to automatically configure and resolveconflicts of I/O addresses, IRQs and DMA channels between ISA boards.
• The TV Remote standard enables you to support applications that eithersend signals to external devices, or receive signals from remote controls.
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1-2 OVERVIEW PC87351EB Reference Manual
1.2 MANUAL ORGANIZATION
This manual provides information for configuring the PC87351EB. It is orga-nized as follows:
Chapter 1 OVERVIEW - Describes the PC87351EB operating environment and features.
Chapter 2 INSTALLATION AND CONFIGURATION - Describes the system installation andconfiguration procedures.
Chapter 3 THEORY OF OPERATION - Provides a detailed description of the PC87351EBmodules, and describes operating principles, based on the schematics in Ap-pendix A.
Chapter 4 SPECIFICATIONS - Provides PC87351EB specifications and physical dimensions.
Appendix A BASE BOARD SCHEMATICS.
Appendix B EXTENSION BOARD SCHEMATICS.
Appendix C BILL OF MATERIALS.
Appendix D PAL EQUATIONS.
1.3 BOARD FEATURES
The PC87351EB includes the following features (see Figure 1-1):
• 128-pin PC87351 SuperI/O ChipThis device is assembled in a socket for easier upgrade and/or replacement.
• Clock Source48 MHz external clock oscillator.
• Two Data Switches74LVX3L384 data switches control the data flow from the PC87351 databus to the X-Bus, or the ISA bus.
• Serial Ports 1 and 2Each serial port has a 10-pin dual-row header and a low-cost RS-232 chip(three drivers and five receivers), DS14185.
• Infrared SupportA 9-pin D-type connector connects the infrared module of the PC87351 toan Infrared Front End Device (IRFE, National Semiconductor discrete module).
• Parallel PortA standard D-type male connector with National ECP terminations.
• Floppy Disk Controller (FDC)A 34-pin dual-row header connects the FDC block on the PC87351 to amaximum of two external Floppy Disk Drives.
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PC87351EB Reference Manual OVERVIEW 1-3
• Keyboard Controller (KBC)A 40-pin dual-row header connects the KBC module on the PC87351 tothe 8042 40-pin DIP socket on the motherboard. Two MINI-DIN 6-pin con-nectors connect the mouse and keyboard to the board.
• 3V battery for RAM backup of the PC87351.
• GPIO1A 10-pin dual-row header connects all GPIO1 signals to any user-definedexternal circuitry.
• GPIO2A 10-pin dual-row header connects all GPIO2 signals to any user-definedexternal circuitry.
• PMEA 10-pin dual-row header connects the multiplexed pins PME1/RING andPME2/SUSP to any user-defined external circuitry.
• FANA 2-pin header connects the fan control to an external fan via optional on-board circuitry.
• Standard AT-type ISA add-on edge connector.
• Voltage SupplyThe board operates at 5V, supplied by the ISA bus. The two DS14185 com-ponents, and the fan circuitry on the extension board, operate on +12Vand -12V from the ISA bus.
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1-4 OVERVIEW PC87351EB Reference Manual
Figure 1-1. PC87351EB Features
1.4 PHYSICAL DESCRIPTION OF BASE BOARD
The PC87351EB is designed to be mounted in a PC-AT slot. Figure 1-2 showsthe component side of the base board, and Figure 1-3 the print side.
MINI-DIN
74F
DS14185
OscDB25
FDC
KB
C C
onn 20*2
RSTSW
DB9
MINI-DIN
KeyboardMouse
SER12*5
Conn
Conn 17*2
74AC
48 MHzDS14185
SER22*5
Conn
PC87351+
3V
TQ32
ISA Bus
SA[0.15]
RXD[0..7]
DM
A
IRQ
SD[0..7]
SIOD[0..7]
BADDR
Control
InfraredPortConnector
ParallelPortConnector
KBC PRES
IRQ1
P12,17,20,21,22
PAL 22V10
BT1
Glue Logic
74LVX3L384
74LVX3L384
RSTSW74F
74AC
FPGA1032E
132
Reset
Conn2*5
GPIO2
Conn2*5
GPIO1
Conn2*5
PME
FAN
CIRCUIT
FAN2*1
Conn
GPIO16
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PC87351EB Reference Manual OVERVIEW 1-5
Figure 1-2. PC87351EB Base Board Component-Side Layout
P1J13
P2
RN1
C4R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R1 R2 R3 R4 R5 R6 R7 R8 R9R10
R11
R12
R13
R14
R15
R16
L3
L4
L5
L6
L1
L2U5
U10
C2C1
SW1
J12
R81
C6 C7 C8 C9 C10
C11
C12
C13
C14
C15
Y1
U8
C5
C18
C17
R30
R31
U7
R17
R18
U3
C3
U2U1
SW4
XU9
XU4
JP2
J2
J5
J1J10
JP1
XJ4E
XU6
J4
XJ4D
XJ4A
XJ4B
XJ4C
-+ +
BT1
J3
J8
J9J6
J7
JP3
J11
JP4
LD1
TP3
TP1
TP2
TP4
RN2
SW3
F2
XBT2
TP6
TP5R82
C16
XF1
SW2
A
nONCTL
nONCTL
nRINGnSW
= 0
= 1
13
----
32.768 KHz
48 MHz
RES
24 MHz
LED
0101
NY01
NY
PC87
317
KBC RTC FDC
PnP ISA
B. ADD.
1 0
CLK
48 M
Hz
VHEXT
NLEDEXTVVHEXT
NCEXTV
NC
X-DATA
980521682-002 REV
GND
SWITCH
INT
EXT
1
3020 19
10 9
29
10
19
9
2019
109
VCC
PC87317EB
1
151
34 33
2 1
30 29
2 1
1
21
4039
2423
2191
109
21
43
21
C18
C1A31
A1
2420
1513 12
105
1
10 9
2 1
155145135 150140130125
115
110
105
100
9590
85
75 70 65 60 55 50 45
3525
1530
2010
5
3V
ISARST
+
32.768 KHz
48MHz
IRQ 11 10
VDD
VDDGND
GND
VCC
7531
6420
GPIO2
GPIO17
75
53
3
66
44
22
11
00
STANDBY
1
MOUSE
KBD
PARIR
RST
FDC
APC
GPIO3
KBC
RTC
SER2SER1
23
CFG
0 0
1 1
01
BADDR
RES
1X
002E
015C
PnP MBD
01
BADDR
RESET CFG
1011 000
23
PC87307/8
1
10 01
32.7
68 K
Hz
CFG
CFG
GND
GND
GND
VCC
VCC
VCC
1
1
+
11
1
160121
120
81
80 41
401
2A
11
PC
8735
1EB
9805
2169
4-00
1
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1-6 OVERVIEW PC87351EB Reference Manual
Figure 1-3. PC87351EB Base Board Print-Side Layout
R65A
R64B
R34
C20
C54
C47
C50
C65
C63
C64
C44
C41
C24
C39
C36
C32
C34
C38
C37
C28
C26
C43
C19
C21
C30
C31
C23
C22
C57
C56
C59 C61
C60
C62
C55
R68
R57
R67
R60
R59
R62
R61
R79
R76
R77
R78
R33
R32
R41
S/N
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
C33
C49
C48
C52
C51
R36
R35
R38
R39
R37
R58
R75
C58
C40
C46
C45
C42
C25
C29
C27
C35
C81
C66
C67
C68
C69
C70
C71
C72
C73
C74
C75
C76
C77
C78
C79
C80
R40
R64A
R80
R84
R86
R83
R63B
R85
R74
R73
R56
R63A
R65B
R66A
R66B
R72A
R72B
R71A
R71B
R69A
R69B
R70B
R70A
SWIT
CHLED
29
2019
109
2019
109
3020 19
10 9
XU9
21
109
13
251496
+
VCC
VCC
VCC
GND
GND
GND
SER1 SER2
RTC
KBC
GPIO3
APC
FDC
RST
IR
PAR
KBD
MOUS
E
1
STAN
DBY
00
11
22
44
66
33
55
77GP
IO1
GPIO
2
0 2 4 6
1 3 5 7
VCC
GND
VCC
GND VDD
VDD
1011
IRQ
ISAR
ST
3V
510
2030
1525
35
45505560657075
8590
9510
010
511
011
5
125 130 140 150135 145 155
12
910
15
101213
1520
24
12
34
12
910
1 9 12
2324
3940
12
1
12
2930
1
2
3334
1 5 1
1
1
B1B3
1D1
D18
TP5
TP6
F2
SW3
RN2
TP4
TP2
TP1
TP3
LD1
JP4
J11
JP3
J7J6
J9
J8
J3
BT1
XJ4C
XJ4B
XJ4A
XJ4D
J4
XU6
XJ4E
JP1
J10
J1
J5
J2
JP2
SW1
SW4
Y1
RN1
SW2
P2
J13J12
P1
66
55
44
22
33
11
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PC87351EB Reference Manual OVERVIEW 1-7
1.5 PHYSICAL DESCRIPTION OF EXTENSION BOARD
The PC87351EB is designed to be mounted in a PC-AT slot. Figure 1-4 showsthe component side of the extension board, and Figure 1-5 the print side.
Figure 1-4. PC87351EB Extension Board Component-Side Layout
R2
J5
J10
U2
J3J4
J1
JP7
J2
JP22
JP21
JP20
JP19
JP18
JP23
JP25
JP11JP10
JP4
U8
U1
U3
U5
JP1JP2
JP6JP3
JP9
R1
RP1
TP1
TP2
TP3TP4
JP17
LD2
U4U6
SW1
C1
JP5
JP12
JP24
JP8
XU7
JP14
J7
JP13
J6
LD3
J8
J9
LD1
U1 PINS 37-43*
EXT
JP14JP12
JP11-PNFJP8
JP5
JP10-GPIO1 FROMJP7
JP4
JP9JP6
JP3JP2
1487
8 432
1
1
1 1
1
1
1
126
128
127
105
104
103
100
102
101
67 66 65
63
64
62
39
40
41
37
38
3632
150 145 140 135 130 125
7570656055504035
3025
2015
105
1
PIRQSIRQ*
P12
GPIO21*
P17
GPIO22*
IRQ9
GPIO14*
GPIO15*
IRQ11
P21*
PNF
HIGH*
1998
REV980521694-001
PC87351EB
U1/115
LOWDOWN
UPOUT
IRSL2
CNSC
U1 PINS 112-119
2 1FANOUTGND
FAN
VDD
PMEGPIO2
GPIO1GND
VDDVSB
PWUREQVSB
VDDGND
BADDR15C
2E
SPARE
2 2 2 2 2
1 1 1 1 11
18 7 6 5 4 3 2 1 3 2 1ISPDIS
ISPEN
2
5 33 2 1
1
P20*PP*
33
22
11
22
21
11
CONNECT*FAN0* IRQ*
UART2*
7 5 3 1
6 4 2 01
2 0
108 6 4 2
9 7 5 3 1
VSB
VBAT
OUTFDC
INGPIO20
BYPASSFAN1
DOWNDOWN
UPUP
OUTIN
GPIOGPIO
JUMPER
JUMPERJUMPER
1-23-45-67-8
JP1JUMPER
P12
P12P17
P17
IRRX2IRRX2
PNF
FANOUT1FANOUT0
GPIO17
22
22
24
44
44
66
66
68
88
88
77
77
75
55
55
33
33
31
11
11
115110
105100
9590
85
9
21
1
1213
1213
5026100
76
755125
124
24
241312
11
1
1312
1
854 1
002
P20
P21
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1-8 OVERVIEW PC87351EB Reference Manual
Figure 1-5. PC87351EB Extension Board Print-Side Layout
R10
R11
C14
C3
C16
R12
R6
R5
C2
R4R7
R9
R13
R14
R15
C4 C5
C8
C7
C11
C10
C12
C6
C13
C15
R3
R8
C9
FAN
FANOUTGND
VDD
ISPD
IS
ISPE
N
14 87
1
12
9
8590
95105
110
11
11
13
33
33
55
55
57
77
77
88
88
86
66
66
44
44
42
22
22
1 3 5 7 9
2 4 6 810
0 21
0 2 4 6
1 3 5 7
11
12
22
11
22
33
11 2 3
3 5
2
1 2 3 1 2 3 4 5 6 7 811
1 1 1
1
1
2 2 2
2
2
GND
VDD
VSB
PWUR
EQVS
BVD
DGND
GPIO1
GPIO2
PME
1 2
110
1520
2530
3540
505560657075
125 130 135 140 145 150
2336
38 37
41
40
39
62
64
63
65
66 67
101 10
2
100
103
104
105
127
128
126
1
1
1
1 1
1
123
4 8
115
JP9
JP3
JP6
JP2
JP1
U1
JP4
JP10
JP11
JP25
JP23
JP18 JP
19
JP20
JP21
JP22
J2
JP7
J1J4
J3
J10
J5
RP1
TP1
TP2
TP3
TP4
JP17LD2
SW1
JP5
JP12
JP24
JP8
XU7
JP14
J7
JP13
J6
LD3
J8
J9
LD1
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PC87351EB Reference Manual INSTALLATION AND CONFIGURATION 2-1
Chapter 2
INSTALLATION AND CONFIGURATION
2.1 INTRODUCTION
The PC87351EB is an ISA add-in board for a desktop personal computer (PC).The board consists of two parts, a base board and an extension board contain-ing the PC87351 socket. The board can be connected to various external com-ponents, including: serial or PS/2 mouse, modem, keyboard, fan, Floppy DiskDrive (FDD), National Semiconductor’s Infrared Analog Front End (IRFE) mod-ule, printer, GPIO lines and wake-up events lines. Figure 2-1 shows the fullPC87351 chip evaluation system.
Figure 2-1. PC87351 Chip Evaluation System
PC Desktop Motherboard
PC87351EB
IEEE 1284
PS/2 Keyboard
FDD
SSER1 IRFE
SSER2 FDC
RSTSW
113
15
+
Switch Standby
PC87351
PS2 Mouse
Peripheral
KBC
LED
SupplyPower
PCMotherboard
AC
Module
Device1
ExtensionBoard
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2-2 INSTALLATION AND CONFIGURATION PC87351EB Reference Manual
2.2 UNPACKING
Verify that your PC87351EB package contains the following items1:
1. One PC87351EB (both base board and extension board).
2. One 3.5" floppy disk containing the easyreg configuration program.
3. One 3.5" floppy disk containing the FanDemo program.
4. PC87351 Datasheet.
5. Two Application Notes:Using the SuperI/O PC87351 for Fan Speed ControlExternal Circuit Support for Fan Speed Control.
6. This Reference Manual.
7. PC87351EB Release Letter.
8. One IRFE module and documentation.
9. One KBC cable.
10. Two IDC10 to DB9 cable adapters for the serial ports.
If any item is missing or damaged, contact your nearest Regional MarketingOffice, listed on the back cover of this manual.
2.3 SYSTEM REQUIREMENTS
To fully evaluate the PC87351EB, you need the following equipment:
1. Desktop PC
The PC87351 chip is evaluated on the PC87351EB via a PC-based evaluationsystem. The PC87351EB is installed in an ISA bus slot on the PC motherboard.
To evaluate the KBC module of the PC87351, the motherboard must have a dis-crete KBC chip in the DIP socket (DIP40), and you must connect the KBC cablefrom the PC87351 Base Board.
2. PS/2 Keyboard and Mouse
Connect the keyboard and mouse to the J7 and J6 connectors, respectively, onthe PC87351EB base board. Do not connect or disconnect PS/2 peripheralswhile system power is on.
1. The contents may vary according to the release. See the Release Letter for details.
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PC87351EB Reference Manual INSTALLATION AND CONFIGURATION 2-3
Note Due to keyboard controller ROM code dependency, the PS/2 keyboard connectorand mouse connectors may be swapped. If your keyboard does not respond, tryswapping the keyboard and mouse cables.
3. External RS-232 Compatible Peripheral Device
This device can be a serial mouse, modem, terminal, PC-to-PC serial connection,etc. The PC87351EB supports up to two RS-232 serial channels via standardconnectors. You can connect the devices to any of the two serial headers on thePC87351EB base board.
Note Use only the supplied cables (Type 2), to connect RS-232 compatible peripheraldevices.There are two industry standards for an IDC10-to-DB9 cable:
– Type 1 - Connections according to pin numbers
– Type 2 - Connections according to physical pin locations; used most wide-ly on new motherboards.
Using a Type 1 cable interferes with the functionality of the connection on thePC87351EB. For more details, see Appendix A, Sheet 8.
4. IrDA Compatible IRFE Module
The PC87351EB supports infrared channel communication via the J12 connec-tor on the PC87351EB base board, which interfaces with the IRFE. For more de-tails about the IRFE features, see the SuperI/O IRFE Reference Manual.
5. TV IR Remote Control Device (not supplied)
To activate the infrared functions of the PC87351EB, you need an external infra-red emitting and/or receiving device. This device can be any IrDA-compliant sys-tem: another PC, notebook computer, or printer with IR support, etc. You mayalso use a TV IR remote control device from any manufacturer. If the remotecontrol has a 38 KHz carrier frequency, you may be able to use the internal ana-log demodulator of the IRFE module to increase operating range.
6. External IEEE 1284 Compliant Peripheral Device
Connect this device (e.g., printer) to the J13 parallel port connector on thePC87351EB base board, using an IEEE 1284 printer cable. Using other types ofcable may lower performance.
7. External Floppy Disk Drive (FDD)
Connect an FDD to the J10 FDD header on the PC87351EB base board.
8. External Fan
Connect this device to the J1 Fan header on the PC87351EB extension board.
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2-4 INSTALLATION AND CONFIGURATION PC87351EB Reference Manual
2.4 SYSTEM INSTALLATION
To install your PC87351EB system, follow the step-by-step procedure below.
Note If you use the KBC, start with the software configuration, Section 2.6.1.
Warning To prevent damage, turn off the PC power supply before you start.
1. Verify the following PC87351EB settings:
a. Check that all jumpers are in their default positions, (see Tables 2-1 and 2-2).
Table 2-1. Jumper Default Settings on Base Board
Jumper Default Setting
JP2 1-2 (INT)
JP4 IN
Table 2-2. Jumper Default Settings on Extension Board
Jumper Default Setting
JP1 5-6 (P20)
JP2 7-8 (GPIO15)
JP3 1-2 (GPIO14)
JP4 IN (UART2)
JP5 UP (FAN0)
JP6 1-2 (GPIO22)
JP7 IN (IRQ)
JP8 UP (CONNECT)
JP9 1-2 (GPIO21)
JP10 OUT (U1 PINS 37-43)
JP11 OUT (P.P.)
JP12 DOWN (P21)
JP13 IN
JP14 DOWN (PIRQ) (Vertical Position)
VBAT IN
VSB IN
JP17 OUT (HIGH)
JP18 IN
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PC87351EB Reference Manual INSTALLATION AND CONFIGURATION 2-5
b. Set DIP Switch 1 according to the chip’s base address.
2. Install the PC87351EB in an empty ISA slot on the PC motherboard.
3. Connect all peripherals to the appropriate connectors on the PC87351EB.Verify the polarity of all connectors, as shown in Figure 2-1.
Caution Incorrect connections may cause irreversible damage to both the PC87351EBand motherboard. Pay particular attention to the KBC connections.
4. Turn the PC power supply on.
2.5 HARDWARE CONFIGURATION
This section describes the settings of the DIP switch and jumpers, as well asthe KBC cable connection.
Note To set up the PC87351EB for a specific application, you must set the DIPswitch for the required base address, and the jumpers for the required config-uration (Section 2.5.1), and program the PC87351 configuration registers(Section 2.6). For further details, see the PC87351 Datasheet.
JP19 IN
JP20 IN
JP21 IN
JP22 IN
JP23 IN
JP24 UP (ISPEN)
JP25 IN
Table 2-2. Jumper Default Settings on Extension Board (Continued)
Jumper Default Setting
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2-6 INSTALLATION AND CONFIGURATION PC87351EB Reference Manual
2.5.1 DIP Switch Setup
A DIP switch on the Extension Board, SW1, enables you to configure thePC87351 base address. The BADDR (Base Address) pin of the PC87351 issensed during power-up reset. An external 10 KΩ resistor is recommended topull this pin to VCC.
2.5.2 Base Board Jumper Setup
Two base board jumpers (JP2 and JP4) and 25 extension board jumpers (JP1to JP25) enable you to customize the PC87351EB to your needs.
For details on the base board jumpers, see Appendix A Sheet 4.
JP2 JP2 is located near the STANDBY connector, J8. It selects the source for thechip standby power pin, VSB.
JP4 JP4 is located near the manual reset switch, (SW4). It enables you to usemotherboards that assert the ISA reset signal when you perform a system softreset (<Ctrl><Alt><Delete>). In its default state, IN, it enables both ISA andmanual reset.
If you remove this jumper, the chip does not receive the power-on reset signalfrom the ISA bus. Before you address any of its registers, press the SW4 resetswitch to reset the chip manually. For further details, see Section 2.6.
Table 2-3. Base Address Configuration
BADDR SW1Position
Index Address Data Address Plug and Play Configuration Type
UP 0x015C R/W 0x015D R/W PnP motherboard - wake up in Config state
DOWN 0x002E R/W 0x002F R/W PnP motherboard - wake up in Config state
JP2 Description
1-2 (INT, default) On-board VCC
2-3 (EXT) Off-board J8
JP4 Description
IN (default) ISA reset is connected
OUT ISA reset is not connected
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PC87351EB Reference Manual INSTALLATION AND CONFIGURATION 2-7
2.5.3 Extension Board Jumper Setup
For details on the extension board jumpers, see the schematics in Appendix B.
JP1-4, JP6-7,JP9
JP1-4, JP6-7 and JP9 route, or control the routing of, some of the multiplexedpins of the PC87351 chip. The SIOCF2 and SIOCF3 registers, of the PC87351chip, determine the functions of these pins. For a description of these jumperssettings, and the configuration of the PC87351 registers, see the table below.
To avoid contention, keep to the following rules:
1. Do not use more than one jumper for a function.
2. To change configuration, perform the following steps:
a. Pull out all the above jumpers.
b. Configure the SIOCF2 and SIOCF3 registers according to the table below.
c. Insert the jumpers according to the table below.
Signals JP1 JP2 JP3 JP4 JP6 JP7 JP9
GPIO10-13GPIO16
OUT
SIOCF3,bit 0=0
OUT
SIOCF2,bit 0=0
GPIO14
1-2
SIOCF2,bits 2-1=00orbits 2-0=011
GPIO15
7-8
SIOCF2,bits 4-3=00orbits 4-3,0=011
GPIO173-4
SIOCF2,bits 6-5=00
GPIO211-2
SIOCF3,bits 2-1=00
GPIO221-2
SIOCF3,bits 4-3=00
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2-8 INSTALLATION AND CONFIGURATION PC87351EB Reference Manual
IRQ4-7IRQ12
IN
SIOCF2,bit 0=1
IRQ95-6
SIOCF2,bits 2-0=011
IRQ11
1-2
SIOCF2,bits 4-3,0=010
"Hot Key"(P12)
7-8
SIOCF2,bits 6-5=10
3-4
SIOCF2,bits 4-3=10
5-6
SIOCF3,bits 2-1=10
KBC Lock(P17)
5-6
SIOCF2,bits 4-3=11
3-4
SIOCF2,bits 2-1=11
7-8
SIOCF3,bits 4-3=11
KBRST(P20)
5-6
SIOCF2,bits 6-5=01
PNF(in PPMmode)
1-2
SIOCF2,bits 6-5 =11
1-2
SIOCF3,bits 8-7 =11
IRRX2IRSL0
7-8
SIOCF2,bits 2-1=10
5-6
SIOCF3,bits 4-3=10
FANOUT03-4
SIOCF3,bits 2-1=01
FANOUT13-4
SIOCF3,bits 4-3=01
UART2IN
SIOCF3,bit 0=1
Signals JP1 JP2 JP3 JP4 JP6 JP7 JP9
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PC87351EB Reference Manual INSTALLATION AND CONFIGURATION 2-9
JP4 JP4 controls the state of the electronic switch U4. This switch routes pins112-115 and 117-120 of the PC87351 chip to the PC87351EB. Set up JP4 ac-cording to SIOCF3 bit 0, which determines the function of these pins.
Note To avoid contention when JP10 is IN, make sure that GPIO1 connector (J4 onextension board) is not connected to external signals while JP4 and SIOCF3 bit0 are configured to UART2 mode, or while configuring JP4 and SIOCF3 bit 0.
JP5 JP5 routes either the FAN0, or FAN1, signal from the PC87351 chip to theFAN connector (J2).
JP7 JP7 controls the state of the electronic switch U6. This switch routes pins 37-40 and 43 of the PC87351 chip to the PC87351EB board. JP7 should be setupaccording to SIOCF2 bit 0 which determines the above pins function. See tablebelow.
Note To avoid contention when JP10 is OUT, make sure that GPIO1 connector (J4on extension board) is not connected to external signals while JP7 andSIOCF2 bit 0 are configured to IRQ mode, or while configuring JP7 andSIOCF2 bit 0.
JP8 To work with DC fans, the PC87351 chip requires an external circuit to inter-face with the fan. For a fan that does not need an external circuit, you canconnect the fan directly to the PC87351 chip.
JP4 SIOCF3, Bit 0Function
(PC8735 Pins 112-115 and 117-120)
IN (Default) 1 UART2
OUT 0 GPIO10-16
JP5 Selected Fan
UP FAN0
DOWN FAN1
JP7 SIOCF2, Bit 0Function
(PC87351 Pins 37-40 and 43)
IN (Default) 1 IRQ4-7,12
OUT 0 GPIO10-13, 16
JP8 Description
UP The fan is connected to the Fan Control circuit
DOWN The fan is connected directly to the PC87351 chip
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2-10 INSTALLATION AND CONFIGURATION PC87351EB Reference Manual
JP10 JP10 selects one of two groups of pins of the PC87351 chip to connect to theGPIO1 connector (GPIO10-GPIO16).
JP11 In PPM mode, JP11 indicates to the PC87351 chip the type of device connect-ed to J13 on the base board. Set this jumper as shown below, otherwise re-sults are undefined.
JP12 JP12 routes the multiplexed pin 98, of the PC87351 chip, either to the GPIO2connector (J3 on the extension board) or to the base board. Set this jumperaccording to the function of this pin, which is determined by SIOCF2, bit 7.
VDD VDD is used only to measure the chip current, and should always be inserted.Do not power-up the board unless this jumper, or an amperemeter, is con-nected.
JP14 JP14 routes the multiplexed pins 34, 35 of the PC87351 chip. Set the jumperaccording to SIOCF2 register of the PC351, bit 0, as shown below.
JP10 Selected Pins of the PC87351
IN 112-115, 117-120
OUT 37-43
JP11 Type of Device Connected to J13
IN Floppy Disk
OUT Parallel Device
JP12 SIOCF2, bit 7 Function (PC87351 Pin 68)
UP 0 GPIO20
DOWN 1 GA20 (P21)
VDD Jumper Description
IN Normal operating mode
OUT Illegal, unless replaced by an amperemeter
JP14 SIOCF2, Bit 0 PC87351 Pin 34 PC87351 Pin 35 Mode of Operation
UP 0 PCICLK SERIRQ SIRQ
DOWN 1 IRQ1 IRQ3 Parallel IRQs
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PC87351EB Reference Manual INSTALLATION AND CONFIGURATION 2-11
VBAT VBAT is used only to measure battery current to the extension board andshould always be inserted.
VSB VSB is used only to measure Stand By voltage current to the extension board,and should always be inserted.
JP17 JP17 selects the IRSL2 source, or polarity. IRSL2 selects the IRFE mode of op-eration.
For more information about the IRFE modes, see the IRFE documentation.
JP18-23, 25 JP18-23, 25 are spare.
JP24 JP24 enables, or disables, the ISP. It is used only for development purposes.Always set this jumper in the high position.
2.5.4 KBC Connection to the Motherboard
The KBC module is connected directly to the motherboard via a custom-madeflat cable that is supplied with the PC87351EB. See Figure 2-1 and AppendixA, Sheet 13.
VBAT Jumper Description
IN Normal operating mode
OUT Illegal, unless replaced by an amperemeter
VSB Jumper Description
IN Normal operating mode
OUT Illegal, unless replaced by an amperemeter
JP17 IRSL2 Mode of Operation
UP GPIO13 of PC87351 chip
OUT 1 TV Remote
DOWN 0 DATA
JP24 CPLD Outputs
HIGH ACTIVE (ISP Enabled)
DOWN FLOAT (ISP Disable)
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2-12 INSTALLATION AND CONFIGURATION PC87351EB Reference Manual
To connect the KBC to the 40-pin DIP socket on the motherboard keyboardcontroller chip:
1. Remove the original 8042 chip (or equivalent) and replace it with a 40-pinDIP socket (not supplied).
2. Connect J4 to the socket using only the 40-pin cable provided.
3. Connect the 40-pin cable:Pin 1 (brown) on the narrow connector corresponds to pin 1 of J4 on thebase board.Pin 1 on the other end of the 40-pin cable, is connected to pin 1 of the DIPsocket on the motherboard.
Caution Incorrect connections may cause irreversible damage to your PC87351EB andmotherboard.
2.5.5 KBC Automatic Hardware Configuration
The PC87351EB has an automatic hardware configuration capability. Assum-ing that you have connected the KBC cable correctly and securely (see Figure2-1), it detects the presence of a cable by sensing the VCC pin of the mother-board KBC socket. This is accomplished by means of a PAL input, KBCPRES.For more details, see Appendix D and to Appendix A, Sheet 4 and Sheet 13.
2.6 SOFTWARE CONFIGURATION
2.6.1 Configuring the PC87351 to Work in Parallel IRQ Mode
The PC87351EB supports Parallel IRQ mode only. The configuration processfor this mode depends on whether the KBC is used, or not.
Without theKBC
To configure the PC87351 chip for Parallel IRQ mode if you are not using theKBC:
From your prompt line run:
debug- o BASE ADDRESS 22- o BASE ADDRESS+1 a0
Where BASE ADDRESSrefers to the base address of the chip (either 2E or15C).For more details on the base address, see Table 2-3.
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PC87351EB Reference Manual INSTALLATION AND CONFIGURATION 2-13
With the KBC If you are using the KBC, perform the following steps before the hardware in-stallation (an example follows the explanation):
1. Edit a batch file that includes the following lines:
o BASE ADDRESS 23o BASE ADDRESSS+1 1o BASE ADDRESS 7o BASE ADDRESS+1 7o BASE ADDRESS 60o BASE ADDRESS+1 GPIO1_HIGH_ADDRESSo BASE ADDRESS 61o BASE ADDRESS+1 GPIO1_LOW_ADDRESSo BASE ADDRESS 30o BASE ADDRESS+1 1o BASE ADDRESS f0o BASE ADDRESS+1 16o BASE ADDRESS f1o BASE ADDRESS+1 5o GPIO1_ADDRESS 0o BASE ADDRESS 22o BASE ADDRESS+1 a0q
GPIO1_HIGH_ADDRESS refers to the MSB of the GPIO1 address.
GPIO1_LOW_ADDRESS refers to the LSB of the GPIO1 address.
GPIO1_ADDRESS refers to the GPIO1 address which consists ofGPIO1_HIGH_ADDRESSand GPIO1_LOW_ADDRESS.
2. At the beginning of your autoexec.bat file, add the following line:
debug < [path]/file_name
Example The PC87351 chip base address is 15C, and the GPIO1 address is configuredto 200h. The batch file, 351config.bat , is in the root directory.
The first line of the autoexec.bat file is:
debug < 351config.bat
The 351config.bat file is:
o 15c 23o 15d 1o 15c 7o 15d 7o 15c 60o 15d 2o 15c 61o 15d 0o 15c 30o 15d 1o 15c f0o 15d 16o 15c f1
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2-14 INSTALLATION AND CONFIGURATION PC87351EB Reference Manual
o 15d 5o 200 0o 15c 22o 15d a0q
2.6.2 Easyreg Software Utility
The advanced features of the PC87351 chip are enabled by software configu-ration. To facilitate this task, use the easyreg software utility supplied withthis package.
The easyreg Configuration Program is a DOS utility that enables you to viewand configure the major features of the chip, in particular the EnhancedUART, and Plug and Play features. Easyreg is a stand-alone, executable DOSfile (easyreg.exe ). For a detailed description, see the READMEfile on your flop-py disk.
2.6.3 PC87351 Reset
The chip must exit the reset cycle prior to accessing its registers. The reset isperformed automatically during each powerup, if the JP4 jumper on the baseboard is inserted (default). If not, you must manually reset the chip by press-ing the on-board reset switch, SW4, located near the bracket. After reset, youcan override the hardware configuration by programming the configurationregisters.
2.6.4 Configuration Register Access
In the Configuration state, the PC87351 Index and Data registers are deter-mined by the BADDR strap option (see Table 2-3). The location of the PC87351register set complies with the Plug and Play ISA Specification, Version 1.0a.
For more details, see the ISA Plug and Play Specifications, Rev. 1.0a. For detailedinformation on accessing the registers of the PC87351, see the PC87351Datasheet.
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PC87351EB Reference Manual THEORY OF OPERATION 3-1
Chapter 3
THEORY OF OPERATION
3.1 INTRODUCTION
This chapter describes the operation of the main circuit blocks of thePC87351EB, based on the schematics in Appendix A and Appendix B.
See Appendix A, Sheet 1, and Appendix B, Sheet 1, to verify if the revisionnumbers on your base and extension boards match those of the schematics. Ifyour board is a newer revision, contact your nearest National Semiconductorrepresentative for updated schematics. See the block diagram in Appendix A(Sheet 2) for a root-level representation of the base board design. This will helpyou locate the various modules described in this chapter.
Note Unless specified otherwise, all component references are to the components onthe base board.
3.2 STANDARD ISA BUS ADD-ON CONNECTOR
See Appendix A, Sheet 3 for a diagram of this connector.
This connector includes the AT gold-plated finger sub-connectors, P1 and P2.The connector layout corresponds to an ISA bus edge connector. To help youlocate the signals more easily, the connector is shown in its physical layoutposition. The power supply to the board comes from the ISA bus, and includes+5V and ±12V power supplies. Decoupling capacitors are placed on thesepower supplies to minimize the voltage ripple. The TC signal from the ISA busis filtered by R58 and C33.
3.3 GLUE LOGIC
See Appendix A, Sheet 4 for a diagram of this circuitry.
With the exception of the seven decoupling capacitors on the VDD net, thecomponents of this module are not required in the motherboard application.This circuit creates the correct environment for PC87351 evaluation on thePC87351EB by providing an interface between the on-chip KBC module andthe X-Bus, which is not available on the ISA bus.
Two data switches connect the PC87351 data bus to the system: U10 connectsto the ISA bus, and U5 to the X-Bus. Only the KBC module of the PC87351needs to be connected to the X-Bus. The PAL controls the U10 and U5 switch-es. See Figure 3-1.
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3-2 THEORY OF OPERATION PC87351EB Reference Manual
Figure 3-1. ISA Bus and X-Bus Data Architecture
Switch enabling is based on the ISA access address. The switches are con-trolled by two of the PAL U6 outputs, XENBL and ISAENBL.
The ISA switch, U10, is enabled for any read or write access from/to any Su-perI/O module located at any address, except the KBC legacy addresses: 60and 64.
The X-Bus switch, U5, is enabled for any read or write access from/to theKBC module, only when it is enabled in its legacy addresses, as describedabove.
One 22V10 PAL device, U6, and one 74ACTQ32, U7, are used in this block.The 74ACTQ32 decodes the high ISA address bits A12-A15, and provides thePAL with the CSIN signal that is active low when all the high address bits arezero. The PAL controls the data switches:
• The ISAENBL signal is active on all I/O cycles, except when the address is60, 64h (KBC legacy address spaces).
• The XENBL signal is active only on I/O cycles with address 60, 64h (KBClegacy address space).
KB
C C
onn. 20*2
74AC74LVX
PC87351
TQ32
SA[0..15]
RXD[0..7] SD[0..7]
SIOD[0..7]
KBCPRES
IRQ1
P12,17,20,21
PAL 22V10
Glue Logic
IOR
DIO
WR
AE
NISAENBLCSIN
XENBL
SA
[0..111]
SA
[12..15]
3L38474LVX3L384
ISA Bus
JUMPERS
U5 U6 U7 U10
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PC87351EB Reference Manual THEORY OF OPERATION 3-3
Jumpers on the extension board route P12,17,20,21 signals to the PC87351chip.
The PAL facilitates automatic hardware configuration for the KBC cable. Forfurther details, see Section 2.5.5 and Figure 2-1.
3.4 DEBUG RESET CIRCUIT
See Appendix A, Sheet 4 for a diagram of this circuit.
This circuit allows you to reset the chip, at any time, by pressing the SW4switch located near the bracket. It also allows you to disconnect the reset sig-nal from the ISA bus by removing the JP4 jumper. For a description of thisjumper, see Section 2.5.2. See also Section 2.6 for software configuration de-tails.
3.5 PC87351 CHIP
See Appendix B, Sheet 2, for a diagram of the PC87351 chip connections.
This block contains the PC87351 chip, U1 on the extension board. U1 inter-faces directly with the ISA bus, with the exceptions of the 8-bit data bus thatis connected by the U10 switch (Appendix A, Sheet 4) and IRQ1,3 which areconnected by JP14 jumper on the extension board (Appendix B, Sheets 2, 3).Other external elements, such as decoupling capacitors, pull-up and pull-down resistors are also required.
3.6 BATTERY CIRCUIT
This circuit includes a 3V lithium battery, CR2335, BT1. It serves to keep thewakeup events configuration valid when the system is powered off.
You do not need any external components to comply with the UL safety stan-dard; all the necessary protection circuitry is on-chip.
The decoupling capacitors, C31 and C11, on the extension board help preventnoise on the VBAT line. XBT2 is an optional socket for a smaller, CR2032 type,battery. The R82 resistor serves only for current measuring.
The VBAT jumper on the extension board enables you to measure the batterycurrent consumption of the PC87351 chip. This jumper should always be in-serted.
3.7 FDC
See Appendix A, Sheet 7 for a diagram of the FDC.
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3-4 THEORY OF OPERATION PC87351EB Reference Manual
You can connect the FDC of the PC87351 to a maximum of two Floppy DiskDrives via a 34-pin standard header, J10. Standard 1 KΩ pull-ups (RN2) areused on all input signals.
3.8 UART1 AND UART2
See Appendix A, Sheet 8 for a diagram of the UARTs.
Each serial port connector, J1 and J2, is a 10-pin dual-row header. ThePC87351 chip interfaces these connectors through two DS14185 devices, U1and U2, respectively. DS14185 is an RS-232 compliant 3-driver/5-receiverchip, manufactured by National Semiconductor. This chip uses the +5V and±12V power supplies, assuring the most cost-effective implementation andminimum chip count in PC desktop applications. A standard EMI filter circuitis provided for each port (R1-R8/C66-C73 and R9-R16/C74-C81).
Note The pinout matches the IDC10-to-DB9 adapter cable supplied with the pack-age. For further details, see Section 2.3.
The PC87351 chip’s wakeup module can sense the state of the RI1 and RI2 se-rial port inputs. This feature supports applications in which an external mo-dem ring signal wakes up the system. To keep these two inputs alive duringsystem power-off, the corresponding line receivers are separated from theDS14185 devices, powered from the standby power supply, and consume verylittle power. If your application does not implement the above feature, the U3line receiver can be omitted.
Note The standby voltage VSB on the extension board is referred to as VCCH on thebase board.
3.9 INFRARED
See Appendix A, Sheet 9 for a diagram of this module.
A 9-pin D-type female connector, J12, interfaces the PC87351 chip with thesupplied analog IRFE module. J12 is located on the bracket for easy access.
The serial resistor R34 (33 Ω) on the IRTX signal from the PC87351 protectsthe signal from transmission effects.
When the IRFE is not connected to the board, pull-up resistors R35, R38,R39, R37 and R36 (150 KΩ) assure legal logic levels for the IRRX1 input sig-nal. If your application implements the IRFE on the same motherboard so thatit is always present, omit these resistors.
The IRFE supports FIR, MIR, SIR and Sharp-IR protocols, as well as TV-remote with demodulation outside the PC87351. See Section 4.3.8 for theheader pinout. See also the IRFE documentation for a full description of itsfeatures.
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PC87351EB Reference Manual THEORY OF OPERATION 3-5
3.10 PARALLEL PORT
See Appendix A, Sheet 10, for a diagram of the parallel port.
The IEEE 1284 parallel port on the PC87351 is connected to a standard DB25connector, J13, on the board’s bracket via the ECP terminations.
The PC87351 can route the FDD signals to the parallel port connector. Thismeans that a FDD device can be connected to this DB25 connector. For thesetting for this option see the PC87351 Datasheet.
3.11 FAN CONTROL CIRCUIT
The PC87351 chip includes a fan control which supports two fans. ThePC87351 generates a PWM (Pulse Width Modulation) signal at the fan outputaccording to a predefined frequency and width. External circuitry is needed toconvert the 5V PWM output to the 12V logic level used by the fan.
There is one control circuit that can be connected either to Fan0 or to Fan1.The JP5 jumper on the extension board selects which fan is connected to thefan circuit.
JP8 on the extension board routes the fan control to the fan connector J2 onthe extension board. It selects either the output from the fan control circuit,or the direct output from the PC87351 chip. This enables the use of a fan thatcan be connected directly to the PWM signal.
Note When using a fan that connects directly to PWM, it is your responsibility tocomply with the PC87351 electrical specifications (see the PC87351 Datasheet).
Before using the fan, set JP6 or JP9 according the desired configuration. SeeSection 2.5.3 for more details. See Figure 3-2 for Fan Control Circuit Layout.
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3-6 THEORY OF OPERATION PC87351EB Reference Manual
Figure 3-2. Fan Control Circuit
For more details, see Appendix B, Sheet 4.
3.12 ISP
An ISP, U8 on the extension board, is used to enforce a low logic level on theIRQ1 signal during booting, thus enabling a proper setup of the keyboard inSIRQ mode. After booting, you must configure the PC87351 chip to toggle theGPIO16/IRQ12 pin and to work in a parallel IRQ mode. The ISP detects thetoggle and releases the IRQ1 signal.
For more information about the configuration of the PC87351 chip see Section 2.6.1.
The ISP device, a Lattice 1032E, is programmed by a PC parallel port connect-ed to a single-row 8-bit header, J10. In a regular mode, it is not necessary toprogram the ISP since it should be already programmed.
Seven jumpers are reserved for future implementations.
NDS9942
18Ω18Ω18Ω
FANOUT0FANOUT1
PC87351J2
U2
1KΩ10µF
JP8
JP5
12V
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PC87351EB Reference Manual THEORY OF OPERATION 3-7
Figure 3-3. ISP Block
For more details, see Appendix B, Sheet 3.
3.13 GPIO PORTS AND PME
See Appendix B, Sheet 4, for a diagram of the GPIO ports and the PME.
3.13.1 GPIO1
The GPIO1 port is connected to a dual-row, 10-pin header, J4 on the exten-sion board. GPIO1 has eight signals: GPIO10-GPIO17. Except for GPIO17, allthe signals are duplicated on the PC87351 chip to two sets of pins. To allowevaluation of each of the two sets, two bus changers U5, U3 on the extensionboard, are used as shown in Figure 3-4.
IRQ1IRQ3
IRQ15
10KVcc
10KVcc
10KVcc
10KVcc
10KVcc
10KVcc
10KVcc
JP18
JP21
JP20
JP19
JP23
JP25
JP22
ISPEN SDI SCLK MODE SDO
J10
ispLSI 1032E
U8
HEADER 8X1
SpareJumpers
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3-8 THEORY OF OPERATION PC87351EB Reference Manual
Figure 3-4. GPIO1 Circuit
For more details, see Appendix B, Sheet 4.
3.13.2 GPIO2
The GPIO2 port is accessible on a dual-row, 10-pin header, J3 on the exten-sion board. To use the port, set the jumpers JP12, JP6, JP9 on the extensionboard according to Section 2.5.3.
3.13.3 PME Connector
A dual-row, 10-pin header, J1 on the extension board connects the multi-plexed pins: PME1/RING and PME2/SUSP of the PC87351 chip.
Bits 0,2 of SIOCF4 register of the PC87351 chip, determine the functionalityof the pins as described in the two tables below:
Table 3-1. PME1/RING Pin
U3 74LVX3L383
A
B
U5 74LVX3L383
A
B
Set A [10-16]
PC87351
Set A [10-13]
Set B [10-16]Set B [10-13]
Set A [14-16]
Set B [14-16]
GP
IO1
5*2
GPIO1 [10-16]
10K
JP10
Bus Exchange
Bus Exchange
J4
C
C
SIOCF4, Bit 0 Function of PME1/ RING Pin
0 RING
1 PME1
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PC87351EB Reference Manual THEORY OF OPERATION 3-9
Table 3-2. PME2/SUSP Pin
The PME1, PME2 and RING signals are used as wake up events.
For more details see the PC87351 Datasheet.
3.14 PS/2 KEYBOARD AND MOUSE CONNECTORS
See Appendix A, Sheet 12 for a diagram of these connectors.
The PC87351 directly interfaces with a keyboard and a PS/2 type mouse. TheKBCLK and KBDAT, MCLK and MDAT signals are connected to the keyboardand mouse connectors, J7 and J6 (MINI-DIN 6-pin type). They are located atthe top of the board for easy access. A standard EMI filter circuit is provided(L1-6, C47-52). In a high-end system, you may also implement a protectioncircuit on the power pins of J7 and J6. See Sections 4.3.4 and 4.3.5 for con-nector pinout.
3.15 KBC CONNECTOR
See Appendix A, Sheet 13, for a diagram of this connector.
Only motherboards with a discrete KBC chip in the DIP socket can be used toevaluate the KBC module from the PC87351 on the PC87351EB.
You can connect the PC87351 KBC block to the motherboard via a 40-pinheader, J4. (See Section 4.3.3 for J4 pinout). Connect J4, located on the leftside of the board, with the supplied cable to the KBC socket on the mother-board. (See Section 2.5.4 for system installation procedures). Bear in mindthat you may have to replace the 8042 KBC chip, which must be a 40-pin DIPcomponent, with a 40-pin socket.
The KBC module uses two IRQ signals. IRQ1 is connected by the J4 connec-tor, pin 12. IRQ12, used by the PS/2 mouse, is connected directly to the ISAconnector.
Some of the GPIO lines on the original 8042 device are not available on thePC87351. Instead, pull-up resistors RN1 (1 KΩ, 9-resistor pack) are connectedto these pins to prevent them from floating. Pins P20 and P21 are pulled-upby resistors R78 and R77 (10 KΩ). These two signals are open drain, and areused as the GATEA20 and the RESET signals from the KBC.
SIOCF4, Bit 2 Function of PME2/ SUSP Pin
0 SUSP
1 PME2
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3-10 THEORY OF OPERATION PC87351EB Reference Manual
3.16 TEST CONNECTORS
See Appendix B, Sheet 2 for a diagram of the test connectors.
Connectors XJ4 (A, B, C and D) are used to mount the extension board. Allthe PC87351 pins are accessible for testing on XJ4 connector pins. The XJ4Econnector carries the 12V voltage for the Fan circuit from the base board tothe extension board.
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PC87351EB Reference Manual SPECIFICATIONS 4-1
Chapter 4
SPECIFICATIONS
4.1 INTRODUCTION
The PC87351EB is designed to be mounted in a PC-AT slot.
4.2 PHYSICAL SPECIFICATIONS
The four-layer PC87351EB measures 231 mm x 107.8 mm. It is designed tobe used in a laboratory environment within normal commercial temperatureand humidity ranges:
Temperature : 0 °C to + 50 °CHumidity : 0% to 90%, no condensation
4.3 BASE BOARD CONNECTORS
The PC87351 base board has 11 connectors, described in this section.Table 4-1 shows the function and type of each connector.
Table 4-1. PC87351EB Connector List
Connector Description
J1 SERIAL1 Connector, double-row 10-pin header
J2 SERIAL2 Connector, double-row 10-pin header
J4 KBC Connector, double-row 40-pin header
J6 PS/2 Mouse, MINI-DIN 6-pin round connector
J7 PS/2 Keyboard, MINI-DIN 6-pin round connector
J8 Standby Power Connector, single-row 3-pin header
J10 FDC Connector, double-row 34-pin header
J12 IR Connector, DB9 female connector
J13 Parallel Port Connector, DB25 female connector
P1 ISA Bus Connector, XT, edge 62-pin
P2 ISA Bus Connector, AT, edge 36-pin
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4-2 SPECIFICATIONS PC87351EB Reference Manual
4.3.1 SERIAL1 Connector, J1
A double-row, 10-pin header.
4.3.2 SERIAL2 Connector, J2
A double-row, 10-pin header.
4.3.3 KBC Connector, J4
A double-row, 40-pin header whose pinout is similar to the DIP 40-pin KBCsocket on a PC motherboard. Only some of the signals are supplied by thePC87351. The rest are not connected, or are connected to 1 KΩ pull-up resis-tors.
Table 4-2. SERIAL1 Connector, J1
Signal Pin No. Pin No. Signal
DCD1F 1 2 DSR1F
SIN1F 3 4 RTS1F
SOUT1F 5 6 CTS1F
DTR1F 7 8 RI1F
GND 9 10 N.C.
Table 4-3. SERIAL2 Connector, J2
Signal Pin No. Pin No. Signal
DCD2F 1 2 DSR2F
SIN2F 3 4 RTS2F
SOUT2F 5 6 CTS2F
DTR2F 7 8 RI2F
GND 9 10 N.C.
Table 4-4. KBC Connector, J4
Signal Pin No. Pin No. Signal
N.C. 1 2 KBCV
N.C. 3 4 N.C.
N.C. 5 6 P27
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PC87351EB Reference Manual SPECIFICATIONS 4-3
4.3.4 Mouse Connector, J6
A MINI-DIN 6-pin round connector.
N.C. 7 8 P26
N.C. 9 10 N.C.
N.C. 11 12 IRQ1
N.C. 13 14 P17
N.C. 15 16 P16
N.C. 17 18 P15
N.C. 19 20 P14
N.C. 21 22 P13
RXD0 23 24 P12
RXD2 25 26 P11
RXD3 27 28 P10
RXD4 29 30 N.C.
RXD5 31 32 N.C.
RXD6 33 34 P23
RXD7 35 36 P22
RXD2 37 38 P21
GND 39 40 P20
Table 4-4. KBC Connector, J4 (Continued)
Signal Pin No. Pin No. Signal
Table 4-5. Mouse Connector, J6
Pin No. Signal
1 MDATC
2 N.C.
3 GND
4 MOUVCC
5 MCLKC
6 N.C.
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4-4 SPECIFICATIONS PC87351EB Reference Manual
4.3.5 KBD Connector, J7
A MINI-DIN 6-pin round connector.
4.3.6 Standby Power Connector, J8
A 3-pin header.
4.3.7 FDC Connector, J10
A double-row, 34-pin header. J10 can connect up to two Floppy Disk Drives.
Table 4-6. KBD Connector, J7
Pin No. Signal
1 KBDATC
2 N.C.
3 GND
4 KBDVCC
5 KBCLKC
6 N.C.
Table 4-7. Standby Power Connector, J8
Pin No. Signal
1 N.C.
2 VHEXT
3 GND
Table 4-8. FDC Connector, J10
Signal Pin No. Pin No. Signal
GND 1 2 DENSEL
GND 3 4 N.C.
GND 5 6 DRATE0
GND 7 8 INDEX
N.C. 9 10 MTR0
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PC87351EB Reference Manual SPECIFICATIONS 4-5
4.3.8 IRFE Connector, J12
A 9-pin D-Type, female, right-angle bracket mounted connector, with two ad-ditional pins for shield connection
.
GND 11 12 DR1
GND 13 14 DR0
GND 15 16 MTR1
MSEN1 17 18 DIR
GND 19 20 STEP
GND 21 22 WDATA
GND 23 24 WGATE
GND 25 26 TRK0
MSEN0 27 28 WP
N.C. 29 30 RDATA
GND 31 32 HDSEL
N.C. 33 34 DSKCHG
Table 4-8. FDC Connector, J10 (Continued)
Signal Pin No. Pin No. Signal
Table 4-9. IRFE Connector, J12
PinNo.
TX/RXSignals
ControlSignals
PnPIdentification
SignalsPower
1 IRTXC
2 GND
3 ID3 (Not Used)
4 IRRX2 IRSL0 ID0 (Not Used)
5 IRSL1 ID1 (Not Used)
6 IRRX1
7 IRVCC
8 IRSL2 ID2 (Not Used)
9 N.C.
10, 11 SHIELD
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4-6 SPECIFICATIONS PC87351EB Reference Manual
4.3.9 Parallel Port Connector, J13
A DB25 female connector.
4.3.10 ISA XT and AT Connectors, P1 and P2
The pinout for these connectors meets ISA specifications.
4.4 EXTENSION BOARD CONNECTORS
4.4.1 PME Connector, J1
A 10-pin, dual-row header.
.
Table 4-10. Parallel Port Connector, J13
Pin No. Signal
1 RSTB
2 - 9 RPD0-RPD7
10 RACK
11 RBUSY
12 PE
13 SLCT
14 AFD
15 ERR
16 INIT
17 RSLIN
18 - 25 GND
Table 4-11. PME Connector, J1
Pin No. Signal
1 PME1/RING
2 PME2/SUSP
3-8 N.C.
9,10 GND
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PC87351EB Reference Manual SPECIFICATIONS 4-7
4.4.2 Fan Connector, J2
A 2-pin, dual-row header.
Table 4-12. Fan Connector, J2
4.4.3 GPIO2 Connector, J3
A 10-pin, dual-row header.
Table 4-13. GPIO2 Connector, J3
4.4.4 GPIO1 Connector, J4
A 10-pin, dual-row header.
Table 4-14. GPIO1 Connector, J4
Pin No. Signal
1 GND
2 FANOUT
Pin No. Signal
1 GPIO20
2 GPIO21
3 GPIO22
4-8 N.C.
9,10 GND
Pin No. Signal
1 GPIO10
2 GPIO11
3 GPIO12
4 GPIO13
5 GPIO14
6 GPIO15
7 GPIO16
8 GPIO17
9,10 GND
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4-8 SPECIFICATIONS PC87351EB Reference Manual
4.4.5 ISP Connector, J10
An 8-pin, single-row header.
Table 4-15. ISP Connector, J10
4.5 CURRENT REQUIREMENTS
The PC87351EB board requires +5V and ±12V.
Table 4-16 shows the maximum calculated power consumption for each chip.
Table 4-16. Max Power Consumption
The maximum calculated power consumption for the board is:
567 mA @ +5V44 mA @ +12V−56 mA @ −12V
Pin No. Signal
1 VDD
2 ISPEN
3 SDI
4 SCLK
5 MODE
6 SDO
7,8 GND
Chip Quantity+5V
Current [mA]+12V
Current [mA]−12V
Current [mA]
PC87351 1 32a
a. Typical value
DS14185 2 60 44 -56
DS14C89 1 1
PAL22V10 1 140
74ACTQ32 1 6
74F132 1 18
74LVX3L384 4 80
74LVX3L383 2 40
ispLSI1032E 1 190
Total 567 44 -56
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PC87351EB Reference Manual BASE BOARD SCHEMATIC DIAGRAMS A-1
Appendix A
BASE BOARD SCHEMATIC DIAGRAMS
The following pages contain the schematics diagrams for the PC87351EB baseboard.
![Page 54: SuperI/O PC87351EB Reference Manual€¦ · 2.6 SOFTWARE CONFIGURATION ... • PC87351 hardware configuration • Floppy Disk Controller (FDC), up to 1 MB/sec ... TP1 TP2 TP4 RN2](https://reader034.fdocuments.us/reader034/viewer/2022051814/60379b3a2bfc7f12af3f9b5e/html5/thumbnails/54.jpg)
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Date: April 10, 1997Sheet 1of 14
SizeDocument Number
REV
B870521682-200
2.1
Title
COVER PAGE
ASSEMBLED PCB P/N: 980521682-002 REV:C
PC87317 EVALUATION BOARD
NATIONAL SEMICONDUCTOR
REVISIONS
DATE
APPROVED
IACOB T.
07 JAN 1997
20 JAN 1997
IACOB T.
IACOB T.
09 FEB 1997
IACOB T.
03 FEB 1997
IACOB T.
23 MAR 1997
IACOB T.
04 MAR 1997
09 APR 1997
IACOB T.
DESCRIPTION
1.0
SCH
ECN#
INITIAL VERSION
682-001/A
1.1
DDR REVIEW
1.2
1.3
RELEASED VER AFTER BACKANOTATION
682-001/A
1.4
184
CONFIGURATION RESISTORS, U2, U1
682-001/A
686-001/A
ASSEMBLY BASE NUMBER --> 686
UPDATE FOR PC87309 SUPPORT
UPDATE FOR PC87309EB USE ONLY.
PCB 551521
ASS 980521
682-002/A
2.0
186
682-002/A
NEW PCB LAYOUT INCLUDING:
SOCKET OPTION FOR U4.
682-002/A
2.1
189
682-002/B
682-002/C
R41 680R PULL-DOWN
R41 10K PULL-DOWN, U8 CMOS
PULL-DOWN OPTION ON STRAP PINS,
SER.SCH
PAR.SCH
IR.SCH
FDC.SCH
ISA.SCH
CHIP.SCH
SERIAL PORTS DRIVERS & CONNECTORS
PARALLEL PORT TERMINATIONS & CONNECTOR
SCHEMATIC:
DESIGN FILES (ORCAD 386+)
PG.1
PG.2
PG.3
PG.4
PG.5
PG.6
PG.7
PC87317 CHIP CONNECTIONS
GPIO_APC.SCH
TST_CON.SCH
PG.8
PG.9
PG.10
GPIO AND ADVANCED POWER CONTROL
ISA CONNECTOR
INFRARED PORT CONNECTOR
COVER PAGE
BLOCK DIAGRAM
LOGIC.SCH
GLUE LOGIC
CFG.SCH
PS2.SCH
PG.11
PS/2 KEYBOARD AND PS/2 MOUSE
PG.12
PG.13
PG.14
KBC_RTC.SCH
KBC AND RTC CABLE CONNECTORS
TEST CONNECTORS
FLOPPY DISK DRIVE CONNECTOR
PC87317 CONFIGURATION & CLOCK SOURCES
COVER.SCH
PC87317.SCH
LIBRARY:
NATIONAL SEMICONDUCTOR LIBRARY
317EB.LIB
COVER.SCH
NA
TIO
NA
L S
EM
ICO
ND
UC
TO
R
PC
87351 B
AS
E B
OA
RD
AS
SE
MB
LE
D P
CB
P/
N 9
80521694-0
01
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Date: April 10, 1997Sheet 2of 14
SizeDocument Number
REV
B870521682-200
2.1
Title
BLOCK DIAGRAM
PC87317 EVALUATION BOARD
NATIONAL SEMICONDUCTOR
PG.7
SERIAL PORT
SER.SCH
SOUT2
SIN2
SIN1
nDCD1
nDSR1
nRTS1
SOUT1
nCTS1
nDTR1
nRI1
nDCD2
nDSR2
nRTS2
nCTS2
nDTR2
nRI2
+12V
VCC
-12V
GND
VCCH
FDC
FDC.SCH
VCC
F[1..18]
GND
nDCD1
nDSR1
SIN1
nRTS1
SOUT1
nDTR1
nCTS1
nRI1
F[1..18]
+12V
-12V
VCC
VCC
VCCH
11,12,14,15]
PC87317 SUPERIO
CHIP.SCH
F[1..18]
nDCD1
nDSR1
SIN1
nRTS1
SOUT1
nCTS1
nDTR1
nRI1
nDCD2
nDSR2
SIN2
nRTS2
SOUT2
nCTS2
nDTR2
nRI2
IRTX
IRRX1
IRRX2
IRSL1
IRSL2
ID3
nSTB
nAFD
nERR
nINIT
nSLIN
nACK
BUSY
PE
SLCT
PD[0..7]
GPIO1[0..7]
GPIO2[0..7]
GPIO3[0..7]
SA[0..15]
AEN
nIORD
nIOWR
nZWS
IOCHRDY
DRQ[0..3]
nDACK[0..3]
TCF
VCC
VDD
GND
nSWITCH
nONCTL
nLED
nRING
IRQ[1..15]
SIOD[0..7]
MR
K[1..5]
PS[1..4]
S[1..160]
C[0..5]
X2C
X1C
X1
VCCH
nZWS
IOCHRDY
AEN
TCF
DRQ[0..3]
nDACK[0..3]
nIOWR
nIORD
SA[0..15]
IRQ[3,4,5,6,7,9,
ISA CONNECTOR
ISA.SCH
+12V
-12V
SA[0..15]
AEN
ISAVCC
nIORD
nIOWR
nZWS
IOCHRDY
DRQ[0..3]
nDACK[0..3]
TCF
IRQ[1..15]
GND
ISARST
ISAD[0..7]
ISAVCC
+12V
-12V
PG.4
PG.3
LOGIC AND POWER
LOGIC.SCH
SIOD[0..7]
MR
ISAD[0..7]
ISARST
SA[0..15]
AEN
nIORD
nIOWR
nCSIN
PAEN
KBCPRES
RTCPRES
RXD[0..7]
VCC
EXTVCC
VDD
GND
ISAVCC
CFG0A
SIOD[0..7]
RXD[0..7]
AEN
nIOWR
nIORD
SA[0..15]
CFG0A
MR
VCC
VCC
VDD
EXTVCC
PG.8
IR PORT
IR.SCH
VCCH
SHIELD
GND
VCC
ID3
IRSL2
IRSL1
IRRX2
IRRX1
IRTX
EXTVCC
SIN2
SOUT2
nDCD2
nDSR2
nRTS2
nCTS2
nDTR2
nRI2
IRRX1
IRRX2
IRSL1
IRSL2
IRTX
ID3
EXTVCC
VCCH
VCC
PG.9
PG.10
PARALLEL PORT
PAR.SCH
nSTB
nAFD
nERR
nINIT
nSLIN
nACK
BUSY
PESLCT
PD[0..7]
SHIELD
VCC
GND
GPIO & APC
GPIO_APC.SCH
GPIO3[0..7]
GPIO2[0..7]
GPIO1[0..7]
nSWITCH
nONCTL
nLED
nRING
EXTVCC
VCC
VCCH
GND
nSTB
nACK
BUSY
PESLCT
nSLIN
nINIT
nERR
nAFD
PD[0..7]
GPIO1[0..7]
GPIO2[0..7]
GPIO3[0..7]
SHIELD
VCC
VCC
EXTVCC
K[1..5]
PS[1..4]
VDD
PG.13
IRQ[1,8]
PS/2 CONNECTORS
PS2.SCH
VCC
EXTVCC
GND
PS[1..4]
KBC AND RTC CONN.
KBC_RTC.SCH
RXD[0..7]
K[1..5]
RTCPRES
KBCPRES
IRQ[1..15]
GND
VCC
EXTVCC
VCC
VCC
PG.14
PG.12
TEST CONNECTOR
TST_CON.SCH
VDD
PAEN
nCSIN
VCC
GND
S[1..160]
C[6..7]
CFG0A
PAEN
nCSIN
CFG0A
VCC
PG.5
S[1..160]
C[6..7]
CFG0A
VDD
PG.6
PG.11
PC87317 CONFIG
CFG.SCH
VCC
GND
C[0..5]
X2C
X1C
X1
C[6..7]
CFG0A
nLED
nSWITCH
nONCTL
nRING
C[0..5]
X2C
X1C
X1
VCCH
VCCH
VCC
PC87317.SCH
NA
TIO
NA
L S
EM
ICO
ND
UC
TO
R
PC
87351 B
AS
E B
OA
RD
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Date: April 10, 1997Sheet 3of 14
SizeDocument Number
REV
B870521682-200
2.1
Title
ISA CONNECTOR
PC87317 EVALUATION BOARD
NATIONAL SEMICONDUCTOR
PG.5
PG.4
PG.4,5
PG.4,5
AEN
IOCHRDY
SA[0..15]
ISAD[0..7] GND
AEN
IOCHRDY
SA[0..15]
ISAD[0..7]
COMPONENT
SIDE
SIDE
ISA ADD-IN
CARD
EDGE
CONNECTOR
M E M C S 1 6
D 1
I O C S 1 6
D 2
I R Q 1 0
D 3
I R Q 1 1
D 4
I R Q 1 2
D 5
I R Q 1 5
D 6
I R Q 1 4
D 7
D A C K 0
D 8
D R Q 0
D 9
D A C K 5
D 1 0
D R Q 5
D 1 1
D A C K 6
D 1 2
D R Q 6
D 1 3
D A C K 7
D 1 4
D R Q 7
D 1 5
+ 5 V
D 1 6
M A S T E R
D 1 7
G N D
D 1 8
S B H E
C 1
L A 2 3
C 2
L A 2 2
C 3
L A 2 1
C 4
L A 2 0
C 5
L A 1 9
C 6
L A 1 8
C 7
L A 1 7
C 8
M E M R
C 9
M E M W
C 1 0
S D 0 8
C 1 1
S D 0 9
C 1 2
S D 1 0
C 1 3
S D 1 1
C 1 4
S D 1 2
C 1 5
S D 1 3
C 1 6
S D 1 4
C 1 7
S D 1 5
C 1 8
P2
PCAT36
G N D
B 1
R E S E T D R V
B 2
+ 5 V
B 3
I R Q 9
B 4
- 5 V
B 5
D R Q 2
B 6
- 1 2 V
B 7
Z W S
B 8
+ 1 2 V
B 9
G N D
B 1 0
S M E M W
B 1 1
S M E M R
B 1 2
I O W
B 1 3
I O R
B 1 4
D A C K 3
B 1 5
D R Q 3
B 1 6
D A C K 1
B 1 7
D R Q 1
B 1 8
R E F S H
B 1 9
S Y S C L K
B 2 0
I R Q 7
B 2 1
I R Q 6
B 2 2
I R Q 5
B 2 3
I R Q 4
B 2 4
I R Q 3
B 2 5
D A C K 2
B 2 6
T C
B 2 7
B A L E
B 2 8
+ 5 V
B 2 9
O S C
B 3 0
G N D
B 3 1
I O C H C K
A 1
S D 0 7
A 2
S D 0 6
A 3
S D 0 5
A 4
S D 0 4
A 5
S D 0 3
A 6
S D 0 2
A 7
S D 0 1
A 8
S D 0 0
A 9
I O C H R D Y
A 1 0
A E N
A 1 1
S A 1 9
A 1 2
S A 1 8
A 1 3
S A 1 7
A 1 4
S A 1 6
A 1 5
S A 1 5
A 1 6
S A 1 4
A 1 7
S A 1 3
A 1 8
S A 1 2
A 1 9
S A 1 1
A 2 0
S A 1 0
A 2 1
S A 0 9
A 2 2
S A 0 8
A 2 3
S A 0 7
A 2 4
S A 0 6
A 2 5
S A 0 5
A 2 6
S A 0 4
A 2 7
S A 0 3
A 2 8
S A 0 2
A 2 9
S A 0 1
A 3 0
S A 0 0
A 3 1
P1
PCXT62
P N
C45
22U
2 1
C44
0.1U
P N
C42
22U
2 1
C41
0.1U
P N
C25
22U
2 1
C24
0.1U
PG.4
PG.4
ISARST
ISAVCC
ISARST
ISAVCC
PG.5
PG.8
PG.5
PG.4,5
PG.4,5
PG.8
PNC27
22U
+12V
-12V
DRQ[0..3]
nDACK[0..3]
nZWS
nIOWR
nIORD
-12V
+12V
nZWS
nIOWR
nIORD
P N
C29
22U
2 1
C33
47P
1 2
R58
100R
TC
TCF
12
J11
N/A
IRQ10
IRQ11
PG.5
PG.5
PG.3,13
TCF
IRQ[1..15]
IRQ1
IRQ2
IRQ8
IRQ13
ISA.SCH
NA
TIO
NA
L S
EM
ICO
ND
UC
TO
R
PC
87351 B
AS
E B
OA
RD
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Date: April 10, 1997Sheet 4of 14
SizeDocument Number
REV
B870521682-200
2.1
Title
LOGIC AND POWER
PC87317 EVALUATION BOARD
NATIONAL SEMICONDUCTOR
161
162
TO TEST CON
PG.14
PG.13
RTCPRES
KBCPRES
nCSIN
PAEN
RTCPRES
KBCPRES
PAEN
nCSIN
VCC
SWITCH
BE0-4
1
B0
2
A0
3
A1
4
B1
5
B2
6
A2
7
B3
9
A3
8
A4
11
B4
10
GND
12
VCC
24
B9
23
A9
22
A8
21
B8
20
B7
19
A7
18
A6
17
B6
16
B5
15
A5
14
BE5-9
13
U10
74LVX3L384A
SMD-TSOP24
21C26
0.1U
nISAENBL
ISAD0
ISAD1
ISAD2
ISAD3
ISAD4
ISAD5
ISAD6
ISAD7
SIOD0
SIOD1
SIOD2
SIOD3
SIOD4
SIOD5
SIOD6
SIOD7
AENnXENBL
nISAENBL
RTCPRES
KBCPRES
nCSIN
PAEN
CFG0A
VCC
PG.3
PG.3
PG.3
C/I
1
I2
2
I3
3
I4
4
I5
5
I6
6
I7
7
I8
8
VCC
24
IO10
23
IO9
22
IO8
21
IO7
20
IO6
19
IO5
18
IO4
17
I9
9
I10
10
I11
11
GND
12
I12
13
IO1
14
IO2
15
IO3
16
U6
PAL22V10
DIP24ON SOCKET
ISAD[0..7]
SA[0..15]
nIORD
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
ISAD[0..7]
nIORD
THIS CIRCUIT EXIST ONLY FOR AN
PG.3
PG.3
PG.6
4
5
6 U7B
74ACTQ32
1
2
3
U7A 74ACTQ32
nIOWR
AEN
CFG0A
SA9
SA10
SA12
SA13
SA14
SA15
SA12_13
SA14_15
AEN
nIOWR
CFG0A
SA11
21C28
0.1U
9
10
8
U7C
74ACTQ32
SA11
nIORD
nIOWR nCSIN
VCC
SWITCH
BE0-4
1
B0
2
A0
3
A1
4
B1
5
B2
6
A2
7
B3
9
A3
8
A4
11
B4
10
GND
12
VCC
24
B9
23
A9
22
A8
21
B8
20
B7
19
A7
18
A6
17
B6
16
B5
15
A5
14
BE5-9
13
U5
74LVX3L384A
SMD-TSOP24
21C43
0.1U
nXENBL
SIOD0
SIOD1
SIOD2
SIOD3
SIOD4
SIOD5
SIOD6
SIOD7
RXD0
RXD1
RXD2
RXD3
RXD7
RXD6
RXD5
RXD4
VCC
GND
TEST POINTS
PG.5
PG.13
VCC
GND
1TP2
1TP3
1TP4
N/A
1TP1
N/A
SIOD[0..7]
RXD[0..7]
VCC
VCC
VCC
PG.5
PG.14
PG.11
PG.12
PG.9
1
2
XF1FUSE-SOCKET
SMD2A
1
2F2
FUSE
1.5A/125V
N/A
GND
VCC
EXTVCC
VDD
VCC
FUSE
EXT
21
C21
0.1U
1
TP6
N/A
1
TP5
N/A
XJP3
ISAVCC
RESET CIRCUIT
DEBUG
12
13
11
U8D
74ACT00
SW
RESET
PG.3
ISA ADD-IN BOARD APPLICATION.
FOR A MOTHERBOARD APPLICATION
THIS CIRCUIT IS NOT NEEDED.
2 134 5
SW4
1
2R33
10K
ISAVCC
ISAVCC
RST_NO
VCC
SWITCH
PG.3
ISARST
JUMPER
1
2R32
10K
1
2
JP4
DEFAULT: IN
XJP4
1
2R4110K
ISARST
ISARST
RST_NC
VCC
2 1
C19
0.1U
1
2
R40
0R
N/A
9
10
8
U8C
74ACT00
1
2
3
U8A
74ACT00
4
5
6
U8B
74ACT00
MR
MR
nSW nISARST
RST
VCC
PG.5
DECOUPLING FOR PC87317
124
PIN #
VDD
JUMPER
P N
C35
22U
21
C39
0.1U
21
C36
0.1U
1
2
JP3
DEFAULT: IN
VCC
61
100
121
140
TO PC87317
PIN #
1 2461100
121
140
21
C32
0.1U
21
C34
0.1U
21
C38
0.1U
21
C37
0.1U
LOGIC.SCH
NA
TIO
NA
L S
EM
ICO
ND
UC
TO
R
PC
87351 B
AS
E B
OA
RD
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Date: April 10, 1997Sheet 5of 14
SizeDocument Number
REV
B870521682-200
2.1
Title
PC87317 CHIP
PC87317 EVALUATION BOARD
NATIONAL SEMICONDUCTOR
PG.9
PIN 158
PG.7
JP1/8
IRTX ID3
IRRX1
IRRX2
IRSL1
IRSL2
F[1..18]
VDD
nERR
nINIT
nSLIN
nAFD
PG.12
PG.13
PG.10
nERR
nINIT
nACK
PE
SLCT
BUSY
nSTB
nSLIN
nAFD
PD[0..7]
K[1..5]
PS[1..4]
nERR
nINIT
nACK
SLCT
PE
nSTB
BUSY
nAFD
nSLIN
PD[0..7]
PG.6
nDCD1
nDSR1
nCTS1
nRI1
nDTR1
VCC
VDD
GND
C[0..5]
BADDR0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
C4
C[0..5]
VDD
VCC
V D D
1V S S
2D 0
3D 1
4D 2
5D 3
6D 4
7D 5
8D 6
9D 7
1 0V S S
1 1A 0
1 2A 1
1 3A 2
1 4A 3
1 5A 4
1 6A 5
1 7A 6
1 8A 7
1 9A 8
2 0A 9
2 1A 1 0
2 2A 1 1
2 3V D D
2 4V S S
2 5A 1 2
2 6A 1 3
2 7A 1 4
2 8A 1 5
2 9A E N
3 0Z W S
3 1I O C H R D Y
3 2R D
3 3W R
3 4T C
3 5I R Q 1
3 6I R Q 3
3 7I R Q 4
3 8I R Q 5
3 9V S S
4 0
IRQ6
41
IRQ7
42
IRQ8
43
IRQ9
44
IRQ10
45
IRQ11
46
IRQ12
47
IRQ14
48
IRQ15
49
X1
50
MR
51
DRQ0
52
DRQ1
53
DRQ2
54
DRQ3
55
DACK0
56
DACK1
57
DACK2
58
DACK3
59
VSS
60
VDD
61
X1C
62
X2C
63
VBAT
64
VCCH
65
SWITCH
66
ONCTL
67
LED/CS0
68
RING/XDCS
69
XDRD/ID3
70
CS1/XD0/CSOUT-NSC
71
CS2/XD1
72
GPIO24/XD2
73
GPIO25/XD3
74
GPIO26/XD4
75
GPIO27/XD5
76
IRSL2/SELCS/GPIO21/XD6
77
IRSL1/ID1/XD7
78
GPIO37/IRRX2/IRSL0/ID0
79
GPIO24/IRRX1
80
I R T X
8 1
M S E N 0
8 2
M S E N 1
8 3
D R A T E 0
8 4
M T R 0
8 5
M T R 1
8 6
D R 0
8 7
D R 1
8 8
W D A T A
8 9
S T E P
9 1 D I R
9 0
H D S E L
9 2
W G A T E
9 3
D E N S E L
9 4
R D A T A
9 5
T R K 0
9 6
I N D E X
9 7
W P
9 8
D S K C H G
9 9
V D D
1 0 0
V S S
1 0 1
K B C L K
1 0 2
K B D A T
1 0 3
M C L K
1 0 4
M D A T
1 0 5
P 1 2 / C S 0
1 0 6
P 1 6 / G P I O 2 5
1 0 7
P 1 7
1 0 8
P 2 0
1 0 9
P 2 1
1 1 0
B U S Y / W A I T
1 1 1
S T B / W R I T E
1 1 2
A C K
1 1 3
S L C T
1 1 4
P E
1 1 5
E R R
1 1 6
I N I T
1 1 7
S L I N / A S T R B
1 1 8
A F D / D S T R B
1 1 9
V S S
1 2 0
VDD
121
PD0
122
PD1
123
PD2
124
PD3
125
PD4
126
PD5
127
PD6
128
PD7
129
VSS
130
CTS1
131
DCD1
132
DSR1
133
DTR1/BADDR0
134
RI1
135
RTS1/BADDR1
136
SIN1
137
SOUT1/BOUT1/CFG0
138
VSS
139
VDD
140
GPIO30/CTS2
141
GPIO31/DCD2
142
GPIO32/DSR2
143
DTR2/CFG1
144
GPIO33/RI2
145
GPIO34/RTS2
146
GPIO35/SIN2
147
GPIO36/SOUT2
148
GPIO10
149
GPIO11
150
GPIO12
151
GPIO13
152
GPIO14
153
GPIO15/PME2
154
GPIO16/PME1
155
GPIO17/WDO
156
GPIO20/IRSL1/ID1
157
GPIO21/IRSL0/IRSL2/ID2
158
GPIO22/POR
159
GPIO23/RING
160
U4
PC87317-XXX/VUL
ON SOCKET
S121
S122
S123
S124
S125
S126
S127
S128
S129
S130
S131
S132
S133
S134
S135
VDD
S66
S67
S68
S69
S70
S71
S72
S73
S74
S75
S76
S77
S78
S79
S80
NEAR
PIN 65
PG.14
RTC
TO TEST
CONNECTOR
TO PC87317
PG.11
1
2R82
SPARE
21C30
0.1U
nLED
nONCTL
nSWITCH
VCCH
S[1..160]
nRING
GPIO37
GPIO24
GPIO25
GPIO26
GPIO27
nSWITCH
nONCTL
nLED
S[1..160]
GPIO21
nRING
NEAR
PIN 64
BACKUP PG.6
PG.3
21C31
0.1U
P 1P 2
NBT13.0V
P NXBT2
CR2032
OPTION
SOCKET
N/A
MR
nDACK[0..3]
DRQ[0..3]
X2CX1C
X1C
X2C
VBAT
VCCH
VDD
IRQ15
IRQ14
IRQ12
IRQ11
IRQ10
IRQ9
IRQ8
IRQ7
nDACK3
nDACK2
nDACK1
nDACK0
DRQ3
DRQ2
DRQ1
DRQ0
MRX1
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
S64
S65
S136
S137
S138
S139
S140
S141
S142
S143
S144
S145
S146
S147
S148
S149
S150
S151
S152
S153
S154
S155
S156
S157
S158
S159
FROM IR
INTERFACE
PG.8
PIN
79
TESTING SERIAL2 OR IR.
WHEN TESTING GPIO3.
INSERT IT WHEN
(CFG2)
(CFG3)
REMOVE JUMPER JP1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
JP1
8X10R
ON SOCKET
JUMPER
SIN1
nRTS1
SOUT1
nDCD2
nDSR2
SIN2
nCTS2
nRI2
nRTS2
SOUT2
nDTR2
GPIO31
GPIO32
GPIO34
GPIO36
GPIO30
GPIO33
GPIO35
GPIO37
GPIO11
GPIO12
GPIO14
GPIO16
GPIO10
GPIO13
GPIO15
GPIO17
BADDR1
CFG0
CFG1
IRRX2
C5
C0
C1
C2
C3
VDD
PIN 76
PIN 75
PIN 74
PIN 73
PIN 77
PG.11
PG.4
PG.3
GPIO3[0..7]
GPIO1[0..7]
GPIO2[0..7]
SIOD[0..7]
SA[0..15]
GPIO21
GPIO22
GPIO24
GPIO26
GPIO20
GPIO23
GPIO25
GPIO27
SIOD[0..7]
SA[0..15]
/ID2
IRSL2
S160
VDD
IRQ6
S41
IRQ2
IRQ13
VDD
PG.6
PG.4
PG.3
X1
IRQ[1..15]
nZWSAEN
IOCHRDY
nIORD
nIOWR
TCF
CHIP.SCH
NA
TIO
NA
L S
EM
ICO
ND
UC
TO
R
PC
87351 B
AS
E B
OA
RD
NO
T M
OU
NT
ED
P 2 1 K 5P 2 0 K 4
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Date: April 10, 1997Sheet 6of 14
SizeDocument Number
REV
B870521682-200
2.1
Title PC87317 CONFIGURATION & CLOCK SOURCE
PC87317 EVALUATION BOARD
NATIONAL SEMICONDUCTOR
1
3 2
4Y1
32.768KHz
X1C
X2C
XR
1 2
R17
20M 1
2R18
120K
2 1
C3
33P 2
1 C4
10P
PG.5
PG.5
X2C
X1C
TABLE 1.
0=OFF 1=ON
BADDR0
VCC
VCC 1 0
9
78
SW1D
DEFAULT: 1110
THE REAL APPLICATION
U7D, SW1 AND SW2 ARE
NEEDED ONLY FOR THE
EVALUATION BOARD.
NOTE 1:
RES1
RES2
BADDR1
VCC
VCC
NEEDS ONLY SOME PULL-UP RESISTORS.
1 61 5
12
SW1A
1 41 3
34
SW1B
1 21 1
56
SW1C
1 2R63A
10K
1 2R64A
10K
1 2R65A
10K
1 2R63B
SMD-1206
1 2R64B
SMD-1206
BASE
FULL PnP ISA
PnP MBDADDRESS
CLOCK CONFIG
24MHz ON X1
RESERVED
TABLE 2.
PC87308/307 *1)
DEFAULT :
1 2R66A
10K
1 2R65B
SMD-1206
1 2R66B
SMD-1206
0
11
X 0
SW1
BADDR1
BADDR0
015C
002E
SW2
CFG3
CFG2
00 1
0
RTC OSCILLATOR & CLOCK MULTIPLIER SOURCE
10
GND SHIELD NET 21C23
0.1U
1
4
7
811
14
XU9
DIP14
SOCKET
1
7
814
U9
CRYSTAL-OSC
DIP14
48MHz
VCC
DEFAULT:
NEEDED ONLY IF NOT USING
THE ON-CHIP CLOCK MULTIPLIER.
EXTERNAL CLOCK OSCILLATOR
THE EXTERNAL OSCILLATOR IS
VCC
X1
VCC
0 11 1
1 0
SW2
CFG1
CFG0
NYY N
ENA-
BLED
1 032.768KHz
48MHz ON X1
PG.5
X XX X
11
00
NOTE 5:
1 0 *3
X1
48MHz ON X1
32.768KHz
RESET CONFIG
X-DATA BUFFER
CLOCK
SOURCE
PC87317 ONLY
KBC RTC FDC
TABLE 3.
DEFAULT :
DEFAULT :
0=OFF 1=ON
CFG2
CFG3
1 2R70A
100R
VCC
VCC
1 2R69B
SMD-1206
1 2R70B
SMD-1206
1 09
78
SW2D
DEFAULT: 1100
CFG0
CFG1
1 2
R72A
10K
1 2
R71A
10K
1 2
R69A
10K
N/A
VCC
VCC
1 2R72B
SMD-1206
1 2
R71B
SMD-1206
1 61 5
12
SW2A
1 41 3
34
SW2B
1 21 1
56
SW2C
NOTE 2:
R72A/B AND R71A/B ARE
PROVIDED FOR PC87308/307
*3)
*2)
SUPPORT ONLY; SEE TABLE 4.
PC87307
PC87317
PC87309
POWER-ON CONFIGURATION SIGNALS
CHIP\SIGNAL
PC87308
TABLE 4.
NOTE 3:
R69A IS NOT ASSEMBLED SINCE THE
X-BUS DATA BUFFER IS NOT
IMPLEMENTED IN THIS EVALUATION BOARD.
1 2
R74
10K
12
13
11
U7D
74ACTQ32
1 2R73
1K
CFG0B
CFG0A
10
BADDR
CFG
32
10
PG.5
PG.14
PG.4
PG.14
C[0..5]
CFG0A
C[6..7]
GND
CFG.SCH
NA
TIO
NA
L S
EM
ICO
ND
UC
TO
R
PC
87351 B
AS
E B
OA
RD
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Date: April 10, 1997Sheet 7of 14
SizeDocument Number
REV
B870521682-200
2.1
Title
FLOPPY DISK DRIVE CONNECTOR
PC87317 EVALUATION BOARD
NATIONAL SEMICONDUCTOR
23456
1
RN2
SIP6
5X1K
PG.5
21C22
0.1U
VCC
GND
F[1..18]
F13
F14
F15
F16
F17
F18
nTRK0
nRDATA
nHDSEL
nDSKCHG
MSEN0
nWP
FLOPPY
DISK
CONNECTOR
DRIVE
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
1
2
J10
HD17X2
DENSEL
DRATE0
nINDEX
nMTR0
nDR1
nDIR
nWDATA
nWGATE
MSEN1
nDR0
nMTR1
nSTEP
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
FDC.SCH
NA
TIO
NA
L S
EM
ICO
ND
UC
TO
R
PC
87351 B
AS
E B
OA
RD
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Date: April 10, 1997Sheet 8of 14
SizeDocument Number
REV
B870521682-200
2.1
Title SERIAL PORTS DRIVERS AND CONNECTORS
PC87317 EVALUATION BOARD
NATIONAL SEMICONDUCTOR
PG.5
SERIAL
PORT #1
nDCD1
nDSR1
SIN1
nCTS1
nRI1
nRTS1
SOUT1
nDTR1
21C57
0.1U
21C56
0.1U
2
4
5
9
10
1213
1
14
3
6
8
11
7
151617181920
U1
DS14185M
SMD-SO20W
nDSR1
nRTS1
nCTS1
nDTR1
nRI1
nDCD1
SIN1
SOUT1
+12V
VCC
1
2R1
33R
1
2R2
33R
1
2R3
33R
1
2R4
33R
1
2R5
33R
1
2R6
33R
1
2R7
33R
1
2R8
33R
DCD1
DSR1
nSIN1
RTS1
nSOUT1
CTS1
DTR1
RI1
SERIAL
PORT #1
CONNECTOR
3 4 5 6 7 8 9 10
1 2
J1
HD5X2
DCD1F
DSR1F
nSIN1F
RTS1F
nSOUT1F
CTS1F
DTR1F
RI1F
USE ONLY THE CABLES
WITH STRIGHT CONNECTIONS
IMPORTANT NOTE :
DCD1F
DSR1F
nSIN1F
RTS1F
nSOUT1F
CTS1F
DTR1F
RI1F
CONNECT THE
CAPACITORS
CONNECTORS.
PLACE CLOSE TO
TO SHIELD.
EMI FILTER
NOTE:
1.
2.
2
1C66
200P
2
1C67
200P
2
1C68
200P
2
1C69
200P
2
1C70
200P
2
1C71
200P
2
1C72
200P
2
1C73
200P
21C59
0.1U
21C55
0.1U
13
11
1 4 7U3D
DS14C89A
-12V
VCCH
VCCH
VCC
PG.3
PG.3
PG.11
+12V
-12V
VCCH
-12V
+12V
VCC
VCCH
PG.5
SERIAL
PORT #2
VCC
nDCD2
nDSR2
SIN2
nCTS2
nRI2
nRTS2
SOUT2
nDTR2
GND
21C61
0.1U
21C60
0.1U
P NC58
22U
2
4
5
9
10
1213
1
14
3
6
8
11
7
151617181920
U2
DS14185M
SMD-SO20W
nDSR2
nRTS2
nCTS2
nDTR2
nRI2
nDCD2
SIN2
SOUT2
VCC
+12V
DUE TO LAYOUT
LIMITATIONS,
THE CAPACITORS
ON THIS BOARD,
ARE CONNECTED
TO GND.
3.
1
2R9
33R
1
2R10
33R
1
2R11
33R
1
2R12
33R
1
2R13
33R
1
2R14
33R
1
2R15
33R
1
2R16
33R
2
1C74
200P
DCD2
DSR2
nSIN2
RTS2
nSOUT2
CTS2
DTR2
RI2
SERIAL
PORT #2
CONNECTOR
3 4 5 6 7 8 9 10
1 2
J2
HD5X2
DCD2F
DSR2F
nSIN2F
RTS2F
nSOUT2F
CTS2F
DTR2F
RI2F
SPARE
4
6
1 4 7U3B
DS14C89A
10
8
1 4 7U3C
DS14C89A
DCD2F
DSR2F
nSIN2F
RTS2F
nSOUT2F
CTS2F
DTR2F
RI2F
VCCH
VCCH
2
1C75
200P
2
1C76
200P
2
1C77
200P
2
1C78
200P
2
1C79
200P
2
1C80
200P
2
1C81
200P
21C62
0.1U
1
3
1 4 7U3A
DS14C89A
-12V
VCCH
SER.SCH
NA
TIO
NA
L S
EM
ICO
ND
UC
TO
R
PC
87351 B
AS
E B
OA
RD
![Page 70: SuperI/O PC87351EB Reference Manual€¦ · 2.6 SOFTWARE CONFIGURATION ... • PC87351 hardware configuration • Floppy Disk Controller (FDC), up to 1 MB/sec ... TP1 TP2 TP4 RN2](https://reader034.fdocuments.us/reader034/viewer/2022051814/60379b3a2bfc7f12af3f9b5e/html5/thumbnails/70.jpg)
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Date: April 10, 1997Sheet 9of 14
SizeDocument Number
REV
B870521682-200
2.1
Title
INFRARED PORT CONNECTOR
PC87317 EVALUATION BOARD
NATIONAL SEMICONDUCTOR
PG.4
EXTVCC
EXTVCC
PG.11
GND
VCCH
VCC
VCCH
VCC
ID0
IRRX1
THE LOGIC LEVEL WHEN
IS NOT CONNECTED.
THE PULL-UPS ON IRRX1
AND IRRX2 ARE CONNECTED
TO VCCH SINCE THEY
CAN BE INPUTS TO APC.
PULL-UPS TO ASSURE
THE IR FRONT END (IRFE)
P NC5100U
21C20
0.1U
1 2R35
150K
1 2R38
150K
VCCH
VCCH
ID1
ID2
ID3
1 2R39
150K
1 2R37
150K
1 2R36
150K
VCC
VCC
VCC
DB9
INFRARED
PORT
CONNECTOR
PG.10
SHIELD
SHIELD
1 01 1
9
8
7
6
5
4
3
2
1
J12
CON DB9 FEMALE
ID3
IRSL2
IRSL0
IRSL1
ID0
ID1
ID2
IRRX2
IRRX1
IRTXC
PG.5
1
2R34
33R
IRTX
IRRX1
IRRX2
IRSL1
IRSL2
ID3
IRRX1
IRRX2
IRSL0
IRSL1
IRSL2
SIGNALS
IRTX
IR MULTIPLEXED
ID0
ID1
ID2
ID3
IR.SCH
NA
TIO
NA
L S
EM
ICO
ND
UC
TO
R
PC
87351 B
AS
E B
OA
RD
![Page 72: SuperI/O PC87351EB Reference Manual€¦ · 2.6 SOFTWARE CONFIGURATION ... • PC87351 hardware configuration • Floppy Disk Controller (FDC), up to 1 MB/sec ... TP1 TP2 TP4 RN2](https://reader034.fdocuments.us/reader034/viewer/2022051814/60379b3a2bfc7f12af3f9b5e/html5/thumbnails/72.jpg)
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Date: April 10, 1997Sheet 10of 14
SizeDocument Number
REV
B870521682-200
2.1
Title
PARALLEL PORT TERMINATIONS AND CONNECTOR
PC87317 EVALUATION BOARD
NATIONAL SEMICONDUCTOR
PARALLEL
PORT
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
2 62 7
J13
CON DB25 FEMALE
nERR
nINIT
nERR
nRSTB
nRAFD
nRSTB
nRAFD
nRSLIN
RPD0
RPD1
RPD2
RPD3
RPD4
RPD5
RPD6
RPD7
RPD0
1
2R19
33R
1
2R42
4.7K
1
2R43
4.7K
1
2R44
4.7K
2 1C6
330P 2
1C7
330P 2
1C8
330P
1
2R20
33R
1
2R21
33R
VCC
VCC
VCC
PG.5
nSTB
nERR
nAFD
PD[0..7]
nSTB
nAFD
PD[0..7]
PD0
nERR
nSLIN
nINIT
nSLIN
PD1
PD2
nINIT
1
2R48
4.7K
1
2R45
4.7K
1
2R46
4.7K
1
2R47
4.7K
1
2R49
4.7K
2 1C9
330P 2
1C10
330P 2
1C12
330P2
1C11
330P
1
2R22
33R
1
2R23
33R
1
2R24
33R
1
2R25
33R
VCC
VCC
VCC
VCC
VCC
nRSLIN
nINIT
nRACK
RBUSY
RPD1
RPD2
RPD3
PG.6
2 1 R81
PCB SHORT
N/A
SHIELD
SHIELD
SLCT
PE
VCC
GND
VCC
nRACK
RPD4
RPD5
RPD6
RPD7
2 1C15
330P
1
2R50
4.7K
1
2R51
4.7K
1
2R52
4.7K
1
2R53
4.7K
1
2R54
4.7K
2 1C13
330P 2
1C14
330P 2
1C16
330P 2
1C17
680P
1
2R26
33R
1
2R27
33R
1
2R28
33R
1
2R29
33R
1
2R30
100R
VCC
VCC
VCC
VCC
VCC
PD3
PD4
PD5
PD6
PD7
BUSY
nACK
PE
SLCT
nACK
BUSY
PE
SLCT
1
2R55
4.7K
1
2R56
4.7K
2 1C18
680P
1
2R31
100R
VCC
VCC
SLCT
RBUSY
PE
PAR.SCH
NA
TIO
NA
L S
EM
ICO
ND
UC
TO
R
PC
87351 B
AS
E B
OA
RD
![Page 74: SuperI/O PC87351EB Reference Manual€¦ · 2.6 SOFTWARE CONFIGURATION ... • PC87351 hardware configuration • Floppy Disk Controller (FDC), up to 1 MB/sec ... TP1 TP2 TP4 RN2](https://reader034.fdocuments.us/reader034/viewer/2022051814/60379b3a2bfc7f12af3f9b5e/html5/thumbnails/74.jpg)
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Date: April 10, 1997Sheet 11of 14
SizeDocument Number
REV
B870521682-200
2.1
Title
GENERAL PURPOSE I/O AND APC
PC87317 EVALUATION BOARD
NATIONAL SEMICONDUCTOR
1 2
R57
100K
1 2
R68
100K
N/A
(ON CHIP 1M PULL-UP)
21C54
0.1U
nSWITCH
nRING
nSWITCH
nRING
VCCH
VCCH
SWITCH
1
2
R67
10K
1
2 4 3
SW3
POWER
CONNECTOR
ADVANCED
CONTROL
GENERAL
PURPOSE I/O 1,2
AND
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
2
J9
HD15X2
0.1"
GPIO1
APC
nONCTL
nLED
GPIO11
GPIO12
GPIO14
GPIO16
GPIO10
GPIO13
GPIO15
GPIO17
GPIO21
GPIO22
GPIO20
GPIO23
EXTVCC
nRING
nSW
VHEXT
LED
ACPI
AC
LD1
LED WITH RES
VCCH
PG.5
nLED
nONCTL
nONCTL
nLED
21C10.1U
VCC
VCCHGND
VCCH
VCC
VCCH
VCCH
SOURCE
EXTERNAL
INTERNAL
1-2
2-3
DEFAULT
P N
C46
22U
13
2JP2
XJP2
VHEXT
STANDBY
POWER
CONNECTOR
GPIO1
13 2
J8
nONCTL
GPIO24
GPIO26
GPIO25
GPIO27
VHEXT
CONNECTOR
GPIO3
3 4 5 6 7 8 9 10
1 2
J5
HD5X2
GPIO31
GPIO32
GPIO34
GPIO36
GPIO30
GPIO33
GPIO35
GPIO37
P N
C40
22U
21C20.1U
PG.5
EXTVCC
GPIO3[0..7]
GPIO1[0..7]
GPIO2[0..7]
EXTVCC
GPIO_APC.SCH
NA
TIO
NA
L S
EM
ICO
ND
UC
TO
R
PC
87351 B
AS
E B
OA
RD
![Page 76: SuperI/O PC87351EB Reference Manual€¦ · 2.6 SOFTWARE CONFIGURATION ... • PC87351 hardware configuration • Floppy Disk Controller (FDC), up to 1 MB/sec ... TP1 TP2 TP4 RN2](https://reader034.fdocuments.us/reader034/viewer/2022051814/60379b3a2bfc7f12af3f9b5e/html5/thumbnails/76.jpg)
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Date: April 10, 1997Sheet 12of 14
SizeDocument Number
REV
B870521682-200
2.1
Title
PS/2 CONNECTORS
PC87317 EVALUATION BOARD
NATIONAL SEMICONDUCTOR
PS/2
8
3
6
1
4
2
5
7 9J7
CON-MDIN-6P
MINI-DIN
1 2
R59
10K
1
2L4
BLM31A02PT
1
2
L5
BLM31A02PT
KBCLKC
VCC
1 2
R60
10K
KBCLK
PS1
VCC
PG.5
1 2
R62
10K
PS[1..4]
KBDAT
PS2
VCC
EMI FILTERS
1
2
L6
BLM31A02PT
1 2
R61
10K
KBDATC
KBDVCC
VCC
21C49
330P
21C48
330P
21C47
0.1U
KEYBOARD
CONNECTOR
PS/2
CONNECTOR
MOUSE
8
3
6
1
4
2
5
7 9J6
CON-MDIN-6P
MINI-DIN
21C52
330P
21C51
330P
21C50
0.1U
1
2L1
BLM31A02PT
1
2
L2
BLM31A02PT
1
2
L3
BLM31A02PT
MCLKC
MDATC
MOUVCC
PG.2
VCC
GND
EXTVCC
MCLK
MDAT
PS3
PS4
VCC
PS2.SCH
NA
TIO
NA
L S
EM
ICO
ND
UC
TO
R
PC
87351 B
AS
E B
OA
RD
![Page 78: SuperI/O PC87351EB Reference Manual€¦ · 2.6 SOFTWARE CONFIGURATION ... • PC87351 hardware configuration • Floppy Disk Controller (FDC), up to 1 MB/sec ... TP1 TP2 TP4 RN2](https://reader034.fdocuments.us/reader034/viewer/2022051814/60379b3a2bfc7f12af3f9b5e/html5/thumbnails/78.jpg)
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Date: April 10, 1997Sheet 13of 14
SizeDocument Number
REV
B870521682-200
2.1
Title
KBC AND RTC CONNECTORS
PC87317 EVALUATION BOARD
NATIONAL SEMICONDUCTOR
PG.5
PG.4
PAL
PG.4
21C65
0.1U
1 2R79
1K
RXD[0..7]
RTCPRES
KBCPRES
IRQ[1..15]
RXD[0..7]
IRQ8
RTCPRES
KBCPRES
IRQ1
1 2 3 4 5 6 7 8 916
17
18
19
20
21
22
23
24
3 4 5 6 7 8 9101112131415161718192021222324
1 2
J3
HD12X2
1
2
R80
100R
1
2
R75
100R
IRQ8
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RTCV
PINOUT
RTC IC
AD0
4
AD1
5
AD2
6
AD3
7
AD4
8
AD5
9
AD6
10
AD7
11
MOT
1
CS
13
AS
14
R/W
15
DS
17
RST
18
IRQ
19
SQW
23
VCC
24
GND
12
NC
2
NC
3
NC
16
NC
20
NC
22
NC
21
DS1287
DIP24
THIS CONNECTOR IS NEEDED
REAL-TIME CLOCK CHIP.
RTC
SOCKET ON THE MOTHERBOARD’S
CONNECTOR
PROCEED AS FOLLOWS :
1. REMOVE THE ORIGINAL DS1287
CHIP (OR EQUIVALENT) AND REPLACE
FOR EVALUATION PURPOSES ONLY.
CONNECT IT TO THE 24-PIN DIP
KBCLK-IN
PS/2 SYSTEM
FUNCTIONALITY
2. CONNECT J3 TO THE ABOVE
SOCKET USING THE SUPPLIED CABLE.
3. PIN 1 (BROWN COLOR) OF THE
CABLE MUST BE CONNECTED TO PIN 1
OF J3 AND PIN 1 OF THE SOCKET.
IT WITH A 24-PIN DIP SOCKET.
MC146818
RTC PINOUT
DS1287
PINOUT
KBC IC/
MCLK-IN
KBDAT-OUT
PS/2 SYSTEM
FUNCTIONALITY
X1
2
X2
3
RESET
4
T0
1
T1
39
A0
9
CS
6
SS
5
RD
8
WR
10
D0
12
D1
13
D2
14
D3
15
D4
16
D5
17
D6
18
D7
19
EA
7
PROG
25
P10
27
P11
28
P12
29
P13
30
P14
31
P15
32
P16
33
P17
34
P20
21
P21
22
P22
23
P23
24
P24/OB
35
P25/BF
36
P26/DRQ
37
P27/DAK
38
SYNC
11
VCC
40
VDD
26
VSS
20
8042
DIP40
1 239
40
10
11
12
13
14
15
ALL UNAVAILABLE
SIGNALS ARE
PULLED UP.
234567891 0
1
RN1
SIP10
9X1K
21
C64
0.1U
1 2 3 4 5 6 7 8 910111213141516171819202122232425262728293031323334353637383940
J4
HD20X2
RXD6
RXD7
KBCV
VCC
10K PULL-UPS
ON P20, P21
21C63
0.1U
1 2
R77
10K
1 2
R78
10K
1 2
R76
1K
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
VCC
VCC
SINCE THEY ARE
OPEN-DRAIN.
P17
P16
P12P20
P21
K3
K2
K1
3 4 5 6 7 8 9 10
11
12
13
14
27
28
29
30
31
32
33
34
35
36
37
38
RXD0
RXD1
RXD2
P27
P26
IRQ1
P17
P16
P15
P14
P13
P12
P11
P10
SA2
KBCLK-OUT
IRQ12
IRQ1
MDAT-IN
KBDAT-IN
KBD
CONNECTOR
THIS CONNECTOR IS NEEDED
SOCKET ON THE MOTHERBOARD’S
PROCEED AS FOLLOWS :
CHIP (OR EQUIVALENT) AND REPLACE
2. CONNECT J4 TO THE ABOVE
SOCKET USING THE SUPPLIED CABLE.
3. PIN 1 (BROWN COLOR) OF THE
CABLE MUST BE CONNECTED TO PIN 1
IT WITH A 40-PIN DIP SOCKET.
KEYBOARD CONTROLLER CHIP.
1. REMOVE THE ORIGINAL 8042
FOR EVALUATION PURPOSES ONLY.
CONNECT IT TO THE 40-PIN DIP
OF J4 AND PIN 1 OF THE SOCKET.
8042 MICROCONTROLLER
PINOUT
MCLK-OUT
MDAT-OUT
GATE-A20
SYS-RST
15
16
17
18
19
20
21
22
23
24
25
26
RXD3
RXD4
RXD5
RXD6
RXD7
P23
P22
P21
P20
PG.5
VCC
GND
K[1..5]
P21
P20
K5
K4
VCC
KBC_RTC.SCH
NA
TIO
NA
L S
EM
ICO
ND
UC
TO
R
PC
87351 B
AS
E B
OA
RD
![Page 80: SuperI/O PC87351EB Reference Manual€¦ · 2.6 SOFTWARE CONFIGURATION ... • PC87351 hardware configuration • Floppy Disk Controller (FDC), up to 1 MB/sec ... TP1 TP2 TP4 RN2](https://reader034.fdocuments.us/reader034/viewer/2022051814/60379b3a2bfc7f12af3f9b5e/html5/thumbnails/80.jpg)
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Date: April 10, 1997Sheet 14of 14
SizeDocument Number
REV
B870521682-200
2.1
Title
TEST CONNECTORS
PC87317 EVALUATION BOARD
NATIONAL SEMICONDUCTOR
W65
W55
W66
W56
W45W46
XU4
SOCKET-160
PQFP160-SMD-SMD
VCCVCC
VCCVCC
VCC
GND
VCC
W61
W51
W62
W52
W63
W53
W64
W54
W41W42W43W44
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40 XJ4B
HD40X1
0.05" FEM
N/A
S77
S78
S79
S80
VCCVCCVCCVCC
VCCVCCVCCVCC
1
2R85
SPAREVDD
12
34
56
78
91 0
1 11 2
1 31 4
1 51 6
1 71 8
1 92 0
2 12 2
2 32 4
2 52 6
2 72 8
2 93 0
3 13 2
3 33 4
3 53 6
3 73 8
3 94 0
XJ4C
HD40X1
0.05" FEM
N/A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
XJ4D
HD40X1
0.05" FEM
N/A
S121
S122
S123
S124
VDD
1
2R86
SPARE
S125
S126
S127
S128
S129
S130
S131
S132
S133
S134
S135
S136
S137
S138
S139
S140
S141
S142
S143
S144
S145
S146
S147
S148
VDD
1
2R84
SPARE
VDD
WIRE WRAP AREA
GND
VCC
GND
W31W32W33W34
W21
W11
W22
W12
W23
W13
W24
W14
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
S74
S75
S76
VCCVCCVCCVCC
XJP1
SOCKET-16
DIP16 TH
FOR JP1
XU6
SOCKET-24
DIP24 TH
FOR PAL
W35W36
W25
W15
W26
W16
VCCVCC
(X-TAL OSC.)
LB1
LABEL S/N
M1
PCB
PC87317EB
M2
BRACKET DB25/9
M3
TYRAP-99MM
LB2
LABEL REV A
S41
S42
S43
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PC87351EB Reference Manual EXTENSION BOARD SCHEMATIC DIAGRAMS B-1
Appendix B
EXTENSION BOARD SCHEMATIC DIAGRAMS
The following pages contain the schematics diagrams for the PC87351EB ex-tension board.
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17
18
19
20
21
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25
26
27
28
29
30
31
32
33
34
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37
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GE
PA
GE
22
GP
IO1
GP
IO2
PM
E
VS
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ED
PA
GE
2
PA
GE
2
VD
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PA
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2
PA
GE
2
8705
2169
4-10
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1
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44
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8
Title
Size
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FAN
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EL
GP
IO10
GP
IO11
GP
IO12
GP
IO13
GP
IO14
GP
IO15
GP
IO16
12V
GP
IO21
GP
IO22
GP
IO20
PM
E1/
nRIN
GP
ME
2/nS
US
P
GP
IO11
_AG
PIO
12_A
GP
IO11
_B
GP
IO13
_B
GP
IO15
_AG
PIO
16_A
GP
IO14
_BG
PIO
15_B
GP
IO16
_B
GP
IO13
_A
GP
IO1
0_
A
GP
IO1
0_B
GP
IO1
2_B
GP
IO1
4_
A
GP
IO17
PN
F
FA
NO
UT
0
FAN
OU
T1
12
V
nPW
UR
EQ
VD
D
VD
D
VS
B
VD
D
VB
AT
VS
B
VS
B
VD
D
VD
D
VD
D
VD
DV
DD
C
VD
DC
12V
LD
1
12
LD
3
12
R4
510R
1 2G
ND
OU
T
VC
CN
CU7
33M
R1 10
K
1 2
JP1
11
2R
951
0R
1 2
JP5
1 32
C1
510
U
P N
JP8
132
ND
S99
42
U2
S1
1
G1
2
S2
3
G2
4D
2-2
5D
2-1
6D
1-2
7D
1-1
8
R1
420
R
1 2
R1
320
R
1 2
R1
21K
1 2
R1
520
R
1 2
J2
12
TP
21
TP
11
TP
31
TP
41
C7
0.1u
21
C1
0.1u
21
C8
0.1u
21
C5
0.1u
21
C4
0.1u
21
C1
30.
1U
21
C1
20.
1U
21
XJP
11
XJP
12
XJP
13X
JP1
5X
JP1
6X
JP1
7
XJP
18
XJP
19
XJP
20
XJP
21
XJP
22
XJP
1X
JP2
XJP
3X
JP4
XJP
5X
JP6
XJP
7X
JP8
XJP
9X
JP1
0
XJP
14
PC
B
M1
PC
B2
J1
3 4 5 6 7 8 9 10
1 2
J3
3 4 5 6 7 8 9 10
1 2
LD
2
12
R7
510R
1 2
XJP
23
XJP
24
U5 74
LV
X3
L3
83
nBE
1
C0
2A
03
C2
10
A1
7
D0
5
D1
9
D2
15
D3
19
A2
11
A3
17
C1
6
C3
16
C4
20
D4
23
A4
21
B0
4
B1
8
B2
14
B4
22
B3
18
GN
D1
2
VC
C2
4
BX
13
U3 74
LV
X3
L3
83
nBE
1
C0
2A
03
C2
10
A1
7
D0
5
D1
9
D2
15
D3
19
A2
11
A3
17
C1
6
C3
16
C4
20
D4
23
A4
21
B0
4
B1
8
B2
14
B4
22
B3
18
GN
D1
2
VC
C2
4
BX
13
J4
3 4 5 6 7 8 9 10
1 2
JP10
1 2
R1
010
K
1 2
JP13
12
XJP
25
C9
0.1u
21
C1
410
u
21
C3
10
u
21
C1
00
.1u
21
C1
10
.1u
21
C1
61
0u
21
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PC87351EB Reference Manual BILL OF MATERIALS C-1
Appendix C
BILL OF MATERIALS
Description Location Qty
Base Board
74LVX3L384A SMD-TSOP24 BUS SWITCH 3 OR 5V U10, U5 2
PAL22V10 DIP24 7.5NS, 0.3" U6 1
74ACTQ32 SMD-SO14S QUAD OR GATES U7 1
74ACT00 SMD-SO14S QUAD NAND GATES U8 1
DS14185M SMD-SO20W +/-12, +5V UART DRV/RCV U1, U2 2
DS14C89A SMD-SO14S +5V UART RECEIVER U3 1
33R SMD-1206 1/4W 5%
R1, R2, R3, R4, R5, R6, R7, R8,R9, R10, R11, R12, R13, R14,R15, R16, R19, R20, R21, R22,R23, R24, R25, R26, R27, R28,R29, R34
28
100R SMD-1206 1/4W 5% R30, R31, R58, R75 4
1K SMD-1206 1/4W 5% R76 1
4.7K SMD-1206 1/4W 5%R42, R43, R44, R45, R46, R47,R48, R49, R50, R51, R52, R53,R54, R55, R56
15
10K SMD-1206 1/4W 5%R32, R33, R59, R60, R61, R62,R77, R78
8
10K DIP 1/4W 5% R41 1
150K SMD-1206 1/4W 5% R35, R36, R37, R38, R39 5
SPARE SMD-1206 1/4W SPARE FOOTPRINT R82, R83, R84, R85, R86 5
RES-NET-COM-9 SIP10 9X1K SIP10, 2%, 1/8W RN1 1
RES-NET-COM-5 SIP6 5X1K SIP6, 5%, 1/8W RN2 1
RES-NET-ISOL-8 DIP16 8X10R DIP16, 0.3”, 1%, 1/8W JP1 1
47P SMD-0805 50V C-NP, CER NPO, 10%, C33 1
200P SMD-0805 50V C-NP, CER NPO, 10%C66, C67, C68, C69, C70, C71,C72, C73, C74, C75, C76, C77,C78, C79, C80, C81
16
330P SMD-0805 50V C-NP, CER NPO, 10%C6, C7, C8, C9, C10, C11, C12,C13, C14, C15, C16, C48, C49,C51, C52
15
680P SMD-0805 50V C-NP, CER NPO, 10% C17, C18 2
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C-2 BILL OF MATERIALS PC87351EB Reference Manual
0.1U SMD-1206 50V C-NP, CER X7R, 10%
C1, C2, C19, C21, C22, C23, C24,C26, C28, C30, C31, C32, C34,C36, C37, C38, C39, C41, C43,C44, C47, C50, C55, C56, C57,C59, C60, C61, C62, C63, C64
31
22U SMD-6032 16V C-POL, TANT, 10%C25, C27, C29, C35, C40, C42,C45, C46, C58
9
BLM31A02PT SMD-1206 200mA INDUCTOR, EMIBEAD
L1, L2, L3, L4, L5, L6 6
CRYSTAL-OSC DIP14 48MHz 100PPM, CMOS, 5V U9 1
CON-MDIN-6P MINI-DIN 6 PINS + 3 SHIELD PINS J7, J6 2
CON DB9 FEMALE TH-RA PCB J12 1
CON DB25 FEMALE TH-RA PCB J13 1
CON 3 PIN POL 2.5MM HD LOCK POLARIZED J8 1
HD1X1 0.1” HEADER, 1 PIN TP2, TP3 2
HD2X1 0.1” HEADER, 2 PINS JP4 1
JUMPER-COVER-2PIN, BLACK XJP2, XJP4 2
HD3X1 0.1” HEADER, 3 PINS JP2 1
HD40X1 0.05” FEM HEADER, 40 PINS XJ4D, XJ4C, XJ4B, XJ4A 4
HD5X2 0.1” SHROUDED HEADER, 10 PINS J1, J2 2
HD17X2 0.1” SHROUDED HEADER, 34 PINS J10 1
HD20X2 0.1” SHROUDED HEADER, 40 PINS J4 1
HD5X2 FEM HD 0.05”X0.1” XJ4E 1
SOCKET-24 DIP24, O.3” XU6 1
SW-SPDT-MOM 0.1” 5P 2 SHIELD PINS SW4 1
FUSE-SOCKET SMD 2A SOCKET + FUSE SLOWBLOW
XF1 1
BATT-3PIN COIN 3.0V LITHIUM CELL 380mAH BT1 1
PCB PC87317EB PRINTED CIRCUIT BOARD M1 1
BRACKET DB25/9 IBM PC-AT M2 1
LABEL REV A REV LET ‘A’ LB2 1
LABEL S/N LB1 1
Extension Board
PC87351-XXX/ SMD-PQFP128 SUPERI/O U1 1
SI9942 DUAL MOSFET U2 1
CRYSTAL-OSC DIP14 33MHz 50PPM, TTL, 5V U7 1
74LVX3L383 SMD-TSOP24 BUS CHANGER 3 OR 5V U3, U5 2
Description Location Qty
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PC87351EB Reference Manual BILL OF MATERIALS C-3
74LVX3L384A SMD-TSOP24 BUS SWITCH 3 OR 5V U4, U6 2
ispLSI1032E-100LT CPLD U8 1
SW-DP-NO-NC-X2 DIP4 DIPSWITCHX2 SW1 1
SOCKET-OSC 14/6 DIP14 6PINS ROUND XU7 1
HD3X1 0.1” HEADER, 3 PINS JP5, JP8, JP12, JP17, JP24 5
HD8X1 0.1” HEADER, 8 PINS J10 1
HD2X1 0.1” HEADER, 2 PINSJ2, JP4, JP7, JP10, JP11, JP13,JP15, JP16, JP18, JP19, JP20,JP21, GP22, JP23, JP25
15
HD5X2 0.1” SHROUDED HEADER, 10 PINS J1, J2, J3 3
HD3X2 0.1” SHROUDED HEADER, 6 PINS JP14 1
HD4X2 0.1” SHROUDED HEADER, 8 PINS JP1, JP2, JP3, JP6, JP9 5
HD5X2 FEM HD 0.05”X0.1” J5 1
HD40X1 0.05” MALE J7, J8, J9 3
HD30X1 0.05” MALE J6 1
HD1X1 0.1” HEADER, 1 PIN TP1, TP2, TP3, TP4 4
JUMPER-COVER-2PIN, BLACK
XJP1, XJP2, XJP3, XJP4, XJP5,XJP6, XJP7, XJP8, XJP9, XJP10,XJP11, XJP12, XJP13, XJP15,XJP16, XJP17, XJP18, XJP19,XJP20, XJP21, XJP22, XJP23,XJP24, XJP25
24
JUMPER-COVER-2PIN-X2, BLACK XJP14 1
SOCKET-128 PQFP128-SMD-SMD XU1 1
10K SMD-1206 1/4W 5% R1, R2, R3, R5, R8, R10, R11 7
510R SMD-1206 1/4W 5% R4, R7, R9 3
20R SMD-1206 1/4W 5% R13, R14, R15 3
1K SMD-1206 1/4W 5% R6, R12 2
RES-NET-COM-7 SIP8 7X1K SIP8, 2%, 1/8W RP1 1
0.1U SMD-0805 50V C-NP, CER X7R, 10%C1, C4, C5, C6, C7, C8, C9, C10,C11, C12, C13
11
10n SMD-0805 50V C-NP, CER X7R, 10% C2 1
10U SMD-6032 20V C-NP, 10% C3, C14, C15, C16
LABEL REV A REV LET ‘A’ LB1 1
RED LED SQUARE LD1, LD2, LD3 3
Description Location Qty
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PC87351EB Reference Manual PAL EQUATIONS D-1
Appendix D
PAL EQUATIONS
The PAL equations of the PC87351EB PLD - XU6:
”************************************************************************“* NATIONAL SEMICONDUCTOR CORPORATION *“* *“* *“* Revision Date Description *“* --------------------------------------------------- *“* 0.1 Feb 21, 1997 PC87351EB EVALUATION BOARD *“* Author: Theodor Iacob *“*************************************************************************
module M351EB
title ‘351EB XBUS/ISA buffer control logic ‘
M351EBdevice‘P22V10’;
declarations
“INPUTS“======
SA0,SA1,SA2,SA3,SA4,SA5 pin 1,2,3,4,5,6;SA6,SA7,SA8,SA9,SA10,SA11 pin 7,8,9,10,11,13;NCSIN pin 17;“ NCSIN = SA15 # SA14 # SA13 # SA12
“ delivered by external logicAEN pin 16;NIORD pin 15;NIOWR pin 14;CFG0A pin 21;KBCPRES pin 22;RTCPRES pin 23;
“OUTPUTS“=======NISAENBL pin 20;NXENBL pin 19;PAEN pin 18;
ADDR12 = [SA11,SA10,SA9,SA8,SA7,SA6,SA5,SA4,SA3,SA2,SA1,SA0];ADDR11 = [SA10,SA9,SA8,SA7,SA6,SA5,SA4,SA3,SA2,SA1,SA0];
KBC_ACCESS= !NCSIN & (( ADDR12 == ^h060 ) # ( ADDR12 == ^h064 ));RTC_ACCESS= !NCSIN & (( ADDR12 == ^h070 ) # ( ADDR12 == ^h071 ));
H,L,X,C = 1, 0 , .X. , .C.;
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D-2 PAL EQUATIONS PC87351EB Reference Manual
equations
!NXENBL = (( KBCPRES & KBC_ACCESS ) #“KBC cable connected AND“KBC address match OR
( RTCPRES & RTC_ACCESS ) “RTC cable connected AND) & “RTC address match OR
!AEN & “AEN must be low AND(!NIORD # !NIOWR ); “read OR write cycle
!NISAENBL= (!NIORD # !NIOWR ) & “read or write cycle AND(AEN # “ for DMA cycles: AEN is High
“ AND any addr. OR“ for IO cycles:
(!AEN & “AEN is LOW AND(!KBC_ACCESS & “there is not a KBC access AND
!RTC_ACCESS“there is not a RTC access.)
));
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PC87351EB Reference Manual INDEX-1
A
Advanced Power Controller 1-3and 4-6AT connector 3-1
B
base board layout 1-5
C
configuration program 2-14connector (on base)
AT 4-6FDC 4-4ISA XT 4-6J2 4-4KBC 4-2KBD 4-3, 4-4mouse 4-3Parallel Port 4-6SERIAL1 4-2SERIAL2 4-2
connector (on extension)fan 4-7GPIO1 4-7GPIO2 4-7ISP 4-8PME 4-6
D
data buffers 1-2DS14185 3-4
E
EasyReg 2-14ECP terminations 3-5EMI filter 3-4, 3-9extension board layout 1-6
F
FanController 3-5
FDC connector 4-4Floppy Disk Controller 1-2
G
GATEA20 3-9
I
IRTX signal 3-4
J
J3 3-4J4 3-4J5 3-9J8 3-4J9 3-5jumper (on base)
J1 4-2J10 4-4J12 4-5J13 4-6J2 4-2J4 4-2J6 4-3J7 4-4J8 4-4
jumper (on extension)J1 4-6J10 4-8J2 4-7J3 4-7J4 4-7
K
KBC connector 4-2KBC IRQ12 3-9KBD connector 4-4KBDAT 3-9KBDCLK 3-9Keyboard Controller 1-3
INDEX
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INDEX-2 PC87351EB Reference Manual
M
MCLK signal 3-9MDAT signal 3-9mouse connector 4-3
P
P2 4-6parallel port 1-2parallel port block 3-5Parallel Port connector 4-6power consumption 4-8
R
reset cycle 2-14RI1 3-4RI2 3-4
S
Standby 4-4SW1 2-6
T
TC signal 3-1
U
UART1 block 3-4
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