Superconductive Logic Circuits Constructed by the Use of TwoThresholds of SQUID

Masahiro Kawai,1 Yoichiro Sato,2 Hiroto Kagotani,3 and Takuji Okamoto4

1Department of Electronics and Computer Engineering, Tsuyama National College of Technology, Tsuyama, 708-8509 Japan

2Faculty of Computer Science and System Engineering, Okayama Prefectural University, Soja, 719-1197 Japan

3Faculty of Engineering, Okayama University, Okayama, 700-8530 Japan

4Faculty of Engineering, Okayama University of Science, Okayama, 700-0005 Japan

SUMMARY

This paper proposes a method for constructing super-conductive logic circuits by actively using two thresholdsin a superconducting quantum interference device(SQUID). First, it is demonstrated that the input–outputcharacteristics of a SQUID with multiple inputs can berepresented as a two-threshold logic function. Next, aSQUID structure is shown in which all of the input currentshave the same significance and the threshold current can bevaried without varying the characteristics of the Josephsonjunction. Each input is weighted by adjusting the internalimpedance rather than the input current, and the SQUIDthresholds are varied using the value of the steady currentapplied to an additional input. Finally, it is explained thatwhen logic functions of two to four variables are realizedusing such SQUIDs, the number of logic functions that canbe realized with a single SQUID is much greater than whenan existing method is used, and the operating regions arereduced only slightly. © 2005 Wiley Periodicals, Inc. SystComp Jpn, 36(2): 42–50, 2005; Published online in WileyInterScience (www.interscience.wiley.com). DOI10.1002/scj.20136

Key words: magnetically coupled superconductivelogic circuit; two-threshold function; SQUID.

1. Introduction

Superconductive logic circuits are expected as one ofthe means for realizing the further high-speed logic circuits.Depending on the type of control used for the Josephsonjunction, superconductive logic circuits can be divided intomagnetically coupled circuits and current injection circuits.The former, although responsible for a circuit scale increasesince the size of superconducting quantum interferencedevices (SQUIDs) as basic constituent elements is large, aresuperior to the latter in terms of input–output separability,sensitivity, stability, and other aspects [1]. In view of this,we believe that it is extremely important to study themethods of constructing magnetically coupled supercon-ductive logic circuits (hereafter termed “logic circuits,”unless such a reference is confusing) with a minimal re-quired number of SQUIDs in order to make such circuitsmore practical.

Methods of constructing logic circuits include thoserealized on the logic gate level [2, 3] and those realized onthe SQUID level [4–7], but the latter are preferred from thestandpoint of the required number of SQUIDs. In the par-

© 2005 Wiley Periodicals, Inc.

Systems and Computers in Japan, Vol. 36, No. 2, 2005Translated from Denshi Joho Tsushin Gakkai Ronbunshi, Vol. J86-D-II, No. 12, December 2003, pp. 855–862

42

ticular case of Ref. 6, the fact that a SQUID is applicable tothe realization of threshold functions is advantageouslyutilized to provide a method for constructing logic circuitswith a minimal required number of SQUIDs.

A SQUID has two thresholds, and the number oflogic circuits capable of representing threshold functionsincreases with an increase in the number of thresholds [8];thus, logic circuits can be realized with a smaller numberof SQUIDs if the two thresholds are used efficiently. As faras the authors know, however, no methods of constructinglogic circuits with two thresholds have so far been pro-posed. In view of this, this paper provides a method forconstructing logic circuits with a minimum required num-ber of SQUIDs by actively using the two thresholds of aSQUID.

If it were possible to freely select the two thresholdsof a SQUID for each logic function, all of the logic func-tions capable of being represented as two-threshold logicfunctions could be realized with a single SQUID, but thisapproach is unsuitable for normalizing logic circuits be-cause the characteristics of the Josephson junction in aSQUID are different for each logic function. In view of this,we note that the effective thresholds of a SQUID can bevaried without varying the characteristics of the devicewhen an input terminal is added to the SQUID and a steadycurrent is applied, and a goal is set to increase the numberof logic functions that can be realized with SQUIDs havingthe same characteristics. In addition, logic functions thatcannot be realized with a single SQUID are realized by theseries or parallel connection of multiple SQUIDs havingthe same characteristics.

It is shown in Section 2 that the logic functions of asingle SQUID with multiple inputs can be represented astwo-threshold logic functions. It is demonstrated in Section3 that the input current and output current of a SQUID thatcorresponds to logic 1 have equal values, and a basic struc-ture is presented of a SQUID in which the thresholds canbe varied while the characteristics of the Josephson junctionremain fixed. Finally, the possibility of realizing all possibletwo- to four-variable logic functions on the basis of thisbasic structure is studied in Section 4, and we describe howthe use of two thresholds and the introduction of a steadycurrent affect the operating regions and the reduction in therequired number of SQUIDs.

2. Logic Circuits Constructed Using TwoThresholds

2.1. Use of thresholds in conventional logiccircuits

When an m-input SQUID gate is used as a switchingelement, the circuit structure which is shown in Fig. 1(a) is

used conventionally [6]. G and R designate the SQUID anda load resistance, respectively. iB, iIk (1 ≤ k ≤ m), and iO arethe bias current, input current, and output current, respec-tively.

Figure 1(b) shows the threshold characteristics of aSQUID. The horizontal and vertical axes represent the sumof input currents iC (= Σk=1

k=m iIk) and the bias current iB, re-spectively. The SQUID is in a superconducting state if bothiC and iB are within the hatched area, and is otherwise in avoltage state. If, for example, It and Ib are taken to be valuessuch as those shown in the figure and the fixed conditioniB = Ib is set, the SQUID is brought to a voltage state andiO = IbRG / (RG + R)(> 0) if the condition iC ≥ It is main-tained. Here, RG is the internal resistance when G is in thevoltage state. The corresponding iO value is designated asI0 below. In addition, a superconducting state is establishedand iO = 0 if 0 ≤ iC ≤ It.

Correlating iIk with the input logic variable xk andassuming that xk = 0 and xk = 1 will yield iIk = 0 andiIk = Ik. Also, correlating iO with the output logic variable yand assuming that y = 0 and y = 1 will yield iO = 0 andiO = I0. The corresponding m-variable logic function y =f(x1, . . . , xm) realizable with the circuit of Fig. 1(a) will bedefined by the formulas

where D1(f) and D0(f) are sets of groups of logic variablevalues for which the f-value is 1 and 0, respectively. Inaddition, Vm is a set of all m-order groups for which eachof the components is 0 or 1. In other words, the functionsused conventionally are single-threshold functions in whichthe real numbers Ik(1 ≤ k ≤ m) and It designate the weight-ing and threshold values, respectively.

Fig. 1. Threshold characteristics of SQUID.

(1)

(2)

43

2.2. Logic circuit having two thresholds

Not only are the threshold characteristics of a SQUIDapplicable when iC is positive, but they can also be ex-panded to cover the characteristics of negative and positivevalues symmetrical about iC = 0, as shown in Fig. 2. When,for example, It and Ib assume values such as those shown inthe figure, the SQUID assumes a voltage state in cases inwhich iB = Ib and iC ≥ It or iB = Ib and iC ≤ −It, and a super-conducting state in cases in which iB = Ib and −It < iC < It.

When a case of two thresholds is considered, asshown in Fig. 2, Eqs. (1) and (2) can be rewritten respec-tively as

In other words, a SQUID can be used to realize a two-threshold function for which the real number Ik(1 ≤ k ≤ m)is taken to be the weighting, and the two real numbers It and−It are taken to be the thresholds.

When the number of logic variables is fixed, thenumber of logic functions capable of being represented astwo-threshold functions is greater than the number of logicfunctions capable of being represented as single-thresholdfunctions [8].

3. Basic Structure of SQUID for RealizingLogic Functions

3.1. Normalization of input–output current

Since the output of a logic circuit is generally an inputof another logic circuit, it is appropriate to assume that an

input current that corresponds to xk = 1(1 ≤ k ≤ m) is a valueI0 that is the same as the output current. When, however,this assumption is accepted without any modifications, allof the Ik in Eqs. (3) and (4) become I0 or –I0; that is, all ofthem have the same weight, and the number of types ofrealizable logic functions decreases dramatically. In viewof this, normalization is performed as described below inorder to realize a variety of weights in an equivalent manner.

Figure 3 shows the circuit structure for normaliza-tion. The G inside the broken line is a SQUID composed ofa superconducting closed circuit that contains two Joseph-son junctions and an impedance L0, and of a supercon-ducting input line that contains an impedance Lj(1 ≤ j ≤ n)for magnetic coupling with L0 [6]. The current ij applied toG has one-to-one correspondence with the input currentxjI0 supplied to the circuit. CONT is a circuit whose func-tion is to control the direction (represented as positive andnegative current values when applied in the direction of thearrow and in the opposite direction, respectively) in whichthe input current that enters the circuit is applied to G.

The ij-value, which may be 0 or I0, varies the degreeto which the superconducting closed circuit is affectedwhen L0 is fixed and Lj is varied. The ij

e-value of ij, repre-sented in terms of its value at L0:Lj = 1:1, can be arbitrarilyset by adjusting the Lj-value in an appropriate manner, andcan be represented as

where wj = Lj / L0.Based on the above, the logic function f realized

using Fig. 3 finally becomes an n-variable, two-thresholdlogic function defined by

Fig. 2. Extended threshold characteristics.

(3)

(4)

Fig. 3. Construction of two-threshold logic circuit.

(5)

(6)

44

Following is a description of a group of logic func-tions realizable with the circuit of Fig. 3, that is, theirgrouping into equivalence classes, when L1 to Ln are fixedat a certain value. The functions can be divided into suchequivalence classes by combining the following three op-erations: (1) negation of a logic function, (2) substitution ofa logic variable, and (3) negation of several logic variables[9]. Among these, (1) can be easily realized in the followingmanner. If iB = Ib, then the gate current iG of G in Fig. 3is Ib or Ib − I0 in accordance with iO = 0 or iO = I0, respec-tively. The R-value is usually sufficiently small in com-parison with the value of RG (internal resistance when Gis in a voltage state), so Ib − I0 ≅ 0. Consequently, theoutput function for a case in which iG is taken to be theoutput current will be the negation of a logic func-tion for which iO is the output current. In other words,f (x1, . . . , xi, . . . , xj, . . . , xn

_______________________ can be realized by replacing

the output current with the gate current of the SQUID,assuming that the logic function f(x1, . . . , xi, . . . ,xj, . . . , xn) can be realized with the circuit of Fig. 3. InEq. (2), the logic function f(x1, . . . , xj, . . . , xi, . . . , xn) inwhich, for example, xi and xj are transposed can be readilyrealized by transposing the input xiI0 and xjI0 of the CONT.By contrast, realization of Eq. (3) requires adding a SQUIDin order to apply the negation of a logic variable to thecircuit, and is thus linked to an increase in the requirednumber of SQUIDs.

In view of the above, the emphasis in this paper isplaced on (1) function negation and (2) variable transposi-tion, which are approaches not linked to an increase in therequired number of SQUIDs; all of the logic functions inquestion are divided into equivalence classes; and an at-tempt is made to determine weights w1, . . . , wn for eachrepresentative function of every equivalence class. In deter-mining the weights, it is assumed for the sake of simplicitythat It = I0 without any loss of generality.

3.2. Realization of threshold variationfunctionality by introduction ofsteady current

The question of whether an n-variable logic functiongiven by the structure in Fig. 3 can be realized duringnormalization as in Section 3.1 is ultimately a question ofwhether w1, . . . , wn can be determined so that Eqs. (6) and(7) are satisfied.

To allow a given logic function f to be realized withEqs. (6) and (7) on the assumption that the group x1, . . . ,xn represents coordinates (x1, . . . , xn) in an n-dimensional

space, it is necessary, in a geographical sense, forW(a1, . . . , an) ∈ D0(f) to be positioned in a space enclosedbetween the two parallel planes (straight lines when n = 2)Σj=1

n wjxj = 1 and Σj=1n wjxj = −1 in the n-dimensional space,

and for W(a1, . . . , an) ∈ D1(f) to be positioned outside thisspace. For example, the three-variable logic functionx1x2x3 + x1

__ x2

__ + x2

__ x3

__ can be geographically represented as

shown in Fig. 4(a). The symbols ! and A orrespond to the(x1, x2, x3) contained in D0(f) and D1(f), respectively. Forthis logic function, only planes such as those hatched inFig. 4(a) can be selected as the two aforementioned planes,and the functions cannot be realized with the structure(single SQUID) of Fig. 3. This is because the two planeshave the limitation that they are always point symmetricabout the origin ((x1, . . . , xn) = (0, . . . , 0)), that is, that theintercepts with the coordinate axes always have differentsigns between the two planes.

The two planes should be selected as shown inFig. 4(b) in order to realize such a logic function with asingle SQUID. In other words, the It in Eq. (6) and the It inEq. (7) can be set to effectively different values withoutchanging the SQUID characteristics. This is achieved bymethods [4, 6] in which a constant term—a steady cur-rent—is introduced on the left-hand side of Eqs. (6) and (7).

Figure 5 shows a circuit structure obtained by addinga steady current to the circuit in Fig. 3. Here, in+1 is thesteady current, and it is supplied by providing the CONTwith an internal current source (magnitude: I0). The follow-ing expression can be obtained for the in+1

e value of in+1,which is the value obtained when L0:Ln+1 = 1:1:

where wn+1 = Ln+1 / L0. With the introduction of a steadycurrent, Eqs. (6) and (7) are transformed respectively as

(7)

Fig. 4. Graphical representation forx1x2x3 + x1

__ x2

__ + x2

__ x3

__.

(8)

(9)

45

The two planes become wn+1 + Σj=1n wjxj = 1 and

wn+1 + Σj=1n wjxj = −1. These two planes still have point sym-

metry, but because the symmetry origin varies with thevalue of wn+1, the restriction that the intercepts with thecoordinate axes have different signs is no longer applicable.For this reason, planes such as those shown in Fig. 4(b) canbe selected, for example, and the required number ofSQUIDs can be reduced.

4. Examination

4.1. Realizability of logic functions

4.1.1. Two-variable logic function

Single-variable logic functions will be omitted be-cause of their simplicity, and the description will startwith two-variable logic functions. There are 14 two-vari-able logic functions (with the exception of constant func-tions), and they can be divided into the following fivetypes when classed according to the system adopted inSection 3: {x1, x2, x1

__, x2

__}, {x1, x2, x1x2

____}, {x1 + x2, x1 + x2

______},

{x1x2

__, x1

__x2, x1x2

______, x1

__x2

____}, {x1 ⊕ x2, x1 ⊕ x2

______}. Here, the func-

tion indicated at the beginning of each class will be referredto as a representative function, and its realizability will beexamined.

It is assumed that It = I0, n = 2 in Eq. (9). For exam-ple, the positional relation between the four coordinates andtwo straight lines shown by A, ! must be as in Fig. 6 in order

to be able to represent x1 ⊕ x2. Here, the conditionw1x1 + w2x2 + w3 = 1 must be satisfied in the region wherethe segments are x1 = 0 (the range of x2 is (0, 1]) and x2 = 1(the range of x1 is [0, 1)) , and the conditionw1x1 + w2x2 + w3 = −1 must be satisfied in the region wherethe segments are x1 = 1 (the range of x2 is [0, 1)) and x2 = 0(the range of x1 is (0, 1]). This arrangement can be realizedas w1 = 2, w2 = −2, w3 = 0 when the segment centers arepoints of intersection.

A similar study into other representative functionscan make it possible to determine the values w1, w2, and w3.Table 1 shows the typical values w1, w2, and w3 for eachrepresentative function. The above considerations showthat all two-variable logic functions can be realized with asingle SQUID.

4.1.2. Three- and four-variable logic functions

A three-variable logic function can be represented asf(x1, x2, x3) = ∨J=0

7 f (J) ⋅ mJ if f(J) can be written instead off(a1, a2, a3) when a group composed of the values of threelogic variables (a1, a2, a3) ∈ V3 is assumed to be a binarynumber, and the decimal representation thereof is J. Here,mJ is the minimum term, equal to 1 for (a1, a2, a3), whichis represented as J in decimal notation. This can be used toassume that N = ΣJ=0

7 f (J) × 27−J and to simplify

(10)

Fig. 5. Construction of two-threshold logic circuit bythe use of a steady current.

Fig. 6. Graphical representation for x1 ⊕ x2.

Table 1. Realized examples of two-variable logicfunctions

46

f(x1, x2, x3), expressing it as fN. For example, a logic func-tion for which f(110) alone is 1 can be represented as f2.

Among the three-variable logic functions, there aretwo constant functions and 38 logic functions that can beconsidered to have essentially two variables or less. Thelatter group of logic functions can be realized in the samemanner as two-variable logic functions, except that theinput to the CONT is varied in an appropriate manner.

Also, the remaining 216 three-variable logic func-tions can be classed in the same manner as in Section 3.2into 33 categories whose representative functions aref1, f2, f6, f7, f8, f9, f11, f14, f22, f23, f24, f25, f26, f27, f30, f31, f40,f41, f42, f43, f44, f45, f46, f47, f61, f62, f104, f105, f106, f107, f110,f111, f126. At this point, a program was created to determinewhether planes such as those that satisfy the conditions ofEqs. (9) and (10) exist for a given logic function; that is, tocalculate coefficients w1, w2, w3, and w4 as solutions of thesystem of inequalities inside the braces {} on the right-handside of Eqs. (9) and (10) for each dimension of V3; and thiswas used to determine whether the 33 representative func-tions could be realized. As a result, w1 to w4 that couldsatisfy Eqs. (9) and (10) were obtained for 31 representativefunctions (except f27 and f105). In other words, it was shownthat the functions can be realized with a single SQUID. Forexample, the typical values of w1, w2, w3, and w4 for f1 =x1x2x3 are 1/3, 1/3, 1/3, and –2/3, respectively.

By contrast, w1, w2, w3, and w4 could not be selectedfor f27 and f105 as long as the selection was premised on thestructure in Fig. 3. However, f27 = x1x2 + x1x3

__ + x2x3 can be

realized through a serial connection of an f81-realizingcircuit and an f2-realizing circuit because the function canbe represented as a logical sum of f2 = x1x2x3

__ and

f81 = x1x3

__ + x2x3. The serially connected circuit configura-

tion is shown in Fig. 7. In the case shown, the f2-realizingcircuit is located at the top, and the f81-realizing circuit islocated at the bottom, but a reverse configuration is alsopossible. Also, f105 can be realized through a serial connec-tion of an f9-realizing circuit and an f40-realizing circuit.

It is apparent from the above that 228 of the three-variable logic functions (a total of 254) other than constantfunctions can be realized with a single SQUID, and that theremaining 26 can be realized with two SQUIDs.

Four-variable logic functions were classed into 456representative functions, the program for three variableswas expanded to include four variables, and this was usedto examine the realizability of the functions with a singleSQUID. A comprehensive study was then conducted todetermine whether any logic function unrealizable with asingle SQUID could be realized as a logical product orlogical sum of two logic functions realizable with a singleSQUID. Realizable functions can be structured in the samemanner as in Fig. 7. A study was then conducted to deter-mine whether the number of logic functions realizable witha single SQUID could be further increased in increments of

one and the result could be configured as a logical productor logical sum. As a result, it was found that the functionsfor which the realistically required number of SQUIDs isone, two, or three amount to 41,206, 20,886, and 3442,respectively, out of the 65,534 functions that exclude con-stant functions. In other words, it was learned that thefunctions could be realized with a maximum of threeSQUIDs.

4.2. Study of the required number of SQUIDs

The effect of using two thresholds was first studied.Table 2 shows the number of SQUIDs required when only

Fig. 7. Circuit configuration for realization of f27.

Table 2. Comparison of the numbers of requiredSQUIDs

47

one threshold is used, and the number of SQUIDs requiredwhen two thresholds are used. The numeral values desig-nate the number of functions that can be realized with thenumber of SQUIDs indicated in the corresponding row. Therequired number of SQUIDs in these results is minimal aslong as the premise involves only a serial or parallel con-nection of the circuits in Fig. 3. Constant functions areexcluded from the consideration. The number of SQUIDsused with a single threshold was determined by a proprie-tary program created to search for planes that linearlyseparate n-dimensional spaces for each function; that is, tocalculate solutions of the system of inequalities of the typeshown in the braces on the right-hand side of Eqs. (1) and(2) for each dimension of Vn. With this program as well, itwas investigated whether logic functions unrealizable witha single SQUID could be constructed as logic products orlogic sums while the logic functions unrealizable withsingle SQUIDs were increased in increments of one in thesame manner as in the case in which two thresholds wereused. As a result, it was learned that the number of logicfunctions realizable with the same number of SQUIDscould be markedly increased by the use of two thresholds.

The effect of the steady current referred to in Section3.2 will be described next. Table 3 shows a comparison ofcases with and without the use of a steady current. In theproprietary program for determining the planes in the n-di-mensional space that satisfies Eqs. (9) and (10), the numberof SQUIDs required when a steady current is not used wasdetermined by assuming that wn+1 = 0. It is apparent fromthe above results that it is more beneficial to use a steadycurrent.

4.3. Effect on operating regions

The circuit in Fig. 5 was studied in relation to oper-ating regions in which the desired logic functionality canbe implemented. The variable circuit parameters are aninput current (I0), bias current (Ib), and SQUID charac-teristics. Of these, the input current originates from theJosephson vibrations and plasma vibrations characteristicof superconducting circuits, and can vary to a greater extentthan other parameters. In addition, the bias current is small

but is affected more easily, and should therefore be studied.Junction critical current, junction gap voltage, and self-in-ductance are believed to be SQUID characteristics, butwhen a specific material is used for the junction, the junc-tion gap voltage varies only slightly and variations in thejunction critical current and self-inductance can be consid-ered as being equivalent to variations in the input current.In view of this, it was decided in this paper to concentrateon the input current and bias current and to investigate theoperating regions. As used in this paper, the term “operatingregion” refers to the range of input currents and bias cur-rents in which the aforementioned logic functionality canbe implemented. Because it is the most widespread, aniobium junction having the characteristics shown in Ta-ble 4 was used for the SQUID junction [10].

Table 5 shows the results of comparing operatingregions obtained using a single threshold and two thresh-olds. The numbers in the left-hand column indicate theratios (%) of operating regions obtained using two thresh-olds in relation to operating regions obtained using a singlethreshold. The numbers in the other columns indicate thenumbers of functions with the corresponding operatingregion ratios. Constant functions are excluded from theconsideration. The results demonstrate that the reduction in

Table 3. Effect of steady current Table 4. Characteristics of a typical SQUID

Table 5. Comparison of operating regions

48

the operating regions for logic functions with a ratio ofapproximately 95% is only about 10%. Also, the reductionin the operating regions becomes more pronounced with anincrease in the number of variables. This is attributed to thefact that an increase in the number of variables reduces thefreedom with which two planes can be selected (see Fig. 4).Consequently, cases in which a reduction in the operatingregions presents a problem should be handled by increasingthe required number of SQUIDs.

Table 6 shows the results of comparing operatingregions obtained with and without the use of a steadycurrent. The numbers in the left-hand column indicate theratios (%) of operating regions obtained using a steadycurrent in relation to operating regions obtained without theuse of a steady current, and the numbers in the othercolumns are the same as in Table 5. The results demonstratethat the reduction in the operating regions for logic func-tions with a ratio of approximately 98% is only about 10%.In this case as well, a reduction in operating regions ishandled in the same way as in Table 5.

5. Conclusions

In this paper, it was noted that a two-threshold logicfunction could be realized with a single SQUID, and amethod was developed for constructing superconductivelogic circuits in which the SQUID thresholds could bevaried while the Josephson junction characteristics couldbe left unchanged by applying a steady current to one of theinputs. It was also made clear that using the method of thispaper allows the number of two-, three-, and four-variablelogic functions realizable with a single SQUID to be in-creased from 12 to 14, from 86 to 228, and from 1108 to41,206, respectively, and that the maximum number ofSQUIDs actually required for logic functions unrealizablewith a single SQUID can be reduced to about half. It wasalso shown that although the operating regions decreasesomewhat when the method of this paper is used, the scope

of this reduction is no more than about 10% in relation tothe logic functions with a ratio of about 95%. In the par-ticular case in which the reduction of operating regionspresents a problem, the scope of the reduction can belimited to a mere 5% or less by increasing the number ofSQUIDs by one.

In conventional technology, the SQUID fan-in is lowat about 5 to 6, so it is not easy to use the method of thispaper in unchanged form for logic functions of multiplevariables. As a way of addressing this problem, we pro-posed representing a given logic function as a syntheticfunction comprising four to five logic functions, and thenexpressing this function by connecting multiple SQUIDs inseries or in parallel. Also, the method of this paper wasdescribed with reference to a magnetically coupled super-conductive logic circuit in which a SQUID constitutes thebasic constituent element, but we believe that the methodcan also be applied to current-injection superconductinglogic circuits by providing two (positive and negative)current source currents.

REFERENCES

1. Ishida A, Yanagawa T, Yoshikiyo H. Superconductivelogic circuits—Logic gates. IECE; 1983. p 30–44.

2. Baechtold W. A flip-flop and logic gate with Joseph-son junctions. IEEE J Solid-State Circuits Tech Dig,p 164–165, 1975.

3. Gheewala TR. A 30ps Josephson current injectionlogic. IEEE J Solid-State Circuits 1979;14:787–793.

4. Nagaishi H, Nakahara H, Hasegawa H, Nishino K.Design and operation of Josephson circuits usingHuffle gates with a stacked structure. IEICE Trans1994;J77-C-II:301–310.

5. Faris SM. Loop decoder for Josephson memory ar-rays. IEEE J Solid-State Circuits 1979;14:699–707.

6. Harada Y, Hatano Y, Yamashita K, Kawabe U. Joseph-son threshold logic circuit and its application. IECETrans 1985;J68-C:1038–1043.

7. Morisue M, Ueda K, Sakamoto M. SFQ digital cir-cuits for single rail asynchronous system. IEICETrans 1999;J82-C-II:398–406.

8. Fujisawa T, Kasami T. Mathematics for electronicsand communication engineers, II. Theory of discretestructures. Corona Publishing; 1977. p 123–147.

9. Sasao T. Logic design—Theory of switching circuits,2nd ed. Kindai Kagakusha Publishing Co.; 1998. p79–93.

10. Hayakawa H (editor). High-speed Josephson de-vices. Baifukan Co.; 1985. p 223.

Table 6. Influence of steady current on operatingregions

49

AUTHORS (from left to right)

Masahiro Kawai (member) graduated from the Department of Metal Engineering of Tsuyama National College ofTechnology in 1975 and joined Alps Electric Co. He moved to Olympus Corporation in 1983. Since 1986, he has taught in theDepartment of Electronics and Computer Engineering at Tsuyama National College of Technology. He is currently an assistantprofessor there. His research concerns the problem of conflicts in asynchronous circuits, and methods for constructingsuperconductive logic circuits. He holds a D.Eng. degree, and is a member of the Information Processing Society of Japan.

Yoichiro Sato (member) graduated from the Department of Electrical Engineering of Okayama University in 1982,received his master’s degree in 1984, and joined Toshiba Corp. He enrolled in the doctoral course at Okayama University in1987 and concurrently became an assistant in the Department of Information Technology. Since 1995, he has been an assistantprofessor in the Department of System Engineering, Faculty of Computer Science and System Engineering, OkayamaPrefectural University. His research interest is computer hardware. He holds a D.Eng. degree, and is a member of the InformationProcessing Society of Japan.

Hiroto Kagotani (member) graduated from the Department of Computer Science of Tokyo Institute of Technology in1988 and completed the doctoral course in 1994. He is currently an instructor teaching in the Department of CommunicationNetwork Engineering at Okayama University. His research interests are asynchronous processor design technology, imageprocessing hardware, and parallel processing. He holds a D.Eng. degree, and is a member of IEEE-CS.

Takuji Okamoto (member) graduated from the Department of Communication Engineering of Osaka University in 1958and joined Kawasaki Heavy Industries, Ltd. He moved to Mitsui Engineering & Shipbuilding Co., Ltd. in 1960. He joined theFaculty of Engineering of Okayama University in 1967, and became a professor in 1987. He has been a professor in theDepartment of Electronic Engineering of Okayama University of Science since 2001. He is primarily involved in research oncomputer hardware based on logic circuits. He holds a Ph.D. degree, and is a member of the Information Processing Society ofJapan, the Institute of Electrical Engineers of Japan, and IEEE.

50