SUPER-Lab - Trials & Tribulations of Evaluating GaN and SiC … · 2016. 9. 28. · Resonant...
Transcript of SUPER-Lab - Trials & Tribulations of Evaluating GaN and SiC … · 2016. 9. 28. · Resonant...
Stanford UniversitySUPER-Lab
Trials & Tribulations of Evaluating GaN and SiC switching devices
Kawin Surakitbovorn, Jungwon Choi, Lei Gu, Sanghyeon Park, WeiLiang, Luke Raymond, Emily Hernandez, Grayson Zulauf, Juan
SUPER-Lab October 3, 2016 1 / 48 Stanford University
Good progress made in low voltage power electronics
Low Voltage Power ConversionI Focus on moderate gain
ratio step downI Efficient, power dense
converters commerciallyavailable
I Efficiencies in the upper90%s
I Power densitiesapproaching 3 kW/in3
VICOR 400 V to 50 V dc-dc
I 2750 W/in3
I ≈98% efficientI 1750 W
www.vicor.com
SUPER-Lab October 3, 2016 2 / 48 Stanford University
High voltage supply development has Lagged
I High voltage power suppliesremain expensive and relativelyinefficient
I If fast pulses are needed a highvoltage switch is generally usedin conjuction with a capacitor
I Efficiencies in the 60%s arecommon
I Typical power densities<10 W/in3
Ultravolt High Power C SeriesI 9 W/in3
I 30 V to 2000 V dc-dc
www.ultravolt.com
SUPER-Lab October 3, 2016 3 / 48 Stanford University
high voltage circuits
I Various circuits can be used togenerate high voltages:I Fly-back convertersI Marx generatorsI Cockcroft–Walton multiplierI Quasi–resonant, resonant
convertersI and cascaded versions of
these
C1
C2
C3
C4
Cn-1
Cn
D1 D2 D3 D4 Dn-1 Dn
+V
vac(t)
C1
C2
C3
C4
Cn-1
Cn
D1 D2 D3 D4 Dn-1 Dn
+2V
C1
C2
C3
C4
Cn-1
Cn
D1 D2 D3 D4 Dn-1 Dn
C1
C2
C3
C4
Cn-1
Cn
D1 D2 D3 D4 Dn-1 Dn
+nV
+V
I Parasitics, output impedance, device stress, etc, impose practicallimits to the number of stages that can be cascaded to produce largevoltage gainsI CockcroftWalton multiplier limited to 10-12 stages due to loading
effects
SUPER-Lab October 3, 2016 4 / 48 Stanford University
Resonant converter structure
Inverter TransformationStage
Rectifier
Control
Vin RL+
−
InverterTakes dc input power,deliver ac power
Transformation stageProvides impedancematching
RectifierTakes ac power,delivers dc power toRL
[2] J.M. Rivas, O. Leitermann, Y. Han, et al, “A very high frequency dc-dc converter based on a class Φ2 resonant inverter,” in Proc.Power Electronics Specialists Conference, 2008. pp. 1657-1666[4] W. Liang, J. Glaser, and J. Rivas, 13.56 MHz high density dc-dc converter with PCB inductors, in Proc. 2013 Twenty-Eighth AnnualIEEE Applied Power Electronics Conference and Exposition (APEC), 2013, pp. 633640.
SUPER-Lab October 3, 2016 5 / 48 Stanford University
Previous work involving a single stage resonant design
+−
vgs(t)+
-
LMR
CMR
LF LS CS
VIN
Q1 CP +− VOUT
LRCDex
D2
+vds(t)-
CM
LM
-
Φ2 Inverter
Low PassMatchingNetwork
Class D Rectifier
COUT
CB
D1
va2(t)
+
-
I 40 V to 500 V 27.12 MHz step up design was testedI Output voltage limited by rectifier diode ratingsI Matching network quality factor (Q) increases with increasing gain
ratio[5] Raymond, L.; Wei Liang; Jungwon Choi; Rivas, J., “27.12 MHz large voltage gain resonant converter with low voltage stress,”Energy Conversion Congress and Exposition (ECCE), 2013 IEEE , vol., no., pp.1814,1821, 15-19 Sept. 2013
SUPER-Lab October 3, 2016 6 / 48 Stanford University
Class-D rectifier modification
I vdiode,max = VOUT
I Relatively low equivalent inputresistance compared to relatedresonant rectifier topologies
I DC blocking capacitor can besplit to achieve isolation
Ct
Lr VoDb
Dt
+
−
Zrec
Zrec
Lr
Ct
Db
+
−Vo
Dt
Cb
SUPER-Lab October 3, 2016 7 / 48 Stanford University
Isolation allows for multiple rectifiers
Db
Cb
Ct
Dt
+
−Vo
Db
Cb
Ct
Dt
+
−Vo
Zrec
Db
Cb
Ct
Dt
+
−Vo
I Isolated rectifiers can be drivenin parallel from a single inputsource
I Equivalent resistance seen bythe ac source is Rrect/n
I Outputs can be added in seriesto achieve voltage gain
I Elimination or reduction ofmatching network
I LR of each rectifier can becombined into a single inductorof value LR/n
I Overall efficiency is equal toefficiency of each individualstage
SUPER-Lab October 3, 2016 8 / 48 Stanford University
High voltages at 10’s of MHz
Resonant
rectifier
Resonant
rectifier
Resonant
rectifier
VHV
+
-
+
−Dc/RFVdc I Capacitive isolation
feasible at 10’s of MHzI Cascading multiple
converters for highvoltage gain
I Also effective forimpedance matching
I Fast pulse capability
SUPER-Lab October 3, 2016 9 / 48 Stanford University
12 Stage Design with Silicon
I 100 W 40 V to 2000 V dc-dc 27.12 MHz converterI Silicon devices exhibit more ideal behavior allowing for 27.12 MHz
operationI 12 class-D stages for a voltage gain of 50 using a matching network
with a quality factor of 2I A single stage design would require a Q >20
SUPER-Lab October 3, 2016 10 / 48 Stanford University
40 V to 2 kV Converter Performance
DC-DC PerformanceI Ability to produce very square pulsesI 90% conversion efficiency (dc-dc)I Silicon diodes yield 95 % rectification efficiency as expected
SUPER-Lab October 3, 2016 11 / 48 Stanford University
Pulsed electric field pasteurization
Diversified Technologies Inc. Diversified Technologies Inc. Diversified TechnologiesInc.
I High electric field ≈ 20 − 50 kV/cm pulses causes rupture bacterialmembranesI Render bacteria un-viableI Non-thermal means to pasteurize foodstuffsI Less energy intensive than thermal pasteurizationI Effective for pasteurization, algai oil extraction, dehydration,
wastewater treatment
I Current PEF systems are costly and limited to industrial settings
SUPER-Lab October 3, 2016 12 / 48 Stanford University
Miniature PEF Experimental Setup: Water
I 2 kV/mm field strengthI Variable speed pumpI Pulse rate selected to ensure all
water is treated at least once
Idex Health & Sciences
SUPER-Lab October 3, 2016 13 / 48 Stanford University
Bacteria Test Results
I Tested Effectivness on E. Coli and ColiformI 2-3 log reduction in measured bacteria levelsI Energy requirement of 0.5 Wh/L
SUPER-Lab October 3, 2016 14 / 48 Stanford University
40% of milk in some emerging markets spoils
I Small farmers can’t afford current pastuerizing equipmentI Communities rely on a network of aggregators and milk collectors to
process and distribute milkI Weather, road conditions etc., can risk milk delivery
Photo credit: Nestle, Sri Lanka & Varick Schwartz, Kiva Fellow serving in Nairobi, Kenya
SUPER-Lab October 3, 2016 15 / 48 Stanford University
2 kW 13.56 MHz 275 V to 2 kV output isolated dc-dc
I 250 W/in3 including gate drive and cold plateI 3 µs transient responseI 2 × Φ2 inverters using GaN Systems 650 V MOSFETsI 94% inverter efficiencyI 4x500 W rectifiers (SiC) with 500 V outputs in seriesI 90% rectifier efficiency vs. 97% predicted by simulation model
SUPER-Lab October 3, 2016 16 / 48 Stanford University
Part I
Losses in WBG rectifying devices
SUPER-Lab October 3, 2016 17 / 48 Stanford University
Class D and Φ2 Rectifiers Prototypes (40 V-500 V)
+−
vgs(t)+
-
LMR
CMR
LF LS CS
VIN
Q1 CP +− VOUT
LRMR
CRMR
LR CDex
D
+vds(t)-
CM
LM
vr(t)
+
-
Φ2 Inverter
Low PassMatchingNetwork
Φ2 Rectifier
COUT
(a) Φ2 Inverter–Φ2 rect.
+−
vgs(t)+
-
LMR
CMR
LF LS CS
VIN
Q1 CP +− VOUT
LRCDex
D2
+vds(t)-
CM
LM
-
Φ2 Inverter
Low PassMatchingNetwork
Class D Rectifier
COUT
CB
D1
va2(t)
+
-
(b) Φ2 Inverter–D rectFig.: Schematic of implementd dc-dc converters
Fig.: Φ2 Inverter – L.P. Matching Network – Class D Rectifier
VIN VOUT Rectifier Designed Sim. Exp.[V] [V] Class POUT %η %η
40 500 Φ2 40 89 3530 300 Φ2 36 84 6430 300 Φ2 42 86 7028 280 D 46 92 80
Losses in the diode wereprincipal suspect as source ofdiscrepancy
SUPER-Lab October 3, 2016 18 / 48 Stanford University
Class D and Φ2 Rectifiers Prototypes (40 V-500 V)
Part 1st Design
MOSFET FDMC86116LZdiode C4D02120E
CS 2 nFCM 20.5 pFCMR 99 pFCP 170 pF
CRMR 13 pFCExtra 15 pF
CB NA
LF 81.6 nHLMR 81.6 nHLS 81.6 nHLM 1380 nHLR 750 nH
LRMR 570 nH
-20
-10
0
10
20
30
40
50
10 27.12 54.24 81.36 300
|Zd
s|
[dB
Ω]
Frequency [MHz]
Drain source impedance (magnitude)
Measured
Simulated
The initial design utilized a Φ2 rectifierI Inverter alone was 93 % efficient as
simulated.I Impedance matching was excellent.
SUPER-Lab October 3, 2016 19 / 48 Stanford University
Diode losses
Fig.: Thermal image of 27.12 MHz Φ2 − Φ2 dc-dc converter. Here VIN = 40 V and VOUT = 500 V. Converter is modulated on/offat 10 kHz with 10 % duty cycle. This was necessary to keep the temperature low for long enough to take pictures.
I Initial design was 35 % efficientI Losses were not accounted for by models or information provided by
manufacturers
SUPER-Lab October 3, 2016 20 / 48 Stanford University
Characterizing diode losses
+
− VOUTLr
CD2
D2
vd(t)D1CD1Cex
+
-
Cb
Cm
Lm
MatchingNetwork Resonant Class D Rectifier
vRF(t)
+
-
iRF(t)
Zrec
vr(t)
+
-
ir(t)
IOUT
Zi
Fig.: Class D rectifier connected to a low-pass matching network. ZIN is designed to be resistive with a value of≈ 50 Ω
I Class D selected to it minimizes diode stressI Rectifier tuned to look resistive at given IOUT , VOUT
I Low-pass matching network matches Zrec to 50 Ω
I lower Zi makes tuning of matching network easier
SUPER-Lab October 3, 2016 21 / 48 Stanford University
There should be only conduction loss in theory
− vD + iD
Cj,D vD
t
Vout
1/fs
t
iD
⟨iD⟩=Iout
Vout = rectifier output voltagefs = switching frequencyIout = rectifier output current
I Voltage across diode vDI Zero voltage turn-on
I Current through diode iDI Zero current turn-off
I Junction capacitance energy recycledthrough resonance
I Zero reverse recovery if SiC diodes areused
SUPER-Lab October 3, 2016 22 / 48 Stanford University
Characterizing Diode losses
+
− VOUTLr
CD2
D2
vd(t)D1CD1Cex
+
-
Cb
Cm
Lm
MatchingNetwork Resonant Class D Rectifier
vRF(t)
+
-
iRF(t)
Zrec
vr(t)
+
-
ir(t)
IOUT
Zi
VOUT Lm Cm Lr Cextra ‖Zrec‖[V] [µH] [pF] [nH] [pF] [Ω]
500 1.52 21.8 783 8 9521000 1.75 19.2 1062 10 1788
I fs = 27.12 MHz,IOUT = 75 mA, Zi ≈ 50Ω
I ddt v(t) can exceed 100 V/ns
I Notice discrepancy betweensimulated loss breakdown andtotal measured loss
0
10
20
30
40
50
500V(sim) 500V(exp) 1kV(sim) 1kV(exp)
Power Loss [W]
Simulated and experimental losses, IOUT=75mA (C4D02120E)
D1D2LrLm
Total Loss (Measured)
SUPER-Lab October 3, 2016 23 / 48 Stanford University
Diodes studied
Mfg Part no. Type VRmax IFmax
Cree C4D02120E SiC 1200 V 4.5 ASTMicro STPSC6H12 SiC 1200 V 6 AGenesic GB02SLT12 SiC 1200 V 2 A
Cree C3D04060E SiC 600 V 7.5 ACree CSD04060E SiC 600 V 4 A
STMicro STPSC406 SiC 600 V 4 AInfineon IDD03SG60C SiC 600 V 3 A
Diodes Inc. DFLS1200 Si 200 V 1 A
020406080100120140
1 10 100 1000
CKA [pF]
VKA [V]
CKA vs. VKA for GB02SLT12-252
datasheetSpice Model
Datasheet and spice models can beincomplete or inaccurate
DidealRF
+ −
VF
vika(t) +-
ic(t)
ddt
Look upTable
C(vika1)vika1C(vika2)vika2C(vika3)vika3
vika(t)
LW
anodeCathode
Rapid method to evaluate junctioncapacitance
SUPER-Lab October 3, 2016 24 / 48 Stanford University
Test setup
ch1 ch2 ch3 ch4
Oscilloscope
COMA
V
V A
AOFF
COMA
V
V A
AOFF
Lm
Cm Lr
Cb
50Ω
RFIN
V
A
Linear PowerAmplifier
Low PassMatching Network
Rectifier ConstantVoltageLoad
vd(t)
-
+
vIN(t)
-
+
iIN(t) IOUT
VOUT
-
+
D1
D2
COUT
deg C
Thermocouple
I Zi matched to ≈ 50 Ω
I Constant VOUT , Zener load
I Different design for each diodeand VOUT
I Minor tuning through Cextra
SUPER-Lab October 3, 2016 25 / 48 Stanford University
Performance measurements of 600 V CREE SiC diode
-100
0
100
200
300
400
500
600
0 20 40 60 80 100 120 140
Voltage [V]
Time [nS]
Anode Voltage C3D04060E
Measured
Simulated
I VOUT = 170 V, 350 V and500 V
I Experiments and simulationsmatch well
I In all cases IOUT = 75 mA
I Discrepancies betweenmeasurement and simulationincrease with increasing VOUT
SUPER-Lab October 3, 2016 26 / 48 Stanford University
600 V SiC diode loss comparison
0
0.5
1
1.5
2
2.5
3
3.5
170 V 350 V 500 V
Power [W]
Estimated Diode loss at various output voltages, IOUT=50mA (600V SiC Diodes)
STPS406CSD04060EC3D04060E
IDD03SG60C
IOUT = 50 mA
0
0.5
1
1.5
2
2.5
3
3.5
170 V 350 V 500 V
Power [W]
Estimated Diode loss at various output voltages, IOUT=100mA (600V SiC Diodes)
STPS406CSD04060EC3D04060E
IDD03SG60C
IOUT = 100 mA
I Notice that the diode loss is similar at both current levels butincreases significantly with output voltage.
SUPER-Lab October 3, 2016 27 / 48 Stanford University
1.2 kV SiC diode loss comparison
0
2.5
5
7.5
10
12.5
15
17.5
20
500 V 1000 V
Power [W]
Estimated Diode loss at various output voltages, IOUT=50mA (1.2kV SiC Diodes)
STP6H12C4D02120EGB02SLT12
IOUT = 50 mA0
2.5
5
7.5
10
12.5
15
17.5
20
500 V 1000 V
Power [W]
Estimated Diode loss at various output voltages, IOUT=100mA (1.2kV SiC Diodes)
STP6H12C4D02120EGB02SLT12
IOUT = 100 mAI Notice that the Diode loss is similar at both current levels but
increases significantly with output voltage
SUPER-Lab October 3, 2016 28 / 48 Stanford University
Direct Comparison
I VOUT = 500 V , IOUT = 100 mA fs = 27.12 MHz
I D1 ST MicroelectronicsI D2 Infineon
I D1 InfineonI D2 ST Microelectronics
SUPER-Lab October 3, 2016 29 / 48 Stanford University
GaN’s zero reverse recovery raised hopes for improvement
I Tying the gate to the source makes GaN FET behave like a diode.
GD
S
GaN FET
≡
Eric Person (Infineon) “Practical Application of 600 V GaN HEMTs in PowerElectronics”, Professional Education Seminar, APEC 2015
SUPER-Lab October 3, 2016 30 / 48 Stanford University
The experimental efficiency did not match the simulationI 100 W 500 V 27.12 MHz class-D resonant rectifier with GS66502B
working as a diode.
Simulation Experiment
Efficiency 94% 90%Power loss in total 6W 11 W
Power loss per device 0.8W 3.0W
SUPER-Lab October 3, 2016 31 / 48 Stanford University
Power loss comparison of devices with similar V-I ratingsI Blue bars are GaN FETs and red bars are SiC diodes.I GaN FET power loss is much larger than predicted by simulation.
Power loss per device, whenPout = 25 W, Vout = 500 V, f = 27.12 MHz, Idc = 50 mA
0W 1W 2W 3W 4W 5W 6W
STMicro
Cree 3Amp
Cree 7Amp
Cree 8Amp
Navitas
GaNSys
Transphorm 10.2W2.8W
1.4W
simulation
SUPER-Lab October 3, 2016 32 / 48 Stanford University
Power loss comparison of devices with similar V-I ratingsI Blue bars are GaN FETs and red bars are SiC diodes.I GaN FET power loss is much larger than predicted by simulation.
Power loss per device, whenPout = 25 W, Vout = 500 V, f = 40.68 MHz, Idc = 50 mA
0W 2W 4W 6W 8W
STMicro
Cree 3Amp
Cree 7Amp
Cree 8Amp
Navitas
GaNSys
Transphorm 19.4W
6.6W
2.6W
simulation
SUPER-Lab October 3, 2016 33 / 48 Stanford University
The observed power loss is not switching lossI Voltage across GaN Systems part in 50mA 27.12MHz rectifier at
various output voltagesI The waveforms show that soft switching is occurring and the
capacitor energy is being recycled.
-100V
0V
100V
200V
300V
400V
500V
600V
0ns 18ns 37ns 55ns 74ns 92ns 110ns
170V 350V 500V simulation
SUPER-Lab October 3, 2016 34 / 48 Stanford University
The power loss increases with voltageI The offset from the conduction loss remains almost constant with the
increasing dc current.I This additional power loss increases with the voltage across the
device.
The additional power loss from the conduction lossGaN Systems part at f = 27.12 MHz
0W
1W
2W
3W
0.0A 0.5A 1.0A
170V
350V
500V
SUPER-Lab October 3, 2016 35 / 48 Stanford University
The power loss increases with frequency
I The offset from the conduction loss remains almost constant with theincreasing dc current.
I This additional power loss increases with the frequency.
The additional power loss from the conduction lossGaN Systems part at Vout = 500 V
0W
3W
6W
9W
0.0A 0.5A 1.0A
13.56MHz
27.12MHz
40.68MHz
SUPER-Lab October 3, 2016 36 / 48 Stanford University
The power loss increases with temperature
Power loss per device in 25 W rectifier at 27.12 MHz and 500 Voutput voltage
0W
2W
4W
6W
8W
10W
12W
14W
20 30 40 50 60 70
Case Temperature
Transphorm
GaNSys
Navitas
0W
1W
2W
3W
4W
20 30 40 50 60 70
SUPER-Lab October 3, 2016 37 / 48 Stanford University
Part II
Evaluation of GaN transitors at highfrequencies
SUPER-Lab October 3, 2016 38 / 48 Stanford University
How do we achieve precise simulation?
Accurate models for passive components
Circuits only contain air-core high Qinductors and high Q ceramiccapacitorsI Equivalent Series Resistance
(ESR) approx. is accurateenough
Accurate parasitic component values matching
Done by reverse-calculating parasiticcomponent values from themeasured drain impedance
SUPER-Lab October 3, 2016 39 / 48 Stanford University
How de we achieve precise simulation?
Accurate models of the semiconductor devicesI Rely on manufacturer provided models
I Most of the time the models are accurateI Some time the models are incomplete or wrong
I Two most important parts of themodel are:I On Resistance (Rds,ON)I Nonlinear output capacitance
COSS
SUPER-Lab October 3, 2016 40 / 48 Stanford University
How accurate do we typically get?I 100 W Inverter @ 27.12 MHz with FDMS8622
I 100 V Fairchild N-Channel Power Trench Silicon MOSFETI Max Rds,ON = 56 mΩ at VGS = 10 V, ID = 4.8 AI Simulated with manufacturer provided modelI Simulation efficiency: 90%I Test efficiency: 89%
SUPER-Lab October 3, 2016 41 / 48 Stanford University
Advantages of GaN transistors
Lower input and output capacitance (CISS and COSS)
I Faster rise time and fall timeI Lower switching lossI Lower gate lossI Higher switching frequency
Lower on resistance (Rds,ON)I Lower conduction loss
I Higher efficiencyI Smaller heatsink
Better packages!I Most GaN devices come in low inductance packagesI Can’t say the same on SiC (T0-220, To-247)
SUPER-Lab October 3, 2016 42 / 48 Stanford University
The problem comes when we started designing converterswith GaN transistors
Test efficiencies greatly differ from the simulation
I #1 Class Φ2 inverter with GS61008PI 27.12 MHz, 40 Vdc input, 100 W outputI Simulation predicts 94.5% efficiency
I ≈ 1.4W loss in the FETI Test result ≈ 89% efficiency
I #2 Class D rectifier with GS66502BI Vgs = 0 V, GaN transistors configured as
diodesI 27.12 MHz, 260 Vpp AC input, 400 V, 80 W
outputI Simulation predicts 93% efficiency
I ≈ 1W loss in each FETI Test result ≈ 84.5% efficiency
SUPER-Lab October 3, 2016 43 / 48 Stanford University
Thermal images show the losses in the FETs to be up to 3-4times the losses predicted by the simulations
SUPER-Lab October 3, 2016 44 / 48 Stanford University
This is very interesting to us because
I Resonant converters only have conduction lossI If on-resistance (and forward voltage) is accurately model, the
experimental losses should match the simulation lossesI This suggests that there are extra losses beyond the Ron loss
I Not yet accurately modeledI Not switching loss
I Could vary significantly depending on manufacturers technologiesand voltage levelI The same as in the SiC diodes study
I Potentially a high frequency (MHz) phenomenaI Designers using GaN at standard switching frequencies (100s of kHz)
do not notice this problem
SUPER-Lab October 3, 2016 45 / 48 Stanford University
What are potential sources of the extra losses?
Losses in the output capacitance of the transistor (Coss)I Usually modeled with a series resistance
I But could also be distributed and require a more complicated model inMHz frequency
I If this loss dominates, using a bigger device to reduce Rdson will notnecessary reduce the overall loss
Losses due to dynamic Rds,ON
I Due to charge trapping, deviceson-resistance presents a value manytimes its DC value immediately afterbeing switched on
I This behavior has been mitigated, butmay still affect converters operating atMHz frequencies
SUPER-Lab October 3, 2016 46 / 48 Stanford University
Acknowledgent
I would like to thank Texas Instruments (TI) for supporting this study byfunding us through the System X Power Management focus area, as wellas Navitas for providing us with the devices for this study.
SUPER-Lab October 3, 2016 47 / 48 Stanford University
6.78 MHz SiC MOSFET RF inverter
Parameter Measured Simulated
Vds,max 940 V 942 VVout,rms 332 V 333 V
Pout 2204 W 2224 W
efficiency 93% 96%
3.5 inch
3.2 inch
Gate driver LF
LMR
Ls SiC MOSFET
Class Φ2 inverter with the SiC MOSFETI Gate driver: IXRFD630 (IXYS 30 A Low-Side RF MOSFET Drive)I Switching frequency: 6.78 MHz (ISM band frequency)I Inductors: air-core, solenoidal type inductors. Q is above 250.
SUPER-Lab October 3, 2016 48 / 48 Stanford University