Summer03 microeconomicsofyield

Summer 2003 Yield Management Solutions 49

IntroductionMost yield loss is caused by random defectsand systematic process errors. For the 130 nmdesign-rule generation, random defects andparametric process errors are roughly equalcontributors to yield loss. At the 90 and 65 nm nodes, parametric losses are expectedto dominate. Factory managers will be forc e dto make an economic trade-off between yieldand density in order to achieve minimumdie cost. Widespread use of sub-wavelengthlithography with resolution enhancementtechnologies is shrinking both the patternregistration and critical dimension processwindows.

Consider a specific example. Currently,overlay yield entitlement is no longer unitydue to poor correlation of traditional box-in-box overlay targets with in-device features.In addition, shrinking design rules are nar-rowing the overlay process window, cre a t i n ga looming overlay yield problem for the 65 nm technology node. Models predictingoverlay yield loss and subsequent die-costincreases are shown in Figures 1 and 2. The

ITRS 2001 Roadmap has identified the 65 nm genera-tion as a showstopper for overlay, with no known solu-tions. In this work, we describe an innovative solutionusing a grating-based target technology that decreasestotal measurement uncertainty and dramatically incre a s e sthe yield-re l e v a n c e of overlay metrology at the 65 nmnode.

In Figures 3 and 4, we show the effect of mean-shift andcontrol-loss, the two primary mechanisms for overlay-related yield loss in semiconductor manufacturing.Figure 5 shows the overlay control requirements for the250 to 45 nm technology nodes at constant yield. Thecontours are approximate solutions to the integralequation

(1)

In this equation, y is the yield-error curve, E is theoverlay error distribution, x is the error, and σ is theGaussian width of the error distribution.

The economic consequences of yield loss are readilycomputed if the factory economic model is known. InF i g u re 6, we show the particular case for DDR SDRAMin a large factory where a 6-nm overlay error could re s u l tin nearly $30 million of revenue loss. The problem is

Microeconomics of Yield Learning inSemiconductor Manufacturing

Kevin M. Monahan, KLA-Tencor Corporation

Simple microeconomic models that directly link yield learning to profitability in semiconductor manufacturing have beenrare or non-existent. In this work, we review such a model and provide links to inspection capability and cost. Using asmall number of input parameters, we explain current yield management practices in 200 mm factories. The model is thenused to extrapolate requirements for 300 mm factories, including the impact of technology transitions to 130 nm designrules and below. We show that the dramatic increase in value per wafer at the 300 mm transition becomes a driver forincreasing metrology and inspection capability and sampling. These analyses correlate well with actual factory data andoften identify millions of dollars in potential cost savings. We demonstrate this using the example of grating-based overlaymetrology for the 65 nm node.

Special focusO V E R L A Y M E T R O L O G Y

Summer 2003 Yield Management Solutions50

F i g u re 1. Overlay yield component versus gate overlay error for the

250 to 45 nm technology nodes, calibrated to factory data at 250 nm.

F i g u re 2. Die-cost increases versus gate overlay erro r, showing explosive

g rowth in die-cost at the 65 nm node due to overlay-related yield loss.

F i g u re 3. Overlay yield loss distr ibution resulting from a 6 nm mean

shif t. Product of yield error curve and shifted Gaussian error distribut ion

derived from ITRS speci fications.

F i g u re 4. Overlay yield loss distribution resulting from a 6 nm loss of

c o n t rol. Product of y ield error curve and broadened Gaussian erro r

di st ribution derived from ITRS specifications.

F i g u re 5. Model showing 3-sigma overlay control re q u i rements at

constant yield, compared to ITRS 2001 specifications. Control must be

tigh ter to guarantee acceptab le yields.

F i g u re 6. 400MHz 256Mb DDR SDRAM revenue loss model for

constant device overlay off sets. At 6 nm, losses in a large factory

could be as much as $30 mil lion per year.

O V E R L A Y M E T R O L O G Y


that 6 nm offsets from the true device overlay are likelyto be common using current box-in-box overlay targ e t s .*

These offsets cause small losses now, but they will havedevastating yield consequences at the 65 nm node. Asshown in Figures 7 and 8, the solution is to change the paradigm for overlay targets and migrate from box-in-box to grating targets. Since the new targetswork with the existing overlay metrology platform, theimplementation risk is low and the re t u rn on investmentis in millions of dollars per year.

A unified yield model for lithographyOf course, overlay is only one component of a unifiedyield model for lithography. The multitude of yield-affecting process variations can be characterized by theprobability that they will result in a non-functionaldie. We can model this behavior as a product of sur-vival probabilities given by

(2)

Here, λ is the yield-loss due to defects of type i, n isthe number of defects per die of type i, and N is thetotal number of defect components. The accuracy of theyield model can be improved by identifying thosedefects with the highest loss potential and those thatpose quantifiable economic risk.1 For lithography, theprincipal yield components are associated with CD,overlay, macro, and micro defects.

In the case of parametric process defects, we can showthat yield losses are functions of measured parameterssuch as overlay and critical dimension, or other para-meters, such as exposure variation and local defocus,which are observed indirectly in the form of CD excur-sions. For the remainder of this work, the traditionalseparation of systematic pattern-transfer and parametricdefects (Ys) from random process-induced and contami-nation defects (Yr) will be ignored in favor of a newparsing based upon knowable causes (yk) and unknow-able causes (Yu), so that

(3)

In this new parsing, yield is fundamentally limited byunknowable causes, e.g., those that lie beyond themetrology capability of a given factory. The correlationof metrology to yield (and hence to profitability) is astrong function of metrology capability. We demon-strate this in the next sections, where we develop aheuristic model linking defect metrology to yield andprofitability.

Yield and profitabilityThe growth of DUV and 193-nm lithography is dra-matically increasing and changing the use of inlineprocess control tools. For example, CD and overlaymetrology were commonly used in the context of stan-dard statistical process control where an operator orengineer, using a set of well-established rules, decidedto change the process based upon a wafer parametermeasurement that went beyond process control limits.

F i g u re 7. Tradi tional box -in-box targets have large open areas and

a re sensitive to CMP-induced distor tion and pattern noise. They exhibit

low device cor relation and h igh re s i d u a l s .

F i g u re 8. Advanced grating targets have low sensitivity to CMP and

p a t t e rn noise. At or near the design rule, they exhibit high device cor-

relation and improved model accuracy.

* M. Adel, et al., “ P e rf o rmance Study of New Segmented OverlayMarks for Advanced Wafer Processing” and “Characterization ofOverlay Mark Fidelity”, P roc. SPIE, Vol. 5038 (2003).



For 130 nm technology and beyond, we are seeing ap o w e rful trend toward both model-based process contro land closed-loop control, with a minimum of humanintervention. The benefits of advanced process control(APC) include reduced process variation, acceleratedshrinks, elimination of send-ahead wafers, fewer monitorwafers, shorter response times, reduced scrap, better toolmatching, improved overall equipment effectiveness,faster yield ramps, lower parametric yield loss, betterdevice performance, and easier process transfer fromsite to site. These benefits translate directly into largeimprovements in the gross margins for semiconductorp roducts since they simultaneously lower manufacturingcost and increase average selling price.

We can understand these issues by introducing a sim-p l i fied model2 for pro fit a b i l i t y, or rate of pro fit, generatedby a semiconductor manufacturing process. Let

(4)

where R is the factory overhead rate, W is the numberof wafer starts, T is the time interval, Y is the yieldentitlement limit due to unknowable causes, y the fraction of the entitlement attained, d is the number ofdies per wafer, b is the bin yield expressed the fractionof good dies in each performance bin, p is the averageselling price per die, C is the manufacturing cost perw a f e r, i is the product index, and j is the binning index.This business model represents the gross rate of profitattributable to a factory. It does not include variablecosts associated with packaging, marketing, or sales ofthe product. Some of the basic strategies for maximizinggross profit are discussed below.

The first term represents the fixed costs associated withcapital investment, operation, and depreciation of thefacility that are independent of capacity utilization. For130 nm manufacturing and beyond, this investmentcould include advanced OPC/PSM reticle technology,193 nm lithography tools, 300 mm wafer handling,copper/low-k interconnect, and factory-wide metrologyintegration. In the above model, 130 nm factories wouldlose significant amounts of money before processing asingle wafer. The traditional strategy for minimizingthe relative contribution of fixed costs is to reducemanufacturing cycle time and operate near maximumcapacity. In a supply-limited environment, this meansfilling the factory with the highest margin products. Ina demand-limited environment, this may re q u i re loadingthe factory with some lower margin products. The latter

strategy reduces average margins, but it improves theratio of profitability to capital investment. The largestsingle component of the capital investment is currentlyin lithography, but we expect the copper/low-k compo-nent to increase substantially in future generations.

The second term in the profitability equation aboverepresents the rate of profit, adjusted for manufacturingcost per wafer. This variable cost arises from materials,consumables, and other expenses that scale with thenumber of wafers processed. Offsetting this cost, is thefactory revenue, which is calculated from the averageselling price per die, scaled by dies per wafer, waferstarts, metrology-limited yield, device yield, and binyield. Large investments in lithography are currentlybeing used to improve yield and to reduce cost per dieby accelerating shrinks; but shrinks are ineffective with-o u t a commensurate decrease in process variation toaccommodate tighter focus-exposure windows, reducedoverlay budgets, and greater sensitivity to randommacro and micro defects. Both systematic and randomdefects can collapse lithographic process windows atthe 130-nm technology node and beyond, resulting inlong and costly yield ramps. In this paper, we developa heuristic model for metrology and sampling that canhelp define the strategy for ramping yield in developmentand for continuously improving baseline yield in pro-duction. We have already discussed the methodologyfor containing yield excursions in previous work.3

Process tools add value by generating wafer output at agiven level of yield, thereby contributing to the “top-line” revenue. Defect metrology tools, on the other hand,recover value by increasing yield without increasing costs (C), other than those associated with the metro l o g yitself. In this sense, the benefits of metrology go dire c t l yto the “bottom-line” profitability of the semiconductormanufacturing enterprise. We have shown previouslythat metrology in the factory should be optimized usingstochastic models.2 H o w e v e r, the dynamics of metro l o g y,yield, and pro fitability in the factory are best understoodusing heuristic response models that are chosen to fit the re s u l t sof more rigorous stochastic models or actual factory data.

For the single-product response model, we make thesimple assumption that, starting at 1-y0, killer defectsdecline by the same fraction with each cycle of learningn, so that the effectiveness of learning declines expo-nentially. The incremental cost due to metrology isassumed to scale linearly with the number of cycles oflearning, in accord with CoO models. If the capabilityand cost of metrology scale with α and β, respectively,



then substituting into the equation for profitabilitygives us an expression for the value recovered bymetrology:

(5)

In the limit where the metrology-limited yield entitle-ment (Y) approaches unity, the value recovered is justthe improvement in the gross margin of the product.The number of cycles of learning required to reachpeak profitability is given by:

(6)

We can make a number of qualitative observations withregard to metrology-driven yield improvement, someof which are highly intuitive:

• In development, where starting yields are low, theneed for metrology is high for all products. Withina single process generation, the optimal allocationof metrology resources is time-dependent.

• In production, high value per wafer and relativelylow transfer yield increases the need for metrology(microprocessor). Within a process generation, theoptimal allocation of metrology re s o u rces is pro d u c t -dependent.

• If metrology capability and cost are scaled propor-tionately (i.e., if α/β is constant), the design ofnext-generation metrology tools (N+1 and N+2)will be dominated by the re q u i rement for capability.The negative impact of cost on value recovery isgreatest when the expected revenue per wafer is low(memory).

• Value recovery is greatest when metrology tools arefast (low β), sensitive (high α), and responsive to allyield-limiting defect types (high Y). In virtually allcases, these are conflicting requirements that arguefor multiple-tool metrology solutions. An optimizedmulti-tool solution can reduce cycle-times, drivesteeper yield ramps, and achieve higher yield entitlements.

The above results make a strong case for increasing thevariety and extending the capability of metrology toolsin the semiconductor manufacturing process. Economicdrivers are behind a number of observable trends. Forexample, many semiconductor manufacturers are now

adding e-beam-based wafer inspection to the complementof optical inspection tools in their factories. Others areaugmenting traditional optical film-thickness metro l o g ywith advanced C-V metrology that measures both theelectrical thickness and the contamination of gatedielectrics. In lithography, CD and overlay metrology isincreasingly used for closed-loop, model-based processcontrol. In the case of traditional defect metrology,automated defect classification and adaptive samplingare being used to minimize metrology costs, and SEM-based review tools are replacing optical tools.

Results and discussionIn Figures 9 to 14, the value-re c o v e ry model shows gro s smargin improvement (Y=1) for two virtual produ c t s :commodity memory and high-end micro p ro c e s s o r s .These products are assumed to have ASPs of $5 and$500 per die, respectively. The respective densities are2000 and 500 dies per 300 mm wafer. Developmentyields are assumed to start at zero, while productionyields at transfer are scaled to account for chip size andproduct complexity. In Figures 9 and 10, metrologycapability and cost are estimated for both current (N+0)and future (N+2) generations of metrology equipment.Capability and cost are assumed to double while goingfrom generation N+0 to N+2. Capability is scaled ininverse proportion to die density, decreasing as chipsize increases.

In the case of high-volume production, the model re s u l t sa re strongly diff e rentiated by product type. For commoditym e m o ry on 200 mm wafers (Figure 9), the achievableyield is limited primarily by cost. In the case of commodity memory on 300 mm wafers (Figure 10), t h eadditional value per wafer justifies a higher level of metrology(e.g., N+2), resulting in faster baseline yield impro v e m e n tand a higher yield entitlement (nearly 2 percent higherin this case). Larger gains will occur as commoditymemory manufacturers migrate to embedded logic,DSP manufacturers develop system-on-chip products,and microp rocessor companies compete for the highest-ASP market segments.

Due to higher average selling price, larger chip size, andlower transfer yield, the economic model for micro-processors is strikingly different. Substantial investmentin advanced metrology capability may be justified well intohigh-volume production. Microprocessor margins aree x t remely sensitive to metrology capability and re l a t i v e l yinsensitive to cost, justifying more cycles of learning,as shown for the “line monitor” case in Figure 11.



Taken as a whole, this analysis brings up some signific a n teconomic issues:

• Assuming optimized metrology capability, 300 mmfactories should enjoy not only economies of scale butalso higher yields and gross margins. This creates anopportunity for the larger silicon foundries and a

threat for smaller semiconductor manufacturers thatcannot afford to build 300 mm factories.

• In the case where multiple products are manufacture dusing a similar process, monitor reduction strategiesintended for the lowest-value products can lead tounacceptable economic risk. Ideally, sample plans

F i g u re 9. Commodity memory — 200 mm wafers . F i g u re 10. Commodity memory — 300 mm wafers .

F i g u re 11. Integrated met rology — micro p ro c e s s o r. F i g u re 12. Integrated metrology — memory.

F i g u re 13. Copper yield ramps — logic companies. F i g u re 14. Calib rated model — diverging yields.



should increase for high-value products manufacture don 300 mm wafers.

• In the case where multiple factories are equippedidentically (copy exact), the benefits of metrologyinnovation may never be realized, severely limitingthe ultimate yield entitlement. Ideally, 300 mm factories should be designed to support seamlessupgrades of existing metrology equipment and thei n t roduction of newer metrology tools, with minimaldisruption to the process and material flow (copys m a rt). Given the high cost of labor and the potentialfor operator error, these introductions may requireremote e-diagnostics, e-applications, and e-trainingfor both metrology and process tools.4

Multiple tool solutions for process module controlOur models generally support multiple-tool solutionsfor the optimization of yield and profitability. Mostcopper lines, for example, use a combination of dark-field, brightfield, and e-beam wafer inspection to accel-erate yield ramps. In the litho module, a combinationof macro inspection and brightfield micro inspectioncan sometimes be more cost-effective than a single-tooldarkfield inspection. With the further segmentation ofmetrology tools into stand-alone, clustered, integrated,and in-situ systems, the optimal metrology strategyseems less clear, until we consider the economic impactof these technologies.

Integrated MetrologyConsider the case of integrated metrology. We assumethat these systems will have lower sensitivity, respondto fewer defect types, but enjoy higher sampling rate incomparison with traditional stand-alone line monitors.The value-recovery calculations for production ofmicroprocessors and commodity memory are shown inFigures 11 and 12. In this example, transfer yields startat 0.60 and 0.90, respectively. Based on results forintegrated, line-monitor, and combined solutions, wecan make qualitative observations about the use ofintegrated metrology for improvement of baseline yield:

• In the case of microprocessors, integrated metrologyappears to enhance the effectiveness of more sensi-tive, stand-alone line monitors by freeing them formore demanding applications. The wafer-to-wafersampling capability of integrated tools reducesexposure to gross yield excursions.

• The use of integrated metrology as a “single-tool”solution creates unacceptable economic risk, especiallyin a high-volume ramp, since many integrated toolsare “blind” to a large fraction of killer defects. Ingeneral, factories would not achieve entitlementm a rgins and would risk exposure to non-ro o t - c a u s a b l eyield excursions.

• In a supply-limited market, silicon foundries thatcurrently enjoy a “wafers-out” business model, arelikely adopters of integrated metrology. However, ina demand-limited market, foundries that do notacquire the most capable metrology tools, will losecustomers to foundries with efficient “dies-out”business models or “wafers-out” business modelswith predictable yield boundaries. Yield prediction iscritical to meeting production requirements withoutcreating excess inventory.

Copper Yield RampsCopper pilot lines provide another example of successwith multiple-tool solutions. Most copper lines use acombination of darkfield, brightfield, and e-beam waferinspection for tool monitors, station monitors, linemonitors, and engineering analysis. This “use-case” scenario illustrates a more general trend toward completeprocess-module control solutions that include multiplemetrology tools,5 networked analysis software, andoptimized yield strategies.

The normalized copper yield ramps of several leading-edge semiconductor companies are shown in Figure 13.In Figure 14, we use some of this data to calibrate ourmicroeconomic model, thereby enabling a root-causeanalysis of the yield divergence between Companies Aand F. By fitting the model first to Company-F dataand then forcing it to achieve Company-A yield levels,we identified the likely causes of divergence. The modelparameters indicated that Company A had newer, morecapable metrology tools and significantly greater capac-ity, matching our audit of actual installations.

Adding metrology capability goes beyond upgradingor replacing older optical tools. E-beam inspection, forexample, is not only more sensitive to many physicaldefect types but is also uniquely responsive to newclasses of buried electrical defects (e.g., voids andincomplete vias) that are frequently observed in thecopper damascene process. As a consequence, e-beaminspection increases the aggregate metrology capability(α and Y), enabling shorter development cycle-times,accelerated yield learning, and higher yield entitlements.



Some of this discussion applies equally to the challengesof the 300 mm-wafer and 130 nm-technology transitions.In the case of memory, the advantages of shrinkingdesign rules and increasing wafer size are fairly obvious,as shown in Figure 15. The economic leverage ofmetrology is especially evident with the assumption ofrelatively low transfer yield (0.30) and rapidly erodingaverage selling price (-30 percent CAGR). In Figure 16,we show the impact of insufficient metrology capabilityand/or capacity for 300 mm wafers in the 130 nm-tech-nology generation. Optimized metrology clearly hasthe potential to extend the cycle of profitability formemory and other cost-sensitive products.

Dominance of metrology capabilityPerhaps the most striking prediction of the heuristicmodel is the dominance of metrology capability whencapability and cost are scaled pro p o rt i o n a t e l y. With α / βand all other factors held constant, the number of cyclesof learning required to achieve optimum profitabilitywill be inversely proportional to metrology capability

(Equation 6). A doubling of capability, for example,could cut development cycle-time in half. In Figure 17,we show the four key areas of lithographic processmodule control where metrology capability is import a n t .These areas are micro, macro, CD, and overlay defectmetrology, respectively.

The range of micro defects6 in lithography is re p re s e n t e din Figure 18. For a relatively mature process with smallrandomly distributed defects, the yield-loss functiontends to follow the Poisson model:

(7)

Here, D is the density of killer defects and A is thecritical area. Capability extension in micro defectm e t rology is focused on increasing defect sensitivity andpixel throughput (speed). Consider the case of a genericbrightfield inspection tool. If inspection wavelengths

F i g u re 15. Effect of dies per wafer — memor y. F i g u re 16. Ef fect of sensitivity/capacity defic its .

F i g u re 17. After-develop inspection (ADI) in the lithography module

can be parsed into four types.

F i g u re 18. Examples of primar y micro defects that can affect yield in

a g g ress ive li thography.



are scaled down from 500 to 350 and 250-nanometers,respectively, the image pixel sizes must be scaleda c c o rdingly to achieve improvements in sensitivity. Eachsuccessive generation will require a two-fold increase inpixel throughput to sustain the same wafer thro u g h p u t .A similar argument might be applied to darkfieldlaser-scanning tools, where sensitivity improves withsmaller spot size. Consider the case of a generic dark-field inspection tool. If minimum spot sizes are scaledfrom 5.0 to 3.5 and 2.5 micrometers, respectively, thescanning speed must increase two-fold for each genera-tion. In the transition to 300 mmwafers, both the brightfield pixelthroughput and the darkfield scanningspeeds must double again to sustainequivalent wafer throughput.

The range of macro defects in lithogra-phy is re p re s e n t e d in Figure 19. For arelatively immature process with largeclustered defects (e.g., many defectsassociated with resist coating, resistdevelopment, scratches, or gross conta-mination), the yield-loss function tendsto follow the negative binomial model:

(8)

Here, δ is the cluster factor. A valueclose to unity indicates a high degree

of clustering, while a valuegreater than 50 produces ayield-loss function that c l o s e l ya p p roximates the Poissonm o d e l .7 Capability extension in macro defect metrology isfocused on defect sensitivityand automation (speed).Consider the case of a genericmacro inspection tool. If sensi-tivity is improved from 100micrometers (approximatehuman-eye capability) to 50 and25 micrometers, respectively,we can expect to detect a muchlarger number and variety ofdefects more consistently thanwe could with a human opera-tor. Since typical line yieldi m p ro v e m e n t s are on the orderof one percent or less, our

heuristic model would suggest that macro tools mustbe both inexpensive and fast in order to substantiallyincrease gross margins. In the transition to 300 mmwafers, macro tools that utilize whole-wafer s c a n n i n gmay have an advantage in sustaining high waferthroughput at full sensitivity. In cases where operatora c c e ss is re s t r i c t ed because of factory automation, advancedm a c ro inspection may become a clear requirement.

Capability extension in overlay metrology is focused onenhancing tool performance and improving correlation

F i g u re 19. Examples of the primary macro defects tha t can affect yield in aggressive li thography.

F i g u re 20. Die-level analysi s of overlay error shows cor relation wi th manufacturing yield loss.



to yield. The example of overlay (OL) defectivity8 isshown in Figure 20. This die-level overlay analysis wasessential to separate overlay-induced yield losses t h a tw e re confounded with other systematic yield losses,particularly those with a radial dependence across thewafer. Note that typical overlay-induced yield losses9

may be on the order of a few percent. If the losses aresmall and well-behaved, they can be expressed usingTaguchi’s quadratic loss function:10

(9)

where X is the critical overlayparameter, X0 is the optimumoverlay value, and a is the scal-ing constant determined bythe regression fit. To accountfor asymmetric behavior, suchas that observed in Figure 12,we can intro d u c e higher-orderterms. Further, the aboveanalysis can expand to includemultiple regression on morecomplex models.

Capability extension in CDmetrology is focused onenhancing tool performance,improving correlation to yield,and utilizing data more effi-ciently. An example of critical-

dimension (CD) defectivity is shown in Figure 21. Thiswafer-level analysis of CD datashows that a combination offeed-back and feed-forwardtechniques (FB and FF) can beused to shift the mean andreduce the spread of gate CDsin microprocessors, therebyimproving speed and averageselling price. The strategy is tosqueeze CD distributions asclose to the gate-leakagethreshold as possible withoutincurring unacceptable lossesin device yield. In such cases,the yield loss function is sin-gle-sided and approaches unityfor small gate dimensions. Itcan be approximated by meansof logistic re g re s s i o n1 1 if we let:

(10)

where X is the critical dimension, X0 is the yield-lossthreshold, and a is a constant determined by the regres-sion fit. To achieve a better fit, we can introduce moreand higher-order terms on the right-hand side ofEquation 10.

F i g u re 21. Wa f e r- to-wafer analysis o f CD error showing a systematic drif t that affected bin yield.

F i g u re 22. CD defect signature analysis can improve the aggregate CD metrology capabi lity.



Increasing metrology capabilityIncreasing the capability of metrology in a factory canbe accomplished by developing new tool technology, byi m p roving the analysis of data, and by creating a higherlevel of integration with process tools. The parameter αin Equations 5 and 6 is clearly a function of defectdetection, classification, analysis, and correction strategies.

If we take CD metrology as an example, the addition ofprofile and image correlation on CD SEMs has dramati-cally increased the ability of these tools to influenceyield, principally by allowing detection of excursions inp ro file and shape that are not necessarily re flected in CDdata. Further, the CD data itself can be analyzed usinggeneralized ANOVA models12 to detect excursions withpredetermined spatial signatures (Figure 22). T h i sanalysis is especially important for de-confoundingspatial from temporal excursions.

More recently, the development of spectroscopic CDscatterometry has enabled the measurement of criticaldimension, profile, and height of features in gratingtargets (Figure 23). The long-term stability of thesemeasurements can meet ITRS lithographic metrologyrequirements for the 45 nm semiconductor manufac-

turing generation. In addition, SCD is non-destructiveand suited for metrology on sensitive materials, such as193 nm resists. Advanced process control, with stand-alone or integrated SCD, benefits from the simultaneousavailability of profile and height information.

Beyond improving the metrology tools and analysiss o f t w a re, aggregate metrology capability can be incre a s e dby creating higher levels of integration with processtools and improving correlation to device performance.Metrology integration does not necessarily imply a physicalconnection between metrology and process tools, although this isone means of implementation. In Figure 24, for example, weshow a case of metrology integration for a stand-aloneoverlay metrology tool.

• In the off-line case, using monitor wafers, factory - w i d esystems can link CD and overlay data to analysiss o f t w a re that provides automated CD process windowmatching and overlay analysis, respectively. The keyeconomic benefit is removal of in-situ focal and reg-istration tests from $20-25M photo modules to lessexpensive metrology tools. Another benefit is moreaccurate and precise monitoring of focal and regis-tration data due to improved metrology capability.

F i g u re 23. Example o f increased capability (α and Y) provided by spectroscopic scattero m e t ry or SCD. SCD is a relatively new technology and its

capability is incre a s i n g .



• In the inline case, using product wafers, factory - w i d esystems link CD and overlay tools to analysis softwareand advanced process control applications within anAPC framework (e.g., SEMI-E93 Specification).Through the framework, adjustments are fed back orforward to the process tools to maintain CD andoverlay control. The key economic benefits areimproved yield for all products and improved speedbinning for microprocessors.

ConclusionsIn this work, we have introduced a simple micro e c o n o m i cmodel that links metrology, yield, and profitability insemiconductor manufacturing. Our core findings aresummarized below:

• Our grating-based overlay example clearly showedthat yield-relevant metrology (high Y) is a criticalenabler for technology node transitions. Withoutgood device correlation, “corrections” fed to APCsystems could actually generate process error andsubsequent yield loss.

• The dramatic increase in value per wafer at 300 mmjustifies an increase in metrology capability, despitea concomitant increase in metrology cost. The valuere c o v e red by metrology depends on process maturity,product type, metrology capacity, and metrologytool generation.

• The microeconomic model strongly supports optimized,multiple-tool solutions for improvement of yieldand profitability. Integrated monitors, for example,can enhance the effectiveness of stand-alone monitorsbut are generally not viable as the sole metrologysolution in a factory.

• We have shown that success in yield ramps andtechnology node transitions depends on yield-re l e v a n tprocess control capability (high α and Y) despitehigher levels of metrology investment (higher β).

• The aggregate metrology capability of a factory canbe increased by developing new metrology tool tech-nology, by improving the analysis of data, and byc reating a higher level of integration with process tools.

F i g u re 24. Metrology integration increases aggregate capability. The Archer AIM over lay tool in a factory network uses device-cor related gra ting tar -

gets and comprehensive analysis to reduce total measurement uncert a i n t y, enabling overlay control at the 65 nm technology node.



AcknowledgementsWe would like to acknowledge the contributions ofSam Harrell, Tom Long, Scott Ashkenaz, YosefAvrahamov, Arun Chatterjee, Xuemei Chen, GeorgesFalessi, Greg Gray, Matt Hankinson, Eric Kent, SungJin Lee, Marius Lupan, Amir Lev, Ady Levy, JohnMiller, Yoel Moalem, Raman Nurani, Ingrid Peterson,Moshe Preil, Richard Quattrini, Michael Richie, MikeSlessor, Meryl Stoller, Craig Stone, Umar Whitney, andAaron Zuo. A version of this article originally pub-lished in the 2003 SPIE Microlithography proceedings5043, SPIE Microlithography Conference, February2003, Santa Clara, California, USA.

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