Summary Papers_Self-Healing Memory Systems

8/8/2019 Summary Papers_Self-Healing Memory Systems

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1. A Self-Healing Real-Time System Based on Run-Time Self-ReconfigurationManuel G. Gericota, Gustavo R. Alves

Department of Electrical Engineering ISEP

Rua Dr. Antonio Bernardino de Almeida4200-072 Porto - PORTUGAL{mgg, galves}ldee.isep.ipp.pt

Jose M. FerreiraDep. of Electrical and Comp. Eng. FEUP

Rua Dr. Roberto Frias4200-465 Porto - PORTUGAL

jmf fe.up.pt

The article proposes a new Built-In Self-Healing(BISH) methodology, based on run-time self-

reconfiguration for SRAM-based FPGA. A soft microprocessor core implemented in the FPGA will

be responsible for the management and execution of BISH. The FPGA has modular redundancy, it

can detect faults and diagnose, followed by repairing actions. A new methodology is presented that

aims to increase the reliability of real-time systems. Drawbacks of previous approaches are avoided

by the introduction of fault tolerance techniques.

Hardware redundancy was used to increase reliability; one approach is Triple ModularRedundancy (TMR). Is static, achieves fault tolerance without actually detecting it. Each module is

replicated 3 times. A voting element collects the outputs from 3 sources and delivers the majorityvote at output. The reliability of the voter element will determine the reliability of the circuit.

However, the reliability of a voter in a redundant system can be improved by replicating thiselement as well, in a scheme that is called T-TMR (Time Triple Modular Redundancy).

BISH methodology applied only to soft-errors, controlled by a generic soft microprocessorcore (can execute other tasks when self-healing is not active) in the same FPGA and having a

compatible reliability index.Detection of faults scan chain that regularly captures the values at the output of all the

modules and voters.


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Detection-and-fix controller, responsible for detecting data incoherencies, locating the faulty

module and restoring the original configuration (done transparently).


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Scan Chain Boundary-Scan (BS)-like register, updated synchronously with the system clock.Scan chain control signals generated by the detection-and-fix controller. This controller regularly

updates the scan chains and shifts their contents, comparing the output values. Our framework usesthree parallel scan chains, each covering a different module. This approach makes it easier for the

controller to accurately diagnose which of the three module areas was affected by a fault, and totrigger its reconfiguration.


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4. Modeling and Simulation of Multi-Operation Microcode-based Built-In Self Test forMemory Faults

Dr. R.K. Sharma, Aditi SoodDepartment of Electronics and Communications

EngineeringNational Institute of Technology

Kurukshetra, Indiaemail: [email protected], [email protected]

The article presents March Tests algorithms, used for detection of faults on embedded memory on-

chip. Most of these new March algorithms consist of as many as 5 or 6 operations per Marchelement. A new microcoded BIST architecture is presented, capable of employing new test

algorithms like March SS and March RAW, developed for coverage of recently developed staticand dynamic fault models. Just as March SS, any new march algorithm can be implemented using

the same BIST hardware by changing the instructions in the microcode storage unit, without theneed to redesign the entire circuitry.

New trends in memory testing will be driven by the following:

Fault modeling: New fault models should be established in order to deal with the newdefects introduced by current and future (deep-submicron) technologies.

Test algorithm design: Optimal test/diagnosis algorithms to guarantee high defect coverage

for the new memory technologies and reduce the DPM (defect-per-million) level.

BIST: The only solution that allows at-speed testing for embedded memories.


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Clock Generatorgenerates simulated clock waveforms Clock2, Clock3, Clock4, for the rest ofthe circuitry based on the input clock (named Clock1).

Pulse Generatorgenerates a Start Pulse at positive edge of the Start signal which marksstart of test cycle.Instruction Pointerpoints to the next microword, that is the next march operation

to be applied to the memory under test (MUT). Depending on the test algorithm, it is able to i) pointat the same address, ii) point to the next address, or iii) jump back to a previous address.

Instruction Register (IR) holds the microword (containing the test operation to be applied)pointed at by the Instruction Pointer. The various relevant bits of microword are sent to other blocks

from IR.Address Generatorpoints to the next memory address in MUT, according to the test pattern

sequence. It can address the memory in forwards as well as backwards direction.RW Controlgenerates read or write control signal for MUT, depending on relevant microword

bits.Data Controlgenerates data to be written to or expected to be read out from the memory

location being pointed at by the Address Generator.The Address Generator, RW Control and Data Control together constitute the Memory Test

Collar.Comparatorgives the fault waveform which consists of positive pulses whenever the value

being read out of the memory does not match the expected value as given by Test Collar.

5. Testing Molecular Devices in CMOS/Nano Integrated CircuitsPaliwoda, P.C., Maragal, D.S.,Rose, G.S. ;

Dept. of Electr. & Comput. Eng., Polytech. Univ., Brooklyn, OH

This paper starts with the idea of molecular electronics, which may improve the speed and

density of circuits as the limitations of CMOS become stringent. The goal of the paper is to

investigate techniques of detecting defects within molecular electronic structures, which will lead toself-healing memory systems.

The authors propose a molecular memory architecture that consists of the memory array and

column and row decoders, a 4x4 implementation. Decoders are implemented in CMOS technology,memory represented by an array of hysteretic switches is implemented with molecular technology.


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To detect faults in systems where the devices operate at low voltages and currents, signal

amplification using analog CMOS circuitry may be required. Analog Sense Comparator is used todetect short and open circuits in junctions. This tester will be incorporated into a BIST, which will

essentially reconfigure the decoders so that only healthy memory cells are utilized.

For the reconfiguration of the memory, the decoders will be implemented as reconfigurable

decoders which would interface the nano-memory and failure checking logic to isolate the defectiverows and columns, so to effectively utilize the available cells.


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The digital error detection system takes into account the fact that the memory bits fail torespond to changes in the input, i.e. read and write operations to the memory will not yield the

desired results. This detection technique can detect various static faults in molecular devices such asstuck at 1 or 0, open/short circuit, forward/reversed biased faults and hence is more generic in

detecting faults in the memory.This indicated detection system in-conjunction with reconfigurable memory system can be

used to detect, isolate and to reconfigure the molecular memory system during its manufacturingstage. By periodically running the detection system on the molecular memory, faults generated

while in usage can be isolated and thus improve the reliability and life of the memory system.

Other papers:

6. PERFECTORY: A Fault-Tolerant Directory Memory ArchitectureHyunjin Lee, Student Member, IEEE, Sangyeun Cho, Member, IEEE, and

Bruce R. Childers, Member, IEEE

The paper proposes a comprehensive, low-overhead micro-architectural scheme to detect and

correct hardware errors that occur in the coherence directory memory. It uses smart encoding andcoherence protocol adaptation strategies to salvage faulty directory entries.

The hardware architecture consists of 2 parts:- ECC encoder/decoder for the Exclusive state- Online error Detector for the Shared state


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Summary Papers_Self-Healing Memory Systems

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