Submicron Verification Challenges Uri Gruenbaum. Presentation Flow Chart Intro @speed Problems Case...

SubmicronSubmicronVerificationVerificationChallengesChallenges

Uri Gruenbaum

Presentation Flow ChartPresentation Flow Chart

Intro

@speed

Problems

Case study

Intro

Presentation ProgressPresentation Progress

Intro

@speed

Problems

Case study

IntroIntro

What’s going on? What’s going on?

IC features continue to shrink.IC features continue to shrink. Fabrication processes under 130 nmFabrication processes under 130 nm Different size generate different Different size generate different

faults. faults. The faults Distribution is different The faults Distribution is different Good old Stuck-at pattern isn't Good Good old Stuck-at pattern isn't Good

enough.enough.

IntroIntro

@Speed

CompetitionCase study

IntroIntro

In 180 nm we had:In 180 nm we had: Stack at patternStack at pattern Standard memory BIST Standard memory BIST (Built in self test)(Built in self test) IIddqddq

You combine all of them and you get You combine all of them and you get a coverage of ~100%a coverage of ~100%

IntroIntro

@speedproblems

Case study

IntroIntro

In 130 nm and less we have:In 130 nm and less we have: Higher frequencies. Higher frequencies. Different physical Different physical

properties. properties. Much more timing defectsMuch more timing defects

IntroIntro

@speedproblems

Case study

IntroIntroIntroIntro

@speed

problems

Did you know?Did you know? Research from LSI Logic and Intel Research from LSI Logic and Intel

shows that the population of timing shows that the population of timing defects for nanometer designs is defects for nanometer designs is ~2%~2%

Case study

IntroIntroIntroIntro

@speed

problems

Example:Example: 130 nm fabrication process 130 nm fabrication process Yield average of 70%Yield average of 70% Static fault testing coverage of 100%Static fault testing coverage of 100% 2% left unchecked…2% left unchecked… 50% of them on average are ok50% of them on average are ok We will have a defect rate of 0.7%We will have a defect rate of 0.7% DPM of 7000DPM of 7000

Unacceptable

Case study


Intro

@speed

Problems

Case study

@speed @speed

Background Background Been available for many yearsBeen available for many years A timing defect test patternA timing defect test pattern Used so far to test very high Used so far to test very high

speed devices & very accurate speed devices & very accurate goals goals

Intro

@speed@speed

problems

Case study

@speed-before scan @speed-before scan Intro

@speed@speed

CompetitionOur SolutionWhat next?

clock

@speed- scan @speed- scan insertion insertion

Intro

@speed@speed

CompetitionOur SolutionWhat next?

clock

SE

SI

SO

@speed-shift phase @speed-shift phase Intro

@speed@speed

problems

clock

SE = 1

SI

SO

clock

SI

1 10

1 10 101

Case study


@speed@speed

problems

0 11

clock

SE = 1

SI

SO

clock

SI

1 10

Case study

@speed-capture @speed-capture Intro

@speed@speed

problems

0 11

clock

SE = 0

SI

SO

clock

SI

1 10

A B C

A B C

Case study

@speed-capture @speed-capture Intro

@speed@speed

problems

B CA

clock

SE = 0

SI

SO

clock

SI

1 10

A B C

Case study


@speed@speed

Problems

B CA

clock

SE = 1

SI

SO

clock

SI

1 10 0

0 A B C

Case study

@speed Vs Stuck at@speed Vs Stuck atIntro

@speed@speed

problems

Case study

@speed-Accurate @speed-Accurate clocksclocks

Intro

@speed@speed

problems

Case study

There can be variations between the testers clock and the PLL clocking

@speed - solution@speed - solution One solution is having the ATPG One solution is having the ATPG

(automatic test pattern generation) (automatic test pattern generation) to decide which clock is necessary to decide which clock is necessary

Intro

@speed@speed

problems

Case study


Intro

Market

Problems

Case study

ProblemsProblems

Test patterns for transition Test patterns for transition faults are not as efficient as for faults are not as efficient as for stuck at faultsstuck at faults

Transition faults test = 5 times Transition faults test = 5 times in size as a static fault testin size as a static fault test

When combined ,expensive When combined ,expensive tester reloads is performedtester reloads is performed

Intro

Market

ProblemsProblems

Case study

ProblemsProblems

An interesting fact:An interesting fact: Intro

Market

ProblemsProblems

Case studyTransition test pattern detect a significant percentage of stack at faults

Starting to get the picture?

ProblemsProblems

If you need to add TFP reduce If you need to add TFP reduce the number of SAP. the number of SAP.

Do it by creating the TAP first Do it by creating the TAP first and the SAP next.and the SAP next.

Intro

Market

ProblemsProblems

Case study


The Need

@speed

Problems

Case study

Case studyCase study

The goal:The goal:

Getting the best possible test Getting the best possible test coverage without doing coverage without doing expensive tester memory expensive tester memory reloads.reloads.

The NeedMarke

tproblems



Characteristic of test design:Characteristic of test design: The NeedMarke

tproblems



For the design, the test requirements are :For the design, the test requirements are :The NeedMarke

tproblems


Tester can hold up to 10,000 test patterns

The highest priority is to get max coverage for SAF

The test coverage for the TF must be as high as possible as long as it still fits the memory.


ResultResult::The NeedMarke

tproblems



Truncating the TDF results in a Truncating the TDF results in a significant lost in transition significant lost in transition coveragecoverage

TDF coverage 85.14% TDF coverage 85.14% 63.93% 63.93% Clearly not idealClearly not ideal

The NeedMarke

tproblems



How can we improve it?How can we improve it? The NeedMarke

tproblems

Case studyCase study Recognize that for each TDF its equivalent SAF is also detected

remove the least effective patterns


ResultResult::The NeedMarke

tproblems


Case studyCase studyThe NeedMarke

tproblems


Submicron Verification Challenges Uri Gruenbaum. Presentation Flow Chart Intro @speed Problems Case...

Documents

Transcript of Submicron Verification Challenges Uri Gruenbaum. Presentation Flow Chart Intro @speed Problems Case...