Sub-expression elimination

• Logic expressions:– Performed by logic optimization.– Kernel-based methods.

• Arithmetic expressions:– Search isomorphic patterns in the parse trees.– Example:– a= x+ y; b = a+ 1; c = x+ y;– a= x+ y; b = a+ 1; c = a;

Examples of other transformations

• Dead-code elimination:– a= x; b = x+ 1; c = 2 * x;– a= x; can be removed if not referenced.

• Operator-strength reduction:– a= x2 ; b = 3 * x;– a= x * x; t = x<<1; b = x+ t;

• Code motion:– for ( i = 1; i < a * b) { } – t = a * b; for ( i = 1; i < t) { }

Strength reduction

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Control- flow based transformations

• Model expansion.– Expand subroutine flatten

hierarchy.– Useful to expand scope of other

optimization techniques.– Problematic when routine is

called more than once.– Example:– x= a+ b; y= a * b; z = foo( x, y) ;– foo( p, q) {t =q-p; return(t);} – By expanding foo:– x= a+ b; y= a * b; z = y-x;

• Conditional expansion • Transform conditional into parallel execution with test at the end.• Useful when test depends on late signals.• May preclude hardware sharing.• Always useful for logic expressions.• Example:•y= ab; if ( a) x= b+d; else x= bd; can be expanded to: x= a( b+ d) + a’bd;•y= ab; x= y+ d( a+ b);

Pipelining

Associativity Transformation

FIR Parallelization

FIR PARALLELIZATION

FIR Filter Parallelization

FIR parallelization: two working phases

IIR filter recursive function

Recursive Function

Interlaced Accumulation Programming for LowPower

4. Register Transfer Level Design

FIR3 Block Diagram and Flow Graph

High-Level Power Estimation

• Pcore = PDP + PMEM + PCNTR + PPROC

• PDP = PREG +PMUX +PFU + +PFU, where PREG is the power of the registers

• PMUX is the power of multiplexers• PFU is the power of functional units• PINT is the power of physical interconnet capacitance

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High-Level Power Estimation: PREG

• Compute the lifetimes of all the variables in the given VHDL code.• Represent the lifetime of each variable as a vertical line from statement i through

statement i + n in the column j reserved for the corresponding varibale v j .• Determine the maximum number N of overlapping lifetimes computing the

maximum number of vertical lines intersecting with any horizontal cut-line.• Estimate the minimal number of N of set of registers necessary to implement the

code by using register sharing. Register sharing has to be applied whenever a group of variables, with the same bit-width b i .

• Select a possible mapping of variables into registers by using register sharing• Compute the number w i of write to the variables mapped to the same set of

registers. Estimate n i of each set of register dividing w i by the number of statements S: i =wi/S; hence TR imax = n i f clk .

• Power of latches and flip flops is consumed not only during output transitions, but also during all clock edges by the internal clock buffers

• The non-switching power PNSK dissipated by internal clock buffers accounts for 30% of the average power for the 0.38-micron and 3.3 V operating system.

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Behavioral Synthesis• loop unrolling : localize the data to reduce the activity of the inputs of the

functional units or two output samples are computed in parallel based on two input samples.

Neither the capacitance switched nor the voltage is altered. However, loop unrolling enables several other transformations (distributivity, constant propagation, and pipelining). After distributivity and constant propagation,

The transformation yields critical path of 3, thus voltage can be dropped.• Clock Selection : Choose optimal system clock period Eliminate slacks/improve resource

utilization and Enable greater voltage scaling• Module selection : For each operation, choose library template• Flow graph restructuring : pull out operations on the critical cycle.

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Critical Path• Longest delayed path from input to

output in combinational logic

• Determine operating clock frequency

• Resizing non-critical path transistor (In-Place Optimization)

• Critical path in Synchronous Sequential logic

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Retiming

Flip- flop insertion to minimize hazard activity moving a flip- flop in a circuit

Exploiting spatial locality for interconnect power reduction

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