Structured Electronics Assignment

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STRUCTURED ELECTRONICS ASSIGNMENT

5MD30, Quartile 3, 2010

Mayur Sarode

student id:0730085

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Contents A. General configuration ..................................................................................................................................... 4

1.1 Motivation of the choice of feedback ....................................................................................................... 4

1.2 Numerical value of the feedback configuration ........................................................................................ 5

1.3 Implementation of feedback configuration ............................................................................................... 5

1.4 Implementing the transfer function .......................................................................................................... 6

B. Noise Figure .................................................................................................................................................. 8

2.1 Derive the expressions for the CE and CS configurations .Explain the impact of collector and drain current,

input impedance and the input internal resistor on the noise figure. ..................................................................... 8

2.1(a) Expression for the noise figure of the single ended common emitter stage ............................................... 8

2.3(a) Optimum noise figure as a function of Collector Current ......................................................................... 12

2.4(a) Calculate the numerical value of these configurations using the spice models A and B ........................... 12

2.1(b) Expression for the noise figure of the differential common emitter stage ................................................. 14

2.3 (b) Optimum noise figure as a function of Collector Current ........................................................................ 18

2.4 (b) Calculate the numerical value of these configurations using Spice models A and B ............................... 19

2.5(b) Simulate the transfer function for the differential BJT pair ...................................................................... 20

2.6 (a) Expression for Common source configuration for a JFET amplifier in single ended mode. ....................... 20

2.8(a) Optimum noise figure as a function of drain Current ............................................................................... 25

2.9(a) Calculate the numerical value of these configurations using the spice model A and B .............................. 25

2.10(a) Simulate the transfer function for single ended JFET ............................................................................. 27

2.6 (b) Expression for Common source configuration for a JFET amplifier in differential model ......................... 28

2.2(a)(b),2.7(a)(b) Compare the capabilities of the two technologies.................................................................. 33

2.8(b) Optimum noise figure as a function of drain Current ............................................................................... 32

2.9(b) Calculate the numerical value of these configurations using the spice model A and B ............................. 33

2.10(b) Simulate the transfer function .............................................................................................................. 35

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C: Feedback and noise ...................................................................................................................................... 36

4.1 Implement the first stage of the feedback configuration of assignment 1 by a JFET or a BJT differential

stage……………… ................................................................................................................................................. 36

4.2 Derive an expression of the noise figure for the total feedback system. Explain the impact of Collector

Current, input impedance and the internal input resistor on the noise figure. ................................................... 36

4.3 Calculate the numerical value of the feedback configuration ....................................................................... 41

4.4. Implement the feedback configuration in the simulator in use and simulate the transfer function ............. 41

4.5 Simulate the transfer function ..................................................................................................................... 42

C. Last Stage .................................................................................................................................................... 43

6. Implement the Last stage in the configuration in A.1 by a CMOS or Bipolar ................................................. 43

7. Determine the collector or the drain current ................................................................................................... 43

D. Open Loop gain ............................................................................................................................................ 45

4.1 Determine the voltage gain transfer function as a function of frequency. ...................................................... 46

4.2. Determine the positioning of the poles and zeros ........................................................................................ 46

4.3 Remove the ideal nullator and determine the open and closed loop function of the feedback .................. 49

E. Closed loop gain 5.1 Determine the transfer function and the noise figure of closed loop…………………………………………………………53 F. Stability

6.1 Check the stability of the system ................................................................................................................. 54

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Assignment 1: General Feedback Configuration

A. General configuration

In this assignment we simulate a negative feedback amplifier circuit. The design of the circuit consists of two parts.

1. Design of the amplifier using a nullor.

2. Design of the feedback loop.

Amplifier is an active component and is modeled by a nullor. Nullor is a combination of a norator and a nullator.

A nullor is chosen as it has infinite voltage gain , current gain ,transconductance and transimpedance. The nullor

can be assumed to be an ideal amplifier. In ADS it is represented by a two port network (A B C D chain matrix

selected from Equation based linear library). Due to high input impedance of an amplifier, values of the chain

matrix are either 0 or very small. The nullor adapts the output such a way that the input current and voltage is 0. In

our simulation we have kept the value ABCD parameters as e-10

.

The specifications of the circuit are given in table 1 and table 2. The signal bandwidth is specified to between 50

Hz to 1.5 MHz.

1.1 Motivation of the choice of feedback

From the source specification of the assignment, the input is a piezoelectric sensor which is specified by the

charge. Taking the output of the sensor over a period of time t , current can be measured. The specifications of the

load indicate output is voltage. It can be inferred that we need to design a negative feedback topology having input

as current and output as voltage. The kind of topology is shown in figure and is called a shunt – shunt feedback.

Negative feedback is chosen as the gain at the amplifier can be controlled. Although the gain of the amplifier is

reduced, it improves the gain sensitivity, bandwidth and doesn’t improve the input noise of the circuit. The input

and output impedance of the circuit can be modified without affecting the gain of the circuit. Negative feedback

reduces output signal clipping.

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Figure 1.1 Choice of feedback

1.2 Numerical value of the feedback configuration

The asymptotic gain of the chosen amplifier configuration is given by

The impedance in the feedback configuration is a capacitance of 1nF value.

1.3 Implementation of feedback configuration

Figure 1.2: ADS simulation of feedback circuit with nullor

In ADS the piezoelectric current source is represented by a frequency dependent sinusoidal A.C current

source .The amplitude of the sinusoidal current source varies with frequency given by the equation.

, / 2)(2 * spolar freq I

1

12

0.5

100

0.5 1

100*10

s

s

f

VlZ

Is

Vl volts

Is pC

Z nFC

6

The AC frequency is sweeped from 10 Hz to 1.5 MHz in step of 10 Hz to plot the transfer function and the

output voltage.

1.4 Implementing the transfer function

Figure 1.3: the transfer function simulated in ADS is given by which is the measure of gain of feedback the

circuit

The transfer function simulated in Fig. 1.3 is given below which is the measure of gain of feedback the circuit.

Thus the circuit is within the maximum gain limits specified (SNR 70 dBm) in the assignment. The gain varies with

frequency because the transfer function of capacitance is dependent on the frequency of the input signal.

The second transfer function simulated is the variation of the output voltage with the sweep frequency of the

amplifier as shown in Fig 1.4. It can be inferred that the output voltage is independent of frequency. Thus the

amplifier is working in the linear region.

10log( )in

VlZ

Is

7

Figure 1.4 Magnitude of output voltage

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Assignment 2: Noise Figure

B. Noise Figure

2.1 Derive the expressions for the CE and CS configurations .Explain the impact of collector and

drain current, input impedance and the input internal resistor on the noise figure.

2.1(a) Expression for the noise figure of the single ended common emitter stage

The noise model of the single ended common emitter BJT is as shown below

Figure 2.1 small signal noise model of a BJT

ic and ib are shot noise currents and vnb is the noise voltage due to the base resistance. ibf is the flicker noise current.

It is too small to be significant, hence we can ignore it. We need to bring the noise current source ic the input side.

After the network transformation, the noise model looks as follows.

DIcIb

BIc

Rb

Vnb

Figure 2.2 small signal noise model of a BJT with the collector noise transformed to input

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The values of the above noise sources are as follows

For the BJT, B = Vt/Ic and D = 1/Beta. The noise course Dic can be neglected since the value of D is very small

due to the large value of Beta. After neglecting Dic, the remaining noise sources are un-correlated. Thus we need to

add their power spectral densities. The PSD of the noise sources are written as follows.

Vnb2 = 4KTRb ib

2 = 2qIb

(B*ic)2 = B

2*2qIc Vs

2 = 4KTRs

If we transform the current source ib to a voltage source by Norton-thevenin transform, the value of the voltage

source is (Rs + Rb)*2qIb

The expression for Noise Figure is written as follows.

NF = 10*log10(1 + (NoiseDUT / Noisein))

NoiseDUT = 4KTRb + B2*2qIc + (Rs + Rb)2qIb

Simplifying and substituting the constants, we get

NoiseDUT =4KTRb + 2q(Vt)2/Ic + (Rs + Rb)

2*(1/Beta)*2qIc

Noisein = 4KTRs

Thus the final expression for the noise figure is

NF = 10log10(1 + (4KTRs + 4KTRb + 2q(Vt)2/Ic + (Rs + Rb)

2*(1/Beta)*2qIc) / 4KTRs)

The above equation is simulated in MATLAB and compared with the curve obtained in ADS.

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Figure 2.3 variation of noise figure with the collector current simulated in ADS

Figure 2.4 variation of noise figure with the collector current simulated in MATLAB

The noise figure depends on three variables namely, collector current, base resistance and the internal source

resistance. The relation to the collector is apparent from the above figures. Initially the noise figure falls as a

function of the collector bias current. For the particular value of the collector bias current, the noise figure is lowest.

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After this point, the noise figure increases as a function of the collector bias current. The point where the noise

figure is lowest is point of optimum collector bias current. Note that, optimum collector current for noise figure

does not guarantee best gain.

The relation of NF with the input base resistance is shown in the following graph.

Figure 2.5 variation of noise figure with the base resistance simulated in MATLAB

The Noise Figure increases non-linearly with the input base resistance.

.

Figure 2.6 variation of noise figure with source resistance simulated in MATLAB

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The relation of the noise figure to the internal source resistance is exponential.

2.3(a) Optimum noise figure as a function of Collector Current

Reiterating the expression for the noise figure, we can see its dependence on the collector bias current.

NF = 10log10(1 + (4KTRb + 2q(Vt)2/Ic + (Rs + Rb)

2*(1/Beta)*2qIc) / 4KTRs)

If we keep the source and the internal base resistance constant, we can differentiate the above equation with respect

to the collector bias current. To obtain a minima for the NF curve, we equate the slope to zero. Thus,

NF / Ic = -2qVt2/Ic

2 + (Rs + Rb)

2*D*2q = 0

2qVt2*Ic

2 = (Rs + Rb)

2*D*2q

Ic (optimum) = Vt / (Rs + Rb)*D

2.4(a) Calculate the numerical value of these configurations using the spice models A and B

For the Spice model A, the transistor is NPN with Rb = 300

The NF curve is shown below.

Figure 2.7 variation of noise figure with source resistance simulated in MATLAB for spice model A

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The optimum noise figure calculated is 8.669 and the optimum collector bias current is 0.0014 A.

For the Spice model B, the transistor is PNP with Rb = 130

The NF curve is shown below.

Figure 2.8 variation of noise figure with source resistance simulated in MATLAB for spice model B

The optimum noise figure calculated is 5.782 and the optimum collector bias current is 0.0027 A.

The optimum noise figure calculated is 5.782 and the optimum bias current is 0.0027 A.

2.5(a) simulating the transfer functions

Figure 2.9 Single ended BJT simulation

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2.1(b) Expression for the noise figure of the differential common emitter stage

The noise model for the differential common emitter BJT is as shown below.

Figure 2.10 transferring the collector shot noise to the input of the differential pair

Figure 2.11 Equivalent current and voltage source at the input

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Figure 2.12 Applying delta current transformation

Figure 2.13 Cancelling out redundant sources

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Figure 2.14 transferring the sources to the first differential input

Figure 2.15 reduced small signal model of differential

In the above figure, the noise sources BCEic2 and BCEic1 result from the transformation of the collector shot noise to

the input ports. ub1 and ub2 are the noise sources due to the base resistances of the two transistors.

The noise current sources i1 and i2 are written as

i1 = ib1 + DCE*ic1 i2 = ib2 + DCE*ic2

We must note that the sources BCEic2 and DCE*ic2 are correlated, as well as, BCEic1 and DCE*ic1.

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We transform the current sources to voltage sources using Norton-Thevenin transformation. The resulting circuit

diagram is drawn below.

ib1*(2Rb+Rs)/2ub1Bceic1ub2Bceic2Rb

Rb

Ib2*(2Rb+Rs)/2

Figure 2.16 Applying thevenin theorem

The expression for the noise figure is given as

NF = 1 + (NoiseDUT / Noisein)

Adding the correlated sources and adding the power spectral densities of the uncorrelated sources, the expression

for NoiseDUT is obtained as follows.

NoiseDUT = 8KTRb + 2*BCE2*q*Ic + (2Rb + Rs)

2*q*Ib + 2(2Rb + Rs)

2*(DCE

2)q*Ic –2DCE*BCE*2qIc

Simplifying and substituting the constants, we get

NoiseDUT = 8KTRb + (8e-22 / Ic) + (1.8e-16*Ic) - 2DCE*BCE*2qIc

Thus, from the above equation, the expression for Noise figure is written as,

NF = 10log (1 + (8KTRb + (8e-22 / Ic) + (1.8e-16*Ic) - 2DCE*BCE*2qIc) / 4KTRs )

The above equation is simulated in MATLAB and compared with the curve obtained in ADS.

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Figure 2.17 Variation of Noise figure with collector current Ic1 and Ic2 simulated in Matlab

Figure 2.18 Variation of Noise figure with collector current Ic1 and Ic2 simulated in ADS

2.3 (b) Optimum noise figure as a function of Collector Current

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NF = 10log (1 + (8KTRb + (8e-22 / Ic) + (1.8e-16*Ic) - 2DCE*BCE*2qIc) / 4KTRs )


to the collector bias current. To obtain minima for the NF curve, we equate the slope to zero. Thus,

Ic (optimum) = ((8e-22/(1.8e-162 DCE*BCE*2qIc )*4KTRs))^0.5

2.4 (b) Calculate the numerical value of these configurations using Spice models A and B

For the Spice model A, the transistor is NPN with Rb = 300

Readout

m2

m2indep(m2)=plot_vs(nf(2),IC1.i+IC2.i)=14.240IBB=0.000005

0.002

For the Spice model B, the transistor is PNP with Rb = 130

0.0002 0.0004 0.0006 0.0008 0.0010 0.0012 0.0014 0.0016 0.0018 0.00200.0000 0.0022

10

11

12

9

13

IC1.i+IC2.i

nf(2

)

0.0029.822

m1


0.002

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The noise figure depends on three variables namely, collector current, base resistance and the internal source

resistance. The relation to the collector is apparent from the above figures. Initially the noise figure falls as a

function of the collector bias current. For the particular value of the collector bias current, the noise figure is lowest.

After this point, the noise figure increases as a function of the collector bias current. The point where the noise

figure is lowest is point of optimum collector bias current. Note that, optimum collector current for noise figure

does not guarantee best gain.

The NF for spice model B is lower than the spice model A because of the lower value of the base resistance of the

spice model B.

The variation of the base resistance and the source resistance have the same curves as that of single ended BJT

transsitor shown in Figure 2.5 and Figure 2.6

2.5(b) Simulate the transfer function for the differential BJT pair

2.6 (a) Expression for Common source configuration for a JFET amplifier in single ended mode.

The small signal noise model is used to calculate the noise figure of the CS JFET.

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Figure 2.19 Small signal noise model of a JFET

Figure 2.20 Small signal noise model of a JFET with the drain and flicker noise transferred to input

Figure 2.21 Equivalent thevenin of the noise model

Fig 2.19 shows the noise model of a JFET amplifier. The contribution to the noise figure is from the following

sources

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m1indep(m1)=plot_vs(Id.i, Vds)=0.025Vgs=0.600000

2.000

2 4 6 80 10

0.005

0.010

0.015

0.020

0.025

0.000

0.030

Vds

Id.i

Readout

m1

m1indep(m1)=plot_vs(Id.i, Vds)=0.025Vgs=0.600000

2.000

id= thermal noise in the channel (channel conductance between the source and drain)

idf = flicker noise between source and the drain

ig= shot noise generated by saturation current Ig

iig =induced gate noise voltage

Idss=drain saturation current

After ignoring the contributions of iig , idf ,The Power spectral density of DUT(Pdut) and the source(Ps) is given by

equations … the circuit in Figure 2 is used to drive the expression for the noise figure expression.

1

.gs m

BC S g

.

( ).gd gs

gd m

C C SD

C S g

2 4d mi KTcg

2 22 4 *(2 )

3

gsg

m

KT f Ci

g

0.5( 2 / )( * )m thg V Idss Id Variation of the drain current with drain source voltage at

Vgs=0

2( ( )) 4 ( ) 410log[1 ]

(4 )

( )1

( )

B D Rg R

Pdut f

s KTcgm Rs Rg

FP

ig KTRgNF

KT s

f

R

s

Vth is the threshold current which is found from the specifications in the ADS (-4.449). Idss is the drain

saturation current. The drain saturation current was found to be 0.025 A by making Vgs=0

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Impact of drain current on the noise figure

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.451

2

3

4

5

6

7

8

9

X: 0.25

Y: 1.511

Id(drain current)

Noi

se fi

gure

[dB

]

Figure 2.22 Variation of Noise Figure with drain current simulated in MATAB

0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24 0.26 0.280.00 0.30

2

4

6

8

10

12

0

14

Id.i

nf(

2)

Readout

m2

m2Id.i=plot_vs(nf(2),Id.i)=0.618Vgs=0.700000

0.264

Figure 2.23 Variation of Noise Figure with drain current simulated in ADS

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Impact of gate resistance Rg on the noise figure

0 10 20 30 40 50 60 70 80 90 1000.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

gate resistance(Rg)

Noi

se fi

gure

[dB

]

Figure 2.24 Variation of Noise Figure with gate resistance simulated in MATLAB

Impact of source resistance on the noise figure

0 10 20 30 40 50 60 70 80 90 1000

2

4

6

8

10

12

14

source resistance(Rs)

Noi

se fi

gure

[dB

]

Figure 2.25 Variation of Noise Figure with source resistance simulated in MATLAB

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Figure 2.26 Variation of Noise Figure with source resistance simulated in ADS

2.8(a) Optimum noise figure as a function of drain Current


2( ( )) 4 ( ) 410log[1 ]

(4 )

B D Rg Rs KTcgm Rs Rg ig KTRgNF

KTRs


to the collector bias current. To obtain minima for the NF curve, we equate the slope to zero. Thus,

2( 2/ ) . .

2 2( )(2 )

( )2( ))Idopt

Vt

Rg Rs

h Idss c B

pif Cgs

D Rg Rs

2.9(a) Calculate the numerical value of these configurations using the spice model A and B

For the Spice model A, the JFET parameters are with Cgs = 5.74 pF ,Cgd=6.46pF. The noise figure as a function of

drain current is plotted in Fig,2,23. The noise figure was found to be 0.632 dB

For the Spice model B, the JFET parameters are with Cgs = 47.7 pF , Cgd=47.7 pF. The noise figure as a function

of drain current is plotted in Fig 2,24. The noise figure was found to be 1.596 dB. The lower noise figure for spice

model A is due to its lower value of gate source capacitance.

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27

2.10(a) Simulate the transfer function for single ended JFET

Figure 2.29 Single ended JFET noise figure simulation

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2.6 (b) Expression for Common source configuration for a JFET amplifier in differential model

Vng2

Rg2

Ig2Id1

Vns

Rs

Vng1

Rg1

Ig1 Id1 Rs2

Vs2Vs1

Vng2

Rg2

Ig2Rs

Vng1

Rg1

Ig1Did1

Rs2

Vs2Vs1

Bid1Bid2

DId2

Figure 2.30 (a) small signal model of a differential JFET amplifier

(b) With the drain shot noise transferred to input

Rs

2Rg

Vs1

Bid1 Bid2

Un1+un2I2

I1

Figure 2.31 Equivalent current and voltage noise sources

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Ueq

Ieq

Figure 2.32 Equivalent current and voltage noise sources (further simplified)

ug1 Bid2

Rg

Rg

(2Rg+Rs)I1(2Rg+Rs)I2

Bid2ug2

Rs

Figure 2.33 Equivalent thevenin noise model

1 11

2 22

2 2 2 2 2 2 21 2 1 2

10

1

2 2 2 2 2 2 2(8 1 2 ( 1 2 )( 2 ) )10log (1 )

;

(8 ( )( 2 ) )

4

4

s gdut

s

dut

s

s

s

PNF

KTRg B id B id i i Rs RgNF

i ig Did

i ig Did

P KTRg B id B id i i R R

P KTR

P

KTR

I

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Impact of drain current on noise figure

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.82.5

3

3.5

4

4.5

5noise figure plot for differential configuration of cmos

Id(drain current)

Nois

e fig

ure[

dB]

Figure 2.34 Variation of Noise figure with drain current in MATLAB

0.1 0.2 0.3 0.4 0.50.0 0.6

10

20

0

30

Id1.i+Id2.i

nf(

2)

0.5471.503

m1

m1indep(m1)=plot_vs(nf(2),Id1.i+Id2.i)=1.149Vgs=0.700000

0.528

Figure 2.35 variation of Noise figure with drain current simulated in ADS

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The noise figure of the differential JFET decreases exponentially with the variation of drain current. The drain

current is varied by changing the gate current to the JFET.The noise figure of a JFET doesn’t have a minimum

because the NF depends on the gate source capacitance Cgs. Cgs is not a constant but varies with the frequency of

the input signal.

A difference of 1~1.5 dB can be seen from the plots of matlab and ADS. This is due to the assumptions that have

been taken while simulating the noise figure in the both the softwares. In matlab , the contribution of the shot noise

generated by the saturation current Ig (ig in the above equation) flowing through the reversed biased source and

drain is small and neglected.

Impact of gate resistance on the noise figure

0 10 20 30 40 50 60 70 80 90 1003

3.5

4

4.5

5

5.5

6

6.5

7

7.5


Rg

Noi

se f

igur

e[dB

]

Figure 2.36 variation of Noise figure with gate resistance simulated in MATLAB

As the internal gate resistance is varied, the noise figure of the differential configuration increases exponentially.

The noise figure of the differential pair is proportional to the gate resistance and directly contributes to the noise of

the system.

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Impact of source resistance on the noise figure

Figure 2.37 variation of Noise figure with source resistance simulated in ADS

0 10 20 30 40 50 60 70 80 90 1002

4

6

8

10

12

14


Rs

Noi

se fi

gure

[dB

]

Figure 2.38 variation of Noise figure with source resistance simulated in MATLAB

The noise figure for a differential configuration of JFET decreases exponentially with source resistance.This is

because the ratio of Noise figure is caclulated with repsect to the source resistance noise (4KTRs). For impdance

matching , the source resistance is kept at 50 ohm.

33

2.4(a)(b),2.8(a)(b) Compare the capabilities of the two technologies.

JFETS have high input impedance compared to BJT transistors

JFET is based on CMOS technology and has the following advantages.

Has less power dissipation than BJT’s

Lower noise margin (From the noise figure plots of the two circuits.)

Has better packaging density and integration

Can be used as a good switch in digital design.

Bipolar transistors are

Have higher gm then the CMOS technology so results in a higher gain.

Higher gain at the output

Faster than CMOS due to higher ft

BJT’s are better modeled and hence more predictable

Consume base current and have more area than MOSFET’s

JFETS have higher input impedance than the BJT’s

Noisier than JFET’S

2.8(b) Optimum noise figure of differential JFET as a function of drain Current

The optimum collector current for minimum noise figure is found out differentiating the expression below wrt to Ic .

10

2 2 2 2 2 2 2(8 1 2 ( 1 2 )( 2 ) )10 log (1

4 s

KTRg B id B id i i Rs RgNF

KTR

Idopt =

2 2 22/3

2

( 2 ) (4 )(4 )(2 )( )

23( ) .2

Rs Rg KTRs KT pif Cgs

Idss BVth

2.9(b) Calculate the numerical value of these configurations using the spice model A and B

34

For the Spice model A, the JFET parameters are with Cgs = 5.74 pF , Cgd=6.46pF. The noise figure as a function of

drain current is plotted in Fig,2,23

For the Spice model B, the JFET parameters are with Cgs = 47.7 pF , Cgd=47.7pF. The noise figure as a function

of drain current is plotted in Fig 2,24 .

From the curves it can be inferred that noise figure of spice model B has a lower noise figure than that of spice

model A. this is because a larger capacitance results in a smaller impedance ( Z=1/(2pifCgs)) ,hence a lower

contribution to noise figure .

Figure 2.39 Variation of Noise figure with drain current for spice model A simulated in ADS

35

Figure 2.33 Variation of Noise figure with drain current for spice model B simulated in ADS

2.10(b) Simulate the transfer function

Figure 2.40 Simulation of JFET differential pair in ADS

36

Assignment 3: Feedback and Noise

C: Feedback and noise

4.1 Implement the first stage of the feedback configuration of

assignment 1 by a JFET or a BJT differential stage. The first stage of the feedback circuit is designed to optimize noise. Noise is optimized first because

in the first stage the bandwidth of the system is infinite, there is no distortion .Hence noise, and

distortion and bandwidth are orthogonal to each other. In a cascade amplifier the last stage will have

larger amplitude of signals compared to the first stage. Hence the effect of noise will be more at the

1st stage when the signal level is low than in the last stage where noise level is negligible compared

to the signal level. If the gain of the 1st stage is made large, then the noise contribution of the

subsequent stages of an amplifier is negligible. Hence if we design the 1st stage for noise, then noise

contributions of the subsequent stages can be neglected in the analysis of the circuit. Noise behavior

can be analyzed in presence of the nullor. The different noise sources due to noise producing

components of an active circuit can be modeled by an equivalent voltage and current noise source at

the input or at the output. If the noise is modeled at the input then the noise can be compared with

the source signal to measure the SNR at the input. Modeling noise at the output gives the exact

measurement of the noise sources. Noise modeled at the output can be transferred to the input using

the ABCD chain matrix. The first stage of the feedback is implemented b a differential BJT

amplifier.

From the Vce Vs collector current plot for differential mode BJT, a collector current of 1.8 m A is

inferred. The β (current gain factor) of BC550 ,hence the biasing current IB =Ic/ β.The base current

for th differential pair is 4.80 µA.

4.2 Derive an expression of the noise figure for the total feedback system.

Explain the impact of Collector Current, input impedance and the internal

input resistor on the noise figure.

In this assigment the feedback is implemented with a BJT differential pair configuration

Figure 3.1 Blcok diagram of the amplifier cirucit withfeedback

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From the equivalent noise model of the BJT differential pair derived in the Assignment B,

1 2 1 2

1 2

1 11

2 22

( )

;

n

n

where

V Ub Ub B ic ic

i i

i ib Dic

i ib Dic

i

Figure 3.2 applying voltage transform

Figure 3.3 Applying thevenin to Norton transformation

Figure 3.4 Applying current transform

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Figure 3.4 Equivalent noise current at the input

( )eq n s f nIn i s C C V

(Rs+2Rg)ineq

Figure 3.5 Equivalent thevenin model

2 2

2 2

2 2

2 21 1 2 2 1 2 1 2

10

(2 ) ( )

(2 ) ( ( ) )

(2 ) ( ( ) )

(2 ) ( ( )( ( )))

4

10log (1 )

dut b s eq

dut b s n s f n

dut b s n s f n

dut b s s f

P R R In

P R R i s C C V

P R R i s C C V

P R R ib Dic ib Dic s C C Ub Ub B ic ic

Ps KTRs

PdutNF

Ps

D*id1 is a very small value is neglected in calculation.

Impact of collector current on the noise figure

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0.001

0.0005 0.0010 0.0015 0.0020 0.0025 0.00300.0000 0.0035

15

16

17

18

19

14

20

IC1.i+IC2.i

nf(2

)

Readout

m1


0.001

Figure 3.6 Variation of noise figure with collector current in ADS

0 0.005 0.01 0.015 0.02 0.025 0.03 0.03514

16

18

20

22

24

26

28

X: 0.0152

Y: 16.05

Noi

se fi

gure

collector current (Ic)

Figure 3.7 Variation of noise figure with collector current in MATLAB

Impact of variation of base resistance Rb

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0 50 100 150 200 250 3005

10

15

20

25

30

35

40

45N

oise

fig

ure

base resistance(Rb)

Figure 3.8 Variation of noise figure with base reisistance in MATLAB

Impact of variation of source resistance Rs

Figure 3.8 Variation of noise figure with source resistance in ADS

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0 10 20 30 40 50 60 70 80 90 10015

16

17

18

19

20

21

22

23

24

25

X: 31

Y: 15.78

Noi

se f

igur

e

base resistance(Rb)

Figure 3.9 Variation of noise figure with base resistance in MATLAB

4.3 Calculate the numerical value of the feedback configuration The numerical value of the noise figure in feedback configuration is 14.56 dB.

4.4. Implement the feedback configuration in the simulator in use and

simulate the transfer function

Figure 3.10 Implementation of feedback circuit with the differnetial input in ADS

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4.5 Simulate the transfer function From figure 3.2 it can be inferred that that SNR of the feedback circuit constantly increases to 132 dB .

This may be due to the variation of impedance of capacitance with frequency.

From Fig 3.3 ,it can be observed the power gain of the circuit constantly increases with frequency.

Figure 3.11 the singal to noise ratio of the feedback cirucit.

Figure 3.12 The power gain of the feedback configuration

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Assignment 3: Last Stage

C. Last Stage

6. Implement the Last stage in the configuration in A.1 by a CMOS or Bipolar

The last stage is designed to avoid clipping of the output signal . to bias the transistor so that output

signal never clips for the specific signal range, the maximum load condition has to be found out. The

total load at the output stage can be calculated by

It can be expressed in the form

Where the load is calculated for the maximum possible frequency of the input signal (1.5 MHz). The

load impedance was found out to be

Z(s)~92 ohm

7. Determine the collector or the drain current

The maximum output current for a constant output voltage of 0.5 volt and load impedance of 92 ohm is

5.4 mA . The maximum output current is chosen 50 % beyond the minimum which is 8.1 mA . The bias

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current (base current) is calculated by the formula. The bias current (base current ) is found out from the

Ic vs Vce plot. It was inferred to be 21 uA.

2 4 6 80 10

0.000

0.002

0.004

0.006

-0.002

0.008

VCE

IC.i

Readout

m1

m1indep(m1)=plot_vs(IC.i, VCE)=0.003IBB=0.000010

0.700

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Assignment 4: Open Loop gain

D. Open Loop gain

After optimizing the noise and distortion of the amplifier, the amplifier is required to be

optimized for bandwidth. LP(loop –poles product) is a relatively simple measure of estimating the

bandwidth of the amplifier circuit. The frequency behavior of the amplifier is split into two separate

parts.

Absolute Frequency: It is proportional to the distance between the poles and the origin. It is

dependent on the constituent devices in the circuit and cannot be altered.

Relative frequency: It is proportional to the relative pole positions. The relative frequency

behavior can be altered by adding passive components in the circuit. Amplifier circuits usually

use a relative frequency behavior of Butterworth type as it has a maximum flat magnitude

transfer.

The product of the DC loop gain and the poles is a measure of maximum attainable bandwidth and is

large for accurate amplifiers.

The open loop gain is calculated by opening the circuit at any point (preferably the nullor) in the

circuit. In this assignment, an open loop gain of a BJT differential amplifier is calculated.

For obtaining a negative loop gain, the input stage is implemented as a differential pair.

The open loop gain of the circuit is given by the ratio Vin/Vaux.

Figure 4.1 Small signal parameters of the charge amplifier

To find the open loop gain, the circuit is opened at a nullor of the first transistor of the differential

amplifier.

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Figure 4.2 Small singal parameters with the loop open at the output transistor nullor

4.1 Determine the voltage gain transfer function as a function of frequency.

The voltage gain transfer function is the ratio of 2V

Vin .For simplification of calculations, Vin is

considered to be unity. The transfer function is given by equation

4.2. Determine the positioning of the poles and zeros

Due to pure capacitive feedback nature of the circuit, the DC loop gain of the charge amplifier is zero.

This is because of a zero added at the origin due to the capacitive feedback. It can be compensated by

attaching a resistor in parallel with the capacitance so that the time constant of the feedback network and the input impedance of the nullor implementation are equal. The value of Rf was found from the

expression

1( ) 1f

CsR R M

Cf

Applying Nodal analysis at nodes Vin,V1 ,V2 and Vcom

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3 2(1 / 3 1 / * 1 / ) ( * 1 / ) 0...(1)

( * * * 1 1 1/ ) 2( * 1/ ) ( 1 * 1 1/ 1) 0....(2)

( 1 1/ 1 1/ 2 2 * 1) ( 1 * 1) 1(1/ 2) 0.....(3)

( 1)( *

gm V R Rload s Cl Rf Vin s Cf Rf

Vin s Cf s Cs s Cgs gm Rf V s Cf Rf Vcom gm s Cgs R

Vcom gm R R gm s Cgs Vin gm s Cgs V R

V s 3 1/ 2) ( 2 1/ 2) 0....(4)Cgs R Vcom gm R

The loop gain Vin/Vaux was calculated in mathematica. It is denoted by L(s). The ratio was found to be

The following values of the BJT transistor parameters were used

Cf=1*10^-9

Cs=10*10^-9

Cl=100*10^-9 Cbe1=11.5*10^-12

Cbe3=11.5*10^-12

gm1=0.0496 gm2=0.23709

gm3=0.0496

R3=10.153*10^3 R2=52.85*10^3

Rf=10^6

Rload=10^4

The transconductance parameters gm1, gm2 and gm3 were calculated using the formula Ic

Vt.The output

resistance is found from the formula R1,R2,R3 is found from the equation Va

Ic where Va is the early

voltage found from the model parameters.

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The poles are calculated from the characteristic equation:

The four poles were calculated to be

{{s-3.82755×109} ,p1=-6.09e8 Hz

{s-734994}, p2=-1.16e5 Hz

{s-3621.48}, p3=-576.3764 Hz

{s-49.5064}}, p4=-7.87 Hz

The zeros of the transfer function is found form the equation

The zeros were found to be

{s= -8.6302×109},

{s= -1.34392×108-1.35258×10

8j},

{s= -1.34392×108+1.35258×10

8j},

{s= 1.33981×108-1.33171×10

8j},

{s= 1.33981×108+1.33171×10

8j}

The DC loop gain L(0) is calculated by substituting s=0 in the loop gain transfer function. It was found

to be

The bandwidth of the system is calculated from the eq .

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The bandwidth for the 4 poles was calculated to be 9.93e+005 Hz which is less than the required

bandwidth. This indicates that all the 4 poles are not the dominant poles. To find whether the chosen

poles are dominant or not, the sum of the loop poles (pl1+pl2) should be greater than the sum of the

Butterworth system of poles (ps1 and ps2).

1 2s sp p = -1

2* * 2 *2

BW =-1.41e6 Hz

1 2l lp p = -1.16e5 -576.3764=-1.16e5 Hz

Hence 1 2l lp p > 1 2s sp p

Considering p1, the sum of the loop poles is equal to p1 which is very small compared to the system

poles ( -1.41e6 Hz),so p1 is not a dominant pole.

Similarly considering p4, the bandwidth of the 3 pole system is 1.73e4 Hz which is less than the required

bandwidth. Hence p4 is a non dominant pole.

Using the poles p2 and p3 the maximum bandwidth of the second order system is calculated to be

max( (1 3.12 6)*1.161 5*576.37)B e e = 14.43e6 Hz

As Bmax is greater than the specified bandwidth, frequency compensation can be applied to achieve this

bandwidth. Phantom zero is one of the preferred techniques used in frequency compensation,

4.3 Remove the ideal nullator and determine the open and closed loop function of the feedback

The open loop function of the feedback is determined by the ratio Vin/V2 when the amplifier loop is

opened at the second nullor. The output voltage is given by V2 in the following expression

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Vin is given by loop gain function derived above

The closed loop function of the feedback is given by Vin/V2 where the

Vin is assumed to be unity for simplifying the calculations and V2 is given by

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Assignment 5

E. Closed Loop gain

5.1 Determine the transfer function and the noise figure of the closed loop system

Figure 5.1 The complete feedback amplifier circuit without the nullor

The closed loop transfer function is given by the equation

( )( )

1 ( )t t

L sA s A

L s

Where tA is the asymptotic gain given by Cf, the feedback capacitor and L(s) is the loop gain of the

feedback amplifier.

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The expression for closed loop gain is given by

The open loop transfer function is given by

L

Where α is the open loop transfer function and β is the feedback transfer function and L the loop gain.

1tA so the open loop transfer function is given by * tL A and given be the expression

The noise figure of the feedback loop is simulated in ADS using the s parameters

It can be inferred that that addition of the output stage has not increased the noise figure of the system .In

assignment 2 the minimum noise figure of the differential BJT was observed to be ~14dBm. The

complete circuit has a minimum noise figure of 11dBm. Hence the first stage of the feedback circuit has

been correctly optimized for noise figure.

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Figure 5.2 The noise figure of the feedback cirucit

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Assignment 6

6.1 Check the stability of the system

In this assignment we perform frequency compensation such that the poles of the closed loop system are

in the Butterworth position. Frequency compensation is changing the coefficient of the s terms in the

characteristic polynomial without changing the LP product.

The characteristic polynomial of a Butterworth second order system is given by the equation

Phantom zero is method of frequency compensation which adds a zero to the loop. This zero is not

visible in the transfer function is called a phantom zero. The phantom zero is realized at the input. The

type of component to be used as a phantom load depends on the source impedance.(given in table .) The

phantom zero is not implemented in the feedback as it is not possible for a parallel connection of a

compensation element to increase beyond phantom pole. At the output the load capacitor introduces an

attenuation of high frequency.

Figure 6.1 Small signal model of the amplifier cirucit

The closed loop transer function of ampilifer compensated with a phantom load is given by

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The location of the phantom zero is given by the equation

Where p1= -1.16e5 Hz,

p2= -576.37 Hz and

LP = 2.086e14 Hz

The required phantom zero is located at

n1 = -10.27e6 Hz

The value of the phantom load (the resistor) is calculated from the formula

Rph = 1.5497 ohm

This phantom zero was added to the circuit as shown in Figure

Figure 6.2 Frequency compensation by addition of phantom load Rph

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Figure 6.3 ADS simulation of the complete amplifier cuircuit with phantom load

The stability of the system is measured by the Rollette’s stability criterion, which is given by

For K>1 the circuit is unconditionally stable and K<1 the circuit is unconditionally stable.

From the stability curve Fig 6.3 it can be observed that the feedback circuit is unstable until the 590 KHz

and then conditionally stable till the 1.5 MHz.

From the Fig 6.4, it is inferred that the output signal is constant at 0.5 volts throughout the frequency

range of the input signal.

From Fig 6.5 , the signal to noise ratio is observed to be 115 dBm which is larger than the required SNR

of 70 dBm. Hence the feedback circuit meets the required specifications.

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Figure 6.4 Variation of Stability factor with frequency

Figure 6.5 Plot of output voltage Vs frequency.

Figure 6.6 Variation of SNR with frequency

Structured Electronics Assignment

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