STRJ-WG1 April 21,2001 - 1 Proposed Roadmap Tables on SOC Low Power STRJ-WG1 June 2001 This is an...

April 21,2001 - 1 STRJ-WG1

Proposed Roadmap Proposed Roadmap Tables onTables on

SOC Low PowerSOC Low Power

STRJ-WG1June 2001

This is an updated version of SoC Low PowerRoadmap from STRJ-WG1 developed in 1999


SOC Low PowerSOC Low Power

Premises & ProspectsTechnology Node, ASIC Usable Transistors, DRAM capacity, andPower Supply Voltage conform to ITRS2000 update SC2.0. Application is not specified, but surely it is high-end SOC in each generation.

Other premises or prospects are consistent with those of “SOC Design Productivity”, such as ;

Die size remains around 10mm

Operation frequency goes up from 150MHz(1999) to 2500MHz(2014) .

Logic gate count ratio continuously decreases.

Low 　 Power


SOC Low PowerSOC Low Power (cont.)

AssumptionsPower consumption follows a basic well-known formula, that isPower ∝ C * V * V * f .

“C” can be decomposed into “size factor” and “process factor”.Total transistor count and technology node represents “size factor”and “process factor”, respectively.

“V*V” is considered as “voltage factor”, and it is just internal voltage.Also, “f” is considered as “frequency factor”, and it is just max frequency.

“total power trend” is defined as relative amount of power consumptionfor each year(2001, 2004, 2011 and 2014) comparing each of above four“factor” for 1999 as unit(=1).

Low 　 Power



Assumptions(cont.)

“total power trend” is derived by the following calculation,

“total power trend” = “size factor” x “process factor” x ”voltage factor” x “frequency factor”

Current SOC power consumption is assumed around 3W.

For “size factor”, constant coefficient 0.85 is applied to Memoryportion, while 1.0 to Logic portion.

Low 　 Power



How to derive “Total Power trend” and “Power estimation”

Total Power trend

Power estimation (W)= (Total Power Trend) x 3W

(Ex.) in 2004Total Power trend= 7.71 x 0.50 x 0.36 x 6.67 = 9.25Hence, Power estimation( W )= 9.25 x 3 = 27.75 W

= “size factor” x “process factor” x ”voltage factor” x “frequency factor”

Low 　 Power



Low 　 Power

2002 2005 2008（） 2011 2014Size 50 60 65 70 75Process 10 20 25 30 35Frequency 25 50 55 60 65Voltage 17 22 33 40 43

Reduction ratio

0

20

40

60

80

100

2002 2005 2008（） 2011 2014Technology Node

Redu

ction

ratio Size

ProcessFrequencyVoltage


SOC Low Power TableSOC Low Power Table

Low 　 Power

unit 1999 2001 2004 2011 2014logic tr count Mtr 15.76 19.7 33.99 119.9 197memory tr count Mtr 16 84 226.2 3056.6 6516.0total tr count Mtr 31.76 104 260.2 3176.5 6713.0size factor(logic*1.0+mem*0.85) 1 3.10 → 1.55 7.71 → 3.08 92.58 → 27.77 195.35 → 48.84factor reduction % 0 50 60 70 75technology node nm 180 130 90 40 30process factor 1.00 0.72 → 0.65 0.50 → 0.40 0.22 → 0.16 0.17 → 0.11factor reduction % 0 10 20 30 35max frequency MHｚ 150 400 1000 2000 2500frequency factor 1.00 2.67 → 2.00 6.67 → 3.33 13.33 → 5.33 16.67 → 5.83factor reduction % 0 25 50 60 65internal voltage V 1.5 1.2 → 1.0 0.9 → 0.70 0.50 → 0.30 0.30 → 0.170voltage factor 1 0.64 → 0.44 0.36 → 0.22 0.11 → 0.04 0.04 → 0.01voltage reduction % 0 17 22 40 43total power trend 1 3.82 → 0.90 9.25 → 0.90 30.48 → 0.92 21.71 → 0.40estimation W 3 11.47 → 2.69 27.74 → 2.69 91.43 → 2.76 65.12 → 1.189target W 0.5 0.5 0.5 0.5 0.5Low Power Specswitching activity % 2.68 2.68 2.68 2.68 2.68external voltage V 1.7 5.0～ 1.2 5.0～ 1.2 5.0～ 0.9 5.0～ 0.9 5.0～battery Wh/ kg 120 130～ 140 150～ 200 250～ 250 300～ 300 400～


SOC Low Power DesignSOC Low Power DesignLow 　 Power

- Potential Solution Map -Target profile of low-power SoC and the typical potential solutions

10

100

1000

10000

1 10 100 1000 10000 100000size (M tr)

Max f

req.

(MHz

)

current 0.5W（）2001 0.5W（）2004 0.5W（）2011 0.5W（）2014 0.5W（）

year: currentnode: 0.18

year: 2001node: 0.13



(3-5 clks)

speed

size ( c a pa ci t a nc e )

overall

Ultra-low voltagedata transfer

Data compressionon a chip

Dynamic voltagecontrol

Multi-clocking

Clock gatingMemory bankoptimization

(5-50 clks)Sytem leveloptimization

Low-poweralgorithm(HW&SW)

Asynchronus

Tr/wire sizingFloorplan optimization



Low 　 Power

SOC Low Power DesignSOC Low Power Design

- Potential Solution Map -What this figure means ….

Trade-off line between operation frequency and size(Mtr) is put for eachTechnology node under the condition to accomplish 0.5W power consumption.

A set of potential low power technology is overlaid in accordance with those contribution area and degree of range.

Each potential technology is classified into three types( speed, size, and all ) with respect to main contribution.


Low 　 Power

SOC Low Power DesignSOC Low Power Design

AppendixThe following two pages are LowPower table and solution map developed by STRJ-WG1 in 1999based upon ITRS1999 data


SOC Low Power TableSOC Low Power Table

unit current 2002 2005 2011 logic tr count Mtr 16 27 46.55 121.7 memory tr count Mtr 16 105 319.8 2553.4 total tr count Mtr 32 132 366.4 2675.1size factor(logic*1.0+mem*0.85) 1 3.93 → 1.96 10.76 → 4.30 77.43 → 23.23 factor reduction % 0 50 60 70 technology node nm 180 130 100 50 process factor 1.00 0.72 → 0.65 0.56 → 0.44 0.28 → 0.19 factor reduction % 0 10 20 30 max frequency MHｚ 150 400 1000 2000 frequency factor 1.00 2.67 → 2.00 6.67 → 3.33 13.33 → 5.33 factor reduction % 0 25 50 60 internal voltage V 1.5 1.2 → 1.0 0.9 → 0.6 0.5 → 0.3 voltage factor 1 0.64 → 0.44 0.36 → 0.16 0.11 → 0.04 voltage reduction % 0 17 33 40 total power trend 1 4.84 → 1.13 14.34 → 1.02 31.87 → 0.96 estimation W 3 14.52 → 3.40 43.02 → 3.06 95.60 → 2.89 target W 0.5 0.5 0.5 0.5 Low Power Spec switching activity % 1.8 2.66 → 2.61 2.7 → 2.67 1.85 → 0.96 external voltage V 1.7 5.0～ 1.2 5.0～ 1.2 5.0～ 0.9 5.0～ battery Wh/ kg 120 130～ 140 150～ 200 250～ 400 500～

Low 　 Power

STRJ-WG1 1999 Version


10

100

1000

10000

1 10 100 1000 10000size (M tr)

Max

freq.

(MHz

)

1999 0.5W（）2002 0.5W（）2005 0.5W（）2011 0.5W（）





(3-5 clks)

speed

size(capacitance)

overall

Ultra-low voltagedata transfer

Data compressionon a chip

Dynamic voltagecontrol

Multi-clocking

Clock gatingMemory bankoptimization

(5-50 clks)Sytem leveloptimization

Low-poweralgorithm(HW&SW)

Asynchronus

Tr/wire sizingFloorplan optimization

Low 　 Power

- Potential Solution Map -STRJ-WG1 1999 Version

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