Strain for CMOS performance Improvement -...

IBM Corporation

Strain for CMOS performance Improvement+Victor Chan, +Ken Rim, #Meikei Ieong, +Sam Yang, +Rajeev Malik, ‡Young

Way Teh, #Min Yang, #Qiqing (Christine) Ouyang

+IBM Systems & Technology Group, #IBM Research Division, T. J. Watson Research Center and

‡Chartered Semiconductor Mfg. Ltd

IBM Semiconductor Research and Development Center (SRDC)Hopewell Junction, NY 12533

Fort Collins, Jan 27 Victor Chan, IBM SRDC

� Outline* Introduction: Strain helps carriers to travel faster

* Substrate-induced strain

* Process-induced strain- Contact etch-stop nitride liner (DSL)- Stress Memorization Technique (SMT)- Embedded SiGe in S/D (e-SiGe)

* Stress and Device / Circuit Implication

* Mobility Improvement beyond Stress Engineering- Channel Orientation- Substrate Orientation (eg. HOT, DSB)

* Summary






* Mobility Improvement beyond Stress Engineering- Channel Orientation- Substrate Orientation (eg. HOT)

* Summary


Mechanical Stress: basic

Due to material mismatch of A & Bfrom material composition, element size / volume and thermal expansion rate, A will introduce mechanical stress to B.

Material B (eg. Si)

Material A (tens/comp)

(eg. Nitride)

RelaxSi1-x

Strained Si

B

AA

Stresstransfer

Carrier

B

A

Stresstransfer

Carrier


Mechanical Stress : many ways

B

A

Stresstransfer

Carrier

B

A

CarrierStresstransfer

B

ACarrier

• Many different ways• Stress transfer dependent on

• material A deposition / growth condition (eg. process temp, material)• subsequent steps (eg. annealing, implantation)

gate

source drain

Uniaxial stress: 1-direction biaxial stress: 2-directions

Carrier

gate

source drain

Carrier


Electrons have higher mobility in Strained (biaxial tensile) Si

K. Rim, VLSI Sym 2002

Ec∆6 . . .. ..

. . .. .. . . .. ... . .. ... . ....

. . . .. . .. .. . ... . . .. .. .. .. .. ...

. . .. .. .. . .. .. . .. . ... ..... . ... .

.. . ... ..

. . .. ... . .. .. . . .. ... . .. ... . ...

.

. . . .. . .. .. . ... . . .. .. .. .. .. ...

. . .. .. .. . .. .. . .. . ... ..... . ... .

∆4 ml

∆2mt

Larger curvature� smaller m*

In Strained Si, i) m* (effective mass) is smaller � higher mobilityii) split energy band � less inter-valley scattering � higher mobility *m

qτµ =

∆4 foldvalleys

Biaxial tensile Siin 100 and 010 direction

<001>

<010>

<100>

∆2 fold valley(lowest E)

Unstrained SiConduction Band

<001>

<010>

<100>

6 fold degenerate conduction valleys

Eg

Ec

Ev


In Strained Si, i) m* (effective mass) is smaller � higher mobilityii) split energy band � less carrier scattering � higher mobility

Holes have higher mobility in Strained (biaxial tensile) Si

(Lower E)

HH = heavy holesLH = light holes

Unstrained SiValence Band

E

k

Spin-orbit

LH

HH2 fold degenerate valence band

Eg

Ec

Ev . . .. ... . .. .. . . .. ... . .. ... . ...

.

. . . .. . .. .. . ... . . .. .. .. .. .. ...

. . .. .. .. . .. .. . .. . ... ..... . ... .. . .. ..

. . .. .. . . .. ... . .. ... . ....

. . . .. . .. .. . ... . . .. .. .. .. .. ...

. . .. .. .. . .. .. . .. . ... ..... . ... .

m* is “rated average”of m*(HH) and m*(LH)

strained SiE

k

Spin-orbit

LH

HH

� Out-of-plane (z)

. . .. ... . .. .. . . .. ... . .. ... . ...

.

. . . .. . .. .. . ... . . .. .. .. .. .. ...

. . .. .. .. . .. .. . .. . ... ..... . ... .

.. . ... ..

in-plane (x,y) �

K. Rim, VLSI Sym 2002


Desired uni-axial stress on CMOS performance

TensileCompressiveZSi DepthTensileTensileYTransverseCompressiveTensileXLongitudinal

PMOSNMOS

Transverse

Source Drain

gate

Longitudinal

gate

Z

Source Drain


Longitudinal stress provides different drive current

500

600

700

800

900

1000

A B C D E F

Ion (u

A/u

m) @

100

nA

/um

n(100)

n(110)

300

400

500

600

700

A B C D E F

Ion

(uA

/um

) @ 1

00nA

/um

p(100)

p(110)

nFE

TIo

n (u

A/u

m)

@ Io

ff=1

00nA

/um

pFE

T Io

n (u

A/u

m)

@ Io

ff=1

00nA

/um

500

600

700

800

900

1000

A B C D E F

Ion (u

A/u

m) @

100

nA

/um

n(100)

n(110)

300

400

500

600

700

A B C D E F

Ion

(uA

/um

) @ 1

00nA

/um

p(100)

p(110)

nFE

TIo

n (u

A/u

m)

@ Io

ff=1

00nA

/um

pFE

T Io

n (u

A/u

m)

@ Io

ff=1

00nA

/um

500

600

700

800

900

1000

A B C D E F

Ion (u

A/u

m) @

100

nA

/um

n(100)

n(110)

300

400

500

600

700

A B C D E F

Ion

(uA

/um

) @ 1

00nA

/um

p(100)

p(110)

nFE

TIo

n (u

A/u

m)

@ Io

ff=1

00nA

/um

pFE

T Io

n (u

A/u

m)

@ Io

ff=1

00nA

/um

500

600

700

800

900

1000

A B C D E F

Ion (u

A/u

m) @

100

nA

/um

n(100)

n(110)

300

400

500

600

700

A B C D E F

Ion

(uA

/um

) @ 1

00nA

/um

p(100)

p(110)

nFE

TIo

n (u

A/u

m)

@ Io

ff=1

00nA

/um

pFE

T Io

n (u

A/u

m)

@ Io

ff=1

00nA

/um

500

600

700

800

900

1000

A B C D E F

Ion (u

A/u

m) @

100

nA

/um

n(100)

n(110)

300

400

500

600

700

A B C D E F

Ion

(uA

/um

) @ 1

00nA

/um

p(100)

p(110)

nFE

TIo

n (u

A/u

m)

@ Io

ff=1

00nA

/um

pFE

T Io

n (u

A/u

m)

@ Io

ff=1

00nA

/um

500

600

700

800

900

1000

A B C D E F

Ion (u

A/u

m) @

100

nA

/um

n(100)

n(110)

300

400

500

600

700

A B C D E F

Ion

(uA

/um

) @ 1

00nA

/um

p(100)

p(110)

nFE

TIo

n (u

A/u

m)

@ Io

ff=1

00nA

/um

pFE

T Io

n (u

A/u

m)

@ Io

ff=1

00nA

/um

Neutral TensileCompressive


Technology in this presentation

Tox (nm)

Lpoly (nm)

VCC (V)

IBM 90 / 65nm CMOS technology

1.2

45

1.0







* Summary


Strain in Si-based Heterostructures

RelaxedSi1-xGex

Strained Si

Si

Pseudomorphically Grown Epitaxial Layers

Cubic Lattice at EquilibriumSi1-xGexGe

aaSi

= 1.042 1+0.042 x 1.0 0.802

StrainedSi1-xGex

Unstrained Si

Tensile-StrainedSi on Si1-xGex

Compressively StrainedSi1-xGex on Si

β-SiC

Tensile-StrainedSi on Si1-xGex

Compressive-StrainedSi1-xGex on Si

Ge Si1-xGex Si ββββ-SiC

Cubic Lattice at Equilibrium

a / aSi = 1.042 1 + 0.042x 1.0 0.082

Pseudomorphically Grown Epitaxial Layers

RelaxedSi1-xGex

UnstrainedSi

Si StrainedSi1-xGex

Strained


Schematic diagram to show three ways of formation of strained Si MOS devices

a) Strained Si/SiGeon bulk wafer

b) SiGe-on-Insulator (SGOI) c) Strained-Si Directly On Insulator (SSDOI) MOSFET

SiGe

Si substrate

Strained Si

SiGe

Si substrate

Buried oxide

Strained Si

Si substrate

Buried oxide

Strained Si

K. Rim, VLSI 2002, B. H. Lee IEDM 2002,

K. Rim IEDM 2003


NMOS shows benefits with biaxial tensile strained Si with 13% & 28% Ge

K. Rim, VLSI Sym, 2002

1000

0.0 500.0k 1.0M 1.5M0

200

400

600

800

1000

110%

Control Universal Mobility

Str. Si / Relx. SiGe 28% Str. Si / Relx. SiGe 13% Str. Si / Str. SiGe 30% / Relx. SiGe 13%

Effe

ctiv

e E

lect

ron

Mob

ility

(cm

/V*s

ec)

Effective Field, Eeff

(V/cm)Effective Field (Eeff (MV/um))0.50

600

800

1000

400

200

0E

ffec

tive

e-M

obili

ty (c

m/V

-sec

)

1.0 1.5400.0µ 600.0µ 800.0µ

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

I off (A

/µm

)

Ion

(A/µm)

Str. Si/SiGe (13% [Ge]) Control

Strain Si / SiGe (13% Ge) Control

1

10

100

1000

0.1

0.01

Ioff

(nA

/um

)

nFET

110%controlUniversal Mobility

Str. Si / Relax SiGe 28%Str. Si / Relax SiGe 13%Str. Si / Str SiGe 30% / Relax SiGe 13%

Ion (uA/um)400 600 800

1000

0.0 500.0k 1.0M 1.5M0

200

400

600

800

1000

110%

Control Universal Mobility

Str. Si / Relx. SiGe 28% Str. Si / Relx. SiGe 13% Str. Si / Str. SiGe 30% / Relx. SiGe 13%

Effe

ctiv

e E

lect

ron

Mob

ility

(cm

/V*s

ec)

Effective Field, Eeff

(V/cm)Effective Field (Eeff (MV/um))0.50

600

800

1000

400

200

0E

ffec

tive

e-M

obili

ty (c

m/V

-sec

)

1.0 1.5400.0µ 600.0µ 800.0µ

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

I off (A

/µm

)

Ion

(A/µm)

Str. Si/SiGe (13% [Ge]) Control


1

10

100

1000

0.1

0.01

Ioff

(nA

/um

)

nFET

110%controlUniversal Mobility

Str. Si / Relax SiGe 28%Str. Si / Relax SiGe 13%Str. Si / Str SiGe 30% / Relax SiGe 13%

Ion (uA/um)400 600 800

• Higher NMOS Ion improvement with higher % Ge.

NMOS


PMOS shows benefits with Biaxial TensileStrained Si with 28% Ge


• pMOS Ion only improved with high % Ge in SiGe, eg. > 20%.

200.0µ 400.0µ 600.0µ1E-10

1E-9

1E-8

1E-7

1E-6

I of

f (A/µ

m)

Ion

(A/µm)

Str. Si/SiGe (28% [Ge]) ControlStrain Si / SiGe (28% Ge) Control


Ion (uA/um)200 400 600

1

10

100

0.1

pFET1000

Ioff

(nA

/um

)

200.0µ 400.0µ 600.0µ1E-10

1E-9

1E-8

1E-7

1E-6

I of

f (A/µ

m)

Ion

(A/µm)

Str. Si/SiGe (28% [Ge]) ControlStrain Si / SiGe (28% Ge) Control


Ion (uA/um)200 400 600

1

10

100

0.1

pFET1000

Ioff

(nA

/um

)

PMOS


% Ge vs mobility


0 10 20 30 40 50

1.0

1.5

2.0

2.50.0 0.5 1.0 1.5 2.0

Ninv

= 1e13 cm-2

Chan.Dop.= 2e17 cm-3

Equivalent [Ge] in Fully Relaxed SiGe (%)

Mob

ility

Enh

ance

men

t Fac

tor

Strain = (aStr.Si

-aSi)/a

Si (%)

��

��

0 10 20 30 40 50

1.0

1.5

2.0

2.50.0 0.5 1.0 1.5 2.0

Ninv

= 1e13 cm-2



Mob

ility

Enh

ance

men

t Fac

tor

Strain = (aStr.Si

-aSi)/a

Si (%)

0 10 20 30 40 50

1.0

1.5

2.0

2.50.0 0.5 1.0 1.5 2.0

Ninv

= 1e13 cm-2



Mob

ility

Enh

ance

men

t Fac

tor

Strain = (aStr.Si

-aSi)/a

Si (%)

��

��

Dependent on %GeGoodBiaxial tensile stress

BadGoodUniaxial longitudinal tensile stress

pMOS (h+)nMOS (e-)

bad

good







* Summary


Ion enhancement using stress liner compared to neutral liner (non-stressed process) for nMOS

H. S. Yang, IEDM 2004

Tensile Nit

N

Un-stress

tensile

a) NMOS

700 900 1100 130010-8

10-7

10-6

10-5

10-4

Ioff

(A/ µµ µµ

m)

Ion (µµµµA/µµµµm)

Un-stress

tensile

a) NMOS

700 900 1100 130010-8

10-7

10-6

10-5

10-4

10-8

10-7

10-6

10-5

10-4

Ioff

(A/ µµ µµ

m)


• nMOS Ion improves with higher Tensile nitride liner


Ion enhancement using stress liner compared to neutral liner (non-stressed process) for pMOS

350 450 55010-9

10-8

10-7

10-6

10-5

Un-stressCompressive


b) PMOS

Ioff

(A/ µµ µµ

m)

350 450 55010-9

10-8

10-7

10-6

10-5

10-9

10-8

10-7

10-6

10-5

Un-stressCompressive


b) PMOS

Ioff

(A/ µµ µµ

m)


Comp Nit

P

• pMOS Ion improves with higher Compressive nitride liner


SEM cross-section of an SRAM cell features tensile and compressive liner in NMOS and PMOS respectively

N P

Buried oxide

N P

Buried oxide

N P

Buried oxide

tensile Compr

N P

Tensile nit Compr nit

Contact

ST


• IBM powerPC TM micro-processor Fmax vs power improves 7 % with DSL due to higher current.


Nitride film stress changes after annealing

nit stress vs anneal temp

Neutral

Tensile

Compressive

Afte

r nitr

ide

Line

r dep

ositi

on

After 400-700C temperature annealing

Tensile liner A

Compressive liner B

• Nit film stress tends to be tensile after annealing

• Annealing temperature will affect hot-carrier reliability

K. Lim, EESDERC, 2005

annealing

Performance Reliability


Nitride film stress will be relaxed after Ge implant

N P

Buried oxide

N P

Buried oxide

N P

Buried oxide

Tensile nit Compr nit

Contact

ST

Tensile Nit + Ge

After 400-600C annealing

Neutral

Tensile

Compressive

Tensile liner A

Compressive liner B

After nitride

Liner deposition After Ge

implantation

• Ge implantationdestroys and relaxes nit film

• Nit film stresstends to betensile after annealing








* Summary


Integration process of SMTAmorphous layer

by implant

After anneal & Nit Removal

Si is crystallized and stress is memorized

• Stress will be transferred from the nitride film to thechannel during annealing.


SMT vs DSLSMT contact end-stop liner

Sensitive to Nitride material yes yes(stress, thickness)

Require Annealing yes No(dependent on annealing temperatureand ramp rate)

Sensitive to a-Si layer yes some(from extension & S/D implant,dependent on implant species, dose, energy)

Sensitive to transistor profile yes yes(eg. gate height, spacer shape and material)


SMT annealingPurpose of annealing: i) Tensile transfer from nitride to Si channel through

amorphorization layer in S/D, extension and poly gate.ii) a-Si crystallization

STI STI

1

2

3

from a-Si to c-Si layerafter anneal


NMOS: 15% current improvement with Disposable Tensile Stressor

0 . 0 0 6 0 . 0 0 7 0 . 0 0 8 0 .0 0 9 0 .0 1 0 . 0 1 1 0 . 0 1 2 0 .0 1 3 0 .0 1 4a b s ( M 1 FN 1 0 x p 1 0 ,0 .0 8 , 0 .0 7 M 1 Io n )

1 e -0 8

1 e -0 7

1 e -0 6

1 e -0 5

100

1000

10

600 700 800 900 1000 1100 1200 1300 14001

nFET Ion (uA/um)

nFE

TIo

ff(n

A/u

m)

0 . 0 0 6 0 . 0 0 7 0 . 0 0 8 0 .0 0 9 0 .0 1 0 . 0 1 1 0 . 0 1 2 0 .0 1 3 0 .0 1 4a b s ( M 1 FN 1 0 x p 1 0 ,0 .0 8 , 0 .0 7 M 1 Io n )

1 e -0 8

1 e -0 7

1 e -0 6

1 e -0 5

100

1000

10

600 700 800 900 1000 1100 1200 1300 14001

nFET Ion (uA/um)

nFE

TIo

ff(n

A/u

m)

Tensile contact etch-stop liner is used.

Control

Tensile Nit stressor


SMT benefit with different types of Nitiride stressor• Stress properties of nitride material is changed after annealing

0 5 10 15 20OP Nit stress

POR

OP_Comp

OP_Nutural

BTBASNovAMAT

% n

MO

SIo

n at

targ

et Io

ff

100%

115%

105%

110%

Compr nit

No SMT

~ Neutral nit

Tens nit

Relative Nitride liner stress






* Mobility Improvement beyond Stress Engineering- Channel Orientation

- Substrate Orientation (eg. HOT)

* Summary


PMOS

Si Substrate

PMOS with e-SiGe structure in S/D

C. Ouyang,VLSI Sym, 2005

• Uniaxial stress in Si channel induced by SiGe S/D• higher hole mobility to enhance drive current

PMOS

Si Substrate

SiGeSiGe

PMOSNit liner

SiGeSiGePMOS

SiGeSiGe

PMOS

Uniaxial compressive strain

nit


SEM photo and SiGe grow rate

SiGe

pMOS

pMOS

C. Ouyang,VLSI Sym, 2005

• SiGe epi growth rate in S/D is dependent on pattern density

blanket patterned

0

2

1

Gro

wth

Rat

e (A

ngst

rom

/sec

)

Base on (100) wfr and 15% Ge

Strained Si

Strained Si


PMOS Ion-Ioff for e-SiGe

From iedm 05, ibm, Luo

eSiGeNo-eSiGe

eSiGe+Compr nit liner







* Summary


Ion_N / Ion_P ratio in the Recent Technology Nodes

1.4

1.6

1.8

2.0

2.2

2.4

2.6

20 30 40 50 60 70 80 90 100 110 120 130 140technology node (nm)

IonN

/ Io

nP ra

tio

Neutral N, Neutral P

Tens N, Compr P

Neut N, Compr P

Tens N, Neut P

• Stress engineering � Ion changes � Ion_N / Ion_P (beta) ratio may change


Vt shift due to longitudinal tensile stress

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.01 0.1Lpoly (um)

Vtli

n (V

)

n PORn OPp PORp OP

0.01 0.1 1.0Lgate (um)

Vtli

n(V

)0.3

0.2

0.1

0

-0.1

-0.2

-0.3

-0.4

controlDisposableStressor

Disposable Stressor processWithout pMOS selective RIE

control

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.01 0.1Lpoly (um)

Vtli

n (V

)

n PORn OPp PORp OP

0.01 0.1 1.0Lgate (um)

Vtli

n(V

)0.3

0.2

0.1

0

-0.1

-0.2

-0.3

-0.4



control

TensileUn-stress

Un-stress

Tensile

Lpoly (um)

Vtli

n(V

)

0.01 0.1

0.3

0.2

0.1

0

-0.1

-0.2

-0.3

-0.4-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.01 0.1Lpoly (um)

Vtli

n (V

)

n PORn OPp PORp OP

0.01 0.1 1.0Lgate (um)

Vtli

n(V

)0.3

0.2

0.1

0

-0.1

-0.2

-0.3

-0.4



control

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.01 0.1Lpoly (um)

Vtli

n (V

)

n PORn OPp PORp OP

0.01 0.1 1.0Lgate (um)

Vtli

n(V

)0.3

0.2

0.1

0

-0.1

-0.2

-0.3

-0.4



control

TensileUn-stress

Un-stress

Tensile

Lpoly (um)

Vtli

n(V

)

0.01 0.1

0.3

0.2

0.1

0

-0.1

-0.2

-0.3

-0.4

• Channel Stress can change the energy band gap of Si channel


X-direction: more compressiveIonN decreases, IonP increases

active size

nMOS Ion

active size

pMOS Ion

X

Different Active Sizes (along channel)• STI provides longitudinal stress and affect N/P Ion.

V. Chan, IEDM 2003

% Ion change from Rx=1.2 to 0.24um

-14

-12

-10

-8

-6

-4

-2

0

0.01 0.1 1 10L (um)

%Io

n

all W=10um

% Io n ch an g e fro m R x=1 .2 to 0 .24u m

0

5

10

15

20

25

0 .01 0 .1 1 10L (u m )

%Io

n

a ll W =10um

pMOS

0.01 0.1 1 10L_Design (µµµµm)

0.01 0.1 1 10L_Design (µµµµm)

20

15

10

5

0%

Ion

nMOS

0

% Io

n

-4

-8

-12

Ion changes from large to small active size

All W=10um

All W=10um



-15

-10

-5

0

5

10

15

20

25

0 0.2 0.4 0.6 0.8 1 1.2 1.4active size (symmetric) (um)

driv

e cu

rren

t cha

nge

(%)

n-10x0.045n-10x0.24n-10x10p-10x0.045p-10x0.24p-10x10

PFET

NFET

active size

∆∆ ∆∆D

rive

cur

rent

(%)

active size

10

Lgate (µµµµm)0.24

0.045

active size (symmetric) (µµµµm)

nMOS

pMOS

0.0450.24

10

STI Stress Proximity Effect (Different Device Lengths)

V. Chan, IEDM 2003


Different Active Sizes with different widths(bi-axial effect)

Z-direction: more compressiveIonN decreases, IonP decreases

X

Z

Z

V. Chan, IEDM, 2003

• STI provides both longitudinal and lateral stress and affect N/P Ion.


-10

-8

-6

-4

-2

0

2

4

0.1 1 10W (um)

%Io

n

all L=0.08um

nMOS

All L=45nm


0

5

10

15

20

25

0.1 1 10W (um)

%Io

nall L=0.08um

pMOS

All L=45nm

20

15

10

5

0

% Io

n


0.1 1 10Width (µµµµm)

width (µµµµm)

4

0

-4

-8

0.1 1 10

% Io

n



-10

-5

0

5

10

15

20

25

0 0.2 0.4 0.6 0.8 1 1.2 1.4active size (symmetric) (um)

driv

e cu

rren

t ch

ang

e (%

)n-10x0.045n-0.24x0.045n-0.12x0.045p-10x0.045p-0.24x0.045p-0.12x0.045

PFET

NFET

active size

∆∆ ∆∆D

rive

cur

rent

(%)

active size (symmetric) (µµµµm)

active sizepMOS

nMOS

0.12W(µµµµm)

0.24

10

10

0.12,0.24

STI Stress Proximity Effect (Different Device Widths)

V. Chan, IEDM, 2003


Technology development & Stress Engineering (1)[Stress engineering is developed early]

Time

Base Line Development Pre-manufacturing

Stress Engineering Discovery Circuit Design

Develop Strained Si

Fabrication Process

Circuit adjustment

Modify Device model after mobility enhancement; include STI stress proximity model

Mask tape-out(additional mask may be required)


Technology development & Stress Engineering (2)[Stress engineering is developed a little bit late]

Time

Base Line Development Pre-manufacturing

Stress Engineering Discovery Circuit Design

Develop Strained SiFabrication Process(late development)

Circuit adjustment

Modify Device model after mobility enhancement; include STI stress proximity model

Mask tape-out(additional mask may be Required. logic vs array)

Not enough

Time

Not Enough

Time


Technology development & Stress Engineering (3)[Device adjustment]

Time

Stress engineering will change the devices:

1) Ion

2) Vt and Ioff

The change will be also dependent on

i) Active area dimension (longitudinal and lateral)

ii) Device length and width

Pre-manufacturing

a) Device re-centering

b) Additional mask* different circuit region (eg. SRAM array)

may have different device centering conditions

c) SRAM stability & yield consideration* Device centering to provide good read

stability and writibility margin


Technology development & Stress Engineering (4)[Other consideration]

i) Extra fabrication process.

It may involve :

a) substrate preparation;

b) nitride deposition � process temperature, thickness, stress level, conformity

c) extra annealing � this may affect dopant activation /

deactivation and device reliability (eg hot carrier);

d) lithography;

e) dry etch / wet etch;

f) implantation.

ii) Ground rule consideration, especially in the SRAM cell.

iii) Critical path and circuit performance.

iv) Stress Monitoring by electrical device data and in-line stress monitoring procedure.

v) Fabrication process: cycle time, repeatability, uniformity, cost and yield.







* Summary


0 vs 45 deg notch

0o notch

< 011> channel

<011> channel

X (100)

Y (010)

Z (001)

X (100)

Y (010)

Z (001)

45o notch

<010> channel

<001> channel


<110> (0deg notch) pMOS mobility is very sensitive to longitudinal stress

0.002 0.0025 0.003 0 .0035 0 .004 0 .0 045 0 .005 0 .0 055 0 .006

M 1 FP10x_07,0.08,0 .10 M 1 Io n

compressive

Neutral

tensile

10-7

10-8

10-9

10-6

200 300 400 500 600

pMO

SIo

ff(A

/um

)

pMOS Ion (uA/um)

sensitive


<100> (45deg notch) pMOS mobility is insensitive to longitudinal stress

0.002 0.0025 0.003 0.0035 0.004 0.0045 0.005 0.0055 0.006

1e-08

1e-07

1e-06

1e-05

compressive

Neutraltensile

10-7

10-8

10-9

10-6

200 300 400 500 600

pMO

SIo

ff(A

/um

)

pMOS Ion (uA/um)

insensitive


Both <110> (0 deg) and <100> (45deg notch) nMOS mobilities are very sensitive to longitudinal stress

0.003 0 .0 04 0.005 0.006 0.007 0.008 0.009 0.01 0.011

1e-08

1e-07

1e-06

1e-05

10-7

10-8

10-9

10-6

300 400 500 600 700 800 900 1000 1100

nMO

SIo

ff(A

/um

)

nMOS Ion (uA/um)

Solid = <110> channelOpen = <100> channelcompressive

Neutraltensile

0deg45deg

Tensile

0.006 0.0065 0.007 0.0075 0 .0 08 0.0085 0.009 0 .0 09 5

1e-07

1e-06

Ion (nMOS)

Ioff

(nM

OS

)


<100> pMOS is not sensitive to STI proximity stress

0.0003 0.00035 0.0004 0.00045 0.0005 0.00055

<100> p-channel

Large Rx overhangSmall Rx overhang

10-8

10-9

10-7

pMO

SIo

ff(A

/um

)

300 350 400 450 500 550pMOS Ion (uA/um)

0.0003 0.00035 0.0004 0.00045 0.0005 0.00055pFET Ion/W

1e-08

1e-07

1e-06

pF

ET

Ioff/W

Large Rx overhang

Small Rx overhang

<110> p-channel

300 350 400 450 500 550pMOS Ion (uA/um)

10-9

10-7

10-8

pMO

SIo

ff(A

/um

)






* Mobility Improvement beyond Stress Engineering- Channel Orientation- Substrate Orientation (eg. HOT, DSB)

* Summary


(100) and (110) wafers

(100) plane

<011> channel

(110) plane

<110> channel

Note: <110> and <001> channel in (110) substrate have different mobility enhancement.


Carrier Mobility Dependence on Surface Orientation

Electron mobility is highest on (100) surface

Hole mobility is highest on (110) surface

Holes Electrons

� Combine the (100) and (110) surfaces to obtain the highest mobility for electrons and holesM. Yang, IEDM 2003, M. Yang, VLSI 2004


CMOS fabrication on Substrates with Hybrid Orientation (1)

M. Yang, IEDM 2003, M. Yang, VLSI 2004


CMOS fabrication on Substrates with Hybrid Orientation (2)



CMOS Structure Using HOT

pMOS on(110) SOI

nMOS on(100) epi-Si

nMOS on(100) SOI

pMOS on(110) epi-Si

Type BType A

in (100) Siin (110) Silayer transfer @ bonding

grow (110) Sigrow (100) SiSelective Epitaxy

Type BType AKey Process Step



Carrier Mobility Dependence on Surface Orientation

• pMOS on (110) surface and nMOS on (100) surface

• Forming hybrid substrate using wafer bonding and Si epitaxy – One additional litho level

• Planar structure, fully compatible with standard CMOS processes

PMOS NMOS



Performance of CMOS on Bulk Silicon Substrates

-50%+26%Ioff = 10nA/um

-35%+20%Ioff = 100uA/um

NMOS ∆∆∆∆ IonPMOS ∆∆∆∆ Ion

0.0032 0.0036 0.004 0.0044 0.0048 0.0052 0.0056 0.006 0.0064 0.00681e-09

1e-08

1e-07

1e-06

1e-05

M1 F

P10x_08 M

1 Ioff

100

1000

10

1

0.1360 400 440 480 520 560 600 640 680

pFET Ion (uA/um)

(100) (110)

pFE

T Io

ff (n

A/u

m)

0.0032 0.0036 0.004 0.0044 0.0048 0.0052 0.0056 0.006 0.0064 0.00681e-09

1e-08

1e-07

1e-06

1e-05

M1 F

P10x_08 M

1 Ioff

100

1000

10

1

0.1360 400 440 480 520 560 600 640 680

pFET Ion (uA/um)

(100) (110)

pFE

T Io

ff (n

A/u

m)

PMOS

Vdd=1VCompr contact nit liner

No degradation ofIon by epi-(110).

pMO

SIo

ff(n

A/u

m)


NMOS

0 500 1000 150010-9

10-8

10-7

10-6

10-5

10-4

nMOS Ion (uA/um)nM

OS

Ioff

(A/u

m)

Tensile contact nit liner

(100)(110)


HOT NMOS has same Ion as conventional bulk NMOS and bulk SOI.

NMOS Ion (uA/um)

NM

OS

Ioff

(A/u

m)

400 600 800 1000 1200

Vdd=1V

HOT nMOS (on BOX)

Conventional Bulk NMOS

Conventional SOI nMOS

10-4

10-5

10-6

10-7

10-8



Carrier mobilities in (100) and (110) substrates are both sensitive to longitudinal stress in channel.

70

80

90

100

110

120

130

A B C D E F

Ion

chan

ge (%

)

n(100)

p(100)

70

80

90

100

110

120

A B C D E F

Ion

chan

ge (%

)

n(110)

p(110)

Neutral TensileCompressive


PMOS on (110) substrate performance is further enhanced by stress engineering

Ion = 710uA/um @ Ioff=100nA/um


Mobility Enhancement is dependent on device orientation

350 400 450 500 550 600 650PMOS Ion (uA/um)

PM

OS

Ioff

(nA

/um

)

1000(100), X,Y

(110)-X

(110)-Y

(110)-X (compres)

(110)-Y (compressive)

Solid symbol = X = [110] direction

Open symbol = Y = [001] directionX

Y

C. D. Sheraw,VLSI 2005


Ring Oscillator Delay is improved by higher PMOS Ion with HOT process

10-3

10-4

10-5

6 7 8 9 10

Qua

si S

tand

by C

urre

nt (A

)

Delay (ps/stage)

(110) bulkNeutral liner

(100) SOITens liner

B

(110) bulkComp liner

(100) SOITens liner

C

(100) SOINeutral liner

(100) SOITens liner

A

PMOSNMOS

A n/p=(100)

B (HOT)

C(HOT+DSL)

C. D. Sheraw,VLSI 2005


DSB – Direct silicon Bonding

(110)

Handle wafer Si (100)

(110)


(110)


(100)

Step 1: (110)/(100) DSB Step 2: selective implant Step 3: SPE & CMOS

a-SiSTI

STI

STI

STI

HOT(p=bulk, n = SOI)

DSB(n/p = bulk)

(110)

(100)

Ox free interface

SPE=solidd phase epitaxy

PN N


pFET performance comparison

� pFETs on DSB shows 35% enhancement compared to (100)

pFET

� Ring oscillator speed is improved by higher pFET Ion in DSB.

Ring

DSB=direct silicon bondingSPE=soild phase epitaxy


(100) vs (110) substrates: vector notation

<001> channel(bad)

Z (001)Y (010)X (100)

(110) substrate

(100) substrate

< 011> channel

<011> channel

Y (010)

Z (001)X

<110> channel(good)

• don’t be confused by <110> channel in (100) Substrate and (110) substrate


(100) plane

channel, 0 deg notch(100) plane

channel, 45 deg notch

0o45o

90o

0o45o

90o

Z,001

X,100

Y,010

<110>

<100>

0 deg vs 45 deg on (100) wafer: vector notation







* Summary


Summary

No further improvement in PMOS currentoChannel Orientation (<100>, 45deg)

Extra Cost on hybrid substrate, extra steps eg. Epi to prepare isolation

oSubstrate Orientation (HOT, DSB)

High process complexity, difficulty in epi-growth, yield

oe-SiGe

Extra steps in integrationoSMT

Extra steps in integration, ground rule consideration

Contact etch-stop liner (DSL)

Extra cost on substrate, difficulty in substrate preparation, integration, & device design.

Biaxial Tensile Strain

Disadvantage & limitationPMOSNMOS


Acknowledgement

IBM SRDC System and Technology Group,

IBM Yorktown Research,

ICIS alliance (IBM, Chartered, Infineon, Samsung),

ASTA alliance (IBM, AMD, Sony, Toshiba)

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