Steven M. Cummins (831) 239-6807

kd5edh@gmail.com Santa Clara, CA www.linkedin.com/in/steve-cummins

TEST ENGINEER

Semiconductor Test Engineer with excellent communication and teamwork skills. Over 25 years experience developing test programs and hardware for the following devices:

Mixed-signal: USB and PSoC (Programmable System on a Chip.) Memories: Low and high power SRAMs, nvSRAM, and MRAM. Logic: PLDs and low-power X86 processors. Sensors: Optical finger navigation and CMOS camera.

TECHNICAL PROFICIENCIES

Languages: C, C++, Perl, Python, Assembly, Unix, Linux, SPICE, Verilog, Eagle. Testers: Nextest, Versatest, Teradyne J973, Credence LT, HP83K, HP82K. Lab: Oscilloscopes, BERT, Logic Analyzer, Curve Tracer, Micro/Pico Probing, Laser.

PROFESSIONAL EXPERIENCE

Principal Test Engineer, Cypress Semiconductor, San Jose, CA. 2014 - Present Non-Volatile SRAM Lead TE, successfully prepared, presented, and passed project reviews and released hardware and test programs to production on schedule.

Developed 64-site vertical probe-card and new PIB (Prober Interface Board) to halve test time and enable at-speed testing at sort.

Developed engineering and production class-test hardware for multiple packages.

Coded and debugged Nextest Magnum Mode-Transition and Power-On-Reset characterization test programs, fulfilling product release requirements.

Principal Test Engineer, Cypress Semiconductor, San Jose, CA. 2013 - 2014

Created entire electrical and thermal HW solution to test high-power SRAM on low-cost tester.

Developed PIB for a high-current using PoLs (Point-of-Load Regulators) to minimize inductance, allowing high di/dt. Used LT SPICE to model parasitics and verified in hardware.

Designed a PSoC project to add clock-stretching to allow using the low cost ATE’s limited I2C interface to control the PoLs.

Test Engineer, Silicon Light Machines, San Jose, CA. 2006 - 2013 Owned testing of Optical Navigation Sensors (Laser and PSoC with photodiode array in a module.)

Wrote and debugged ATE test programs for module and wafer testing.

Developed XY stage on Z table and control SW for tracking and VCSELaser calibrations.

Brought up and supported testing in Korea, China, and the Philippines. Improved package test hardware to drive test yield from 40 to 90%.

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Staff Product Engineer, SMaL Camera, Cambridge, MA. 2006 Supported Automotive Image Sensor production, improving yields and quality.

Analyzed sort and class raw test data to improve tests which increased yields by ~15%.

Worked with customer to implement SPC test limits to improve quality by eliminating outliers.

Staff Test Engineer, Silicon Magnetic Systems, San Jose, CA. 2004 - 2006 Implemented MRAM (Magneto-resistive Random Access Memory) test programs and hardware.

Developed ATE sort and package-level test programs.

Designed high-field electromagnets for immunity testing at sort.

Wrote Perl scripts to process sort data for analysis using SAS JMP. Product Engineer, Transmeta Corporation, Santa Clara, CA. 2001 - 2002

Product engineer responsible for low-power X86 Microprocessors.

Performed system-to-tester Fmax correlation to guarantee speed at production test.

Analyzed electrical qualification failures and directed physical FA.

Wrote Perl scripts to analyze test data.

Edited and debugged Teradyne J973 test programs.

ADDITIONAL EXPERIENCE Staff Test Engineer, Cypress Semiconductor, Austin, TX.

Engineered and executed all HW and SW for USB chip characterization on ATE and bench.

Designed and built printed circuit boards for bench char, using Eagle and Protel.

Characterized USB 1.1 and 2.0 chips using ATE, oscilloscopes and BERT.

Sr. Product/Test Engineer, Cypress Semiconductor, San Jose, CA. Designed test hardware and wrote test programs for PLDs (Programmable Logic Devices.)

Developed ATE test programs, reduced test-time by >30%, and implemented gold/silver unit generation/calibration procedures to improve prime-bin speed yield by >20%.

Designed sort and class test hardware including probe cards, handler kits and interface boards.

Performed FA and yield improvement using liquid crystal, Hypervision, SEM, micro-probing, and electron beam prober.

EDUCATION

Master of Science, Electrical Engineering, Santa Clara University, Santa Clara, CA.

Emphasis: digital circuit design and fab process. Bachelor of Science, Computer Engineering, Oregon State Univ., Corvallis, OR. Emphasis: computer architecture and programming. Bachelor of Arts, Chemistry and Biology, Pomona College, Claremont, CA.