Stellaris LM3S9B96 Development Kit User's Manual (Rev. G) · 2011-08-06 · Block Diagram ......

DK-LM3S9B96-05 Copyright © 2009–2010 Texas Instruments

User ’s Manual

Stellaris® LM3S9B96 Development Kit

2 September 5, 2010

CopyrightCopyright © 2009–2010 Texas Instruments, Inc. All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments. ARM and Thumb are registered trademarks, and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others.

Texas Instruments108 Wild Basin, Suite 350Austin, TX 78746http://www.ti.com/stellaris

Stellaris® LM3S9B96 Development Kit User’s Manual

September 5, 2010 3

Table of ContentsChapter 1: Stellaris® LM3S9B96 Development Board Overview ................................................................. 7Features.............................................................................................................................................................. 7Development Kit Contents ................................................................................................................................ 10Block Diagram .................................................................................................................................................. 11Development Board Specifications................................................................................................................... 11

Chapter 2: Stellaris® LM3S9B96 Development Board Hardware Description .......................................... 13LM3S9B96 Microcontroller Overview ............................................................................................................... 13

Jumpers and GPIO Assignments.................................................................................................................. 13Clocking ........................................................................................................................................................ 14Reset............................................................................................................................................................. 15Power Supplies ............................................................................................................................................. 15USB............................................................................................................................................................... 15Debugging..................................................................................................................................................... 16Color QVGA LCD Touch Panel..................................................................................................................... 17I2S Audio....................................................................................................................................................... 19User Switch and LED.................................................................................................................................... 19

Chapter 3: Stellaris® LM3S9B96 Development Board External Peripheral Interface (EPI) ..................... 21SDRAM Expansion Board ................................................................................................................................ 21Flash and SRAM Memory Expansion Board .................................................................................................... 21FPGA Expansion Board.................................................................................................................................... 21EM2 Expansion Board ...................................................................................................................................... 21

Chapter 4: Using the In-Circuit Debugger Interface .................................................................................... 23Appendix A: Stellaris® LM3S9B96 Development Board Schematics........................................................ 25Appendix B: Stellaris® LM3S9B96 Development Board Component Locations...................................... 33Appendix C: Stellaris® LM3S9B96 Development Board Connection Details ........................................... 35DC Power Jack ................................................................................................................................................. 35ARM Target Pinout ........................................................................................................................................... 35

Appendix D: Stellaris® LM3S9B96 Development Board Microcontroller GPIO Assignments ................ 37Appendix E: Stellaris® LM3S9B96 Flash and SRAM Memory Expansion Board ..................................... 41Features............................................................................................................................................................ 41Installation......................................................................................................................................................... 41Hardware Description ....................................................................................................................................... 43

Functional Description .................................................................................................................................. 43Memory Map..................................................................................................................................................... 45Component Locations....................................................................................................................................... 46Schematics ....................................................................................................................................................... 46

Appendix F: Stellaris® LM3S9B96 FPGA Expansion Board....................................................................... 49Features............................................................................................................................................................ 49Installation......................................................................................................................................................... 50Hardware Description ....................................................................................................................................... 52

FPGA ............................................................................................................................................................ 52Camera ......................................................................................................................................................... 52

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SRAM............................................................................................................................................................ 52Configuration PROM..................................................................................................................................... 52Configuration Pushbutton ............................................................................................................................. 52Test Port ....................................................................................................................................................... 53Camera Connector........................................................................................................................................ 535 V Power Pin ............................................................................................................................................... 5324-MHz Oscillator ......................................................................................................................................... 53External Peripheral Interface (EPI) Module .................................................................................................. 53

Using the Widget Interface ............................................................................................................................... 53Writing Your Own Stellaris Application ......................................................................................................... 53

Memory Map..................................................................................................................................................... 54Register Descriptions.................................................................................................................................... 55

Loading a New Image to the FPGA .................................................................................................................. 61Installing the Software................................................................................................................................... 62Modifying the Default Image ......................................................................................................................... 62Default FPGA Image Blocks ......................................................................................................................... 62

EPI Signal Descriptions .................................................................................................................................... 63Component Locations....................................................................................................................................... 64Schematics ....................................................................................................................................................... 65

Appendix G: Stellaris® LM3S9B96 EM2 Expansion Board......................................................................... 69Features............................................................................................................................................................ 69Installation......................................................................................................................................................... 69Installation of EM Modules onto the EM2 Expansion Board............................................................................. 72Hardware Description ....................................................................................................................................... 74

Primary EM Header ...................................................................................................................................... 74Secondary EM Header.................................................................................................................................. 75CAT24C01 EEPROM.................................................................................................................................... 75I2S Header .................................................................................................................................................... 75Analog Audio Header.................................................................................................................................... 75SDIO Header ................................................................................................................................................ 75

EPI Signal Descriptions .................................................................................................................................... 75Component Locations....................................................................................................................................... 77Schematics ....................................................................................................................................................... 77

Appendix H: References ................................................................................................................................ 79


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List of FiguresFigure 1-1. DK-LM3S9B96 Development Board................................................................................................ 9Figure 1-2. DK-LM3S9B96 Development Board Block Diagram ..................................................................... 11Figure 2-1. Factory Default Jumper Settings ................................................................................................... 14Figure 4-1. ICD Interface Out Mode ................................................................................................................ 23Figure B-1. Component Placement Plot for Top .............................................................................................. 34Figure E-1. Flash and SRAM Memory Expansion Board................................................................................. 41Figure E-2. Removing EPI Board from DK-LM3S9B96 Development Board................................................... 42Figure E-3. Flash/SRAM/LCD IF Expansion Board Block Diagram ................................................................. 43Figure E-4. Component Placement Plot for Top and Bottom........................................................................... 46Figure F-1. FPGA Expansion Board ................................................................................................................ 49Figure F-2. Removing EPI Board from DK-LM3S9B96 Development Board................................................... 51Figure F-3. FPGA Expansion Board Block Diagram........................................................................................ 52Figure F-4. FPGA Boundary Scan ................................................................................................................... 61Figure F-5. Component Placement Plot for Top .............................................................................................. 64Figure F-6. Component Placement Plot for Bottom ......................................................................................... 65Figure G-1. EM2 Expansion Board................................................................................................................... 69Figure G-2. Removing EPI Board from DK-LM3S9B96 Development Board................................................... 70Figure G-3. EM2 Expansion Board................................................................................................................... 71Figure G-4. Assembled DK-LM3S9B96 Development Board with EM2 Expansion Board............................... 71Figure G-5. Connecting an EM Module to the EM2 Expansion Board ............................................................. 72Figure G-6. Fully Assembled DK-LM3S9B96 Board with EM2 Expansion Board and Wireless EM Module ... 73Figure G-7. EM2 Expansion Board Block Diagram .......................................................................................... 74Figure G-8. Component Placement Plot for Top and Bottom........................................................................... 77

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List of TablesTable 2-1. Board Features and Peripherals that are Disconnected in Factory Default Configuration............ 13Table 2-2. USB-Related Signals..................................................................................................................... 15Table 2-3. Hardware Debugging Configurations ............................................................................................ 16Table 2-4. Debug-Related Signals ................................................................................................................. 17Table 2-5. LCD-Related Signals..................................................................................................................... 18Table 2-6. I2S Audio-Related Signals............................................................................................................. 19Table 2-7. Navigation Switch-Related Signals ............................................................................................... 19Table C-1. Debug Interface Pin Assignments ................................................................................................. 35Table D-1. Microcontroller GPIO Assignments ............................................................................................... 37Table E-1. Flash and SRAM Memory Expansion Board Memory Map........................................................... 45Table E-2. LCD Latch Register ....................................................................................................................... 45Table F-1. FPGA Expansion Board Memory Map .......................................................................................... 54Table F-2. Version Register............................................................................................................................ 55Table F-3. System Control Register ............................................................................................................... 56Table F-4. Interrupt Enable Register .............................................................................................................. 57Table F-5. Interrupt Status Register ............................................................................................................... 57Table F-6. Test Pad Register.......................................................................................................................... 58Table F-7. LCD Control Register .................................................................................................................... 59Table F-8. EPI Signal Descriptions ................................................................................................................ 63Table G-1. EPI Signal Descriptions................................................................................................................. 75

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Stellaris® LM3S9B96 Development Board OverviewThe Stellaris® LM3S9B96 Development Board provides a platform for developing systems around the advanced capabilities of the LM3S9B96 ARM® Cortex™-M3-based microcontroller.

The LM3S9B96 is a member of the Stellaris Tempest-class microcontroller family. Tempest-class devices include capabilities such as 80 MHz clock speeds, an External Peripheral Interface (EPI) and Audio I2S interfaces. In addition to new hardware to support these features, the DK-LM3S9B96 board includes a rich set of peripherals found on other Stellaris boards.

The development board includes an on-board in-circuit debug interface (ICDI) that supports both JTAG and SWD debugging. A standard ARM 20-pin debug header supports an array of debugging solutions.

The Stellaris® LM3S9B96 Development Kit accelerates development of Tempest-class microcontrollers. The kit also includes extensive example applications and complete source code.

FeaturesThe Stellaris® LM3S9B96 Development Board includes the following features.

Simple set-up—USB cable provides debugging, communication, and power

Flexible development platform with a wide range of peripherals

Color LCD graphics display

– TFT LCD module with 320 x 240 resolution

– Resistive touch interface

80 MHz LM3S9B96 microcontroller with 256 K Flash, 96 K SRAM, and integrated Ethernet MAC+PHY, USB OTG, and CAN communications

– – 8 MB SDRAM (plug-in EPI option board)

– – EPI break-out board (plug-in option board)

1 MB serial Flash memory

Precision 3.00 V voltage reference

SAFERTOS™ operating system in microcontroller ROM

I2S stereo audio codec

– Line In/Out

– Headphone Out

– Microphone In

Controller Area Network (CAN) Interface

10/100 BaseT Ethernet

USB On-The-Go (OTG) Connector

– Device, Host, and OTG modes

C H A P T E R 1

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User LED and push button

Thumbwheel potentiometer (can be used for menu navigation)

MicroSD card slot

Supports a range of debugging options

– Integrated In-circuit Debug Interface (ICDI)

– JTAG, SWD, and SWO all supported

– Standard ARM® 20-pin JTAG debug connector

USB Virtual COM Port

Jumper shunts to conveniently reallocate I/O resources

Develop using tools supporting Keil™ RealView® Microcontroller Development Kit (MDK-ARM), IAR Embedded Workbench, Code Sourcery GCC development tools, Code Red Technologies development tools, or Texas Instruments’ Code Composer Studio™ IDE

Supported by StellarisWare® software including the graphics library, the USB library, and the peripheral driver library

Optional expansion boards that work with the External Peripheral Interface (EPI) of the DK-LM3S9B96 development board extend the capabilities of this development platform (each board sold separately)

– Stellaris® Flash and SRAM Memory Expansion Board (DK-LM3S9B96-FS8) (sold separately)

• Provides Flash memory, SRAM, and an improved performance LCD interface

For more information on the DK-LM3S9B96-FS8 memory expansion board, see Appendix E, “Stellaris® LM3S9B96 Flash and SRAM Memory Expansion Board,” on page 41.

– Stellaris® FPGA Expansion Board (DK-LM3S9B96-FPGA) (sold separately)

• Provides machine-to-machine (M2M), high-bandwidth, parallel interface capability of the Stellaris microcontroller

• Allows users to control and display the FPGA expansion board’s video on the DK-LM3S9B96 development board’s large, 3.5” touchscreen display

For more information on the DK-LM3S9B96-FPGA expansion board, see Appendix F, “Stellaris® LM3S9B96 FPGA Expansion Board,” on page 49.

– Stellaris® EM2 Expansion Board (DK-LM3S9B96-EM2) (sold separately)

• Provides a transition between the Stellaris External Peripheral Interface (EPI) connector and the RF Evaluation Module (EM) connector

• Enables wireless application development using Low Power RF and RF ID evaluation modules on the Stellaris DK-LM3S9B96 platform

For more information on the DK-LM3S9B96-EM2 expansion board, see Appendix G, “Stellaris® LM3S9B96 EM2 Expansion Board,” on page 69.


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Figure 1-1. DK-LM3S9B96 Development Board

On-board JTAG /SWD Debug Interface

USB Connector for Debug and /or Power

Stellaris LM3S39B96 Microcontroller

CAN Bus Interface

3.5" LCD Touch Panel

USB connector withHost, Device and On-the-Go modes

10/100 Ethernet

User LED

microSD Card Slot

Potentiometer

5 VDC supply input

JTAG/SWD In/Out Connector

User Switch

Reset switch

Power and Ground Test

Points

3.00V Analog Reference

Headphone OutputAudio Line Output

Microphone InputAudio Line Input

1MB Serial Flash Memory

EPI Expansion Board

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Development Kit ContentsThe Stellaris® LM3S9B96 Development Kit contains everything needed to develop and run a range of applications using Stellaris microcontrollers:

LM3S9B96 development board

8 MB SDRAM expansion board

EPI signal breakout board

Retractable Ethernet cable

USB Mini-B cable for debugger use

USB Micro-B cable for OTG-to-PC connection

USB Micro-A to USB A adapter for USB Host

USB Flash memory stick

microSD Card

20-position ribbon cable

CD containing:

– A supported version of one of the following (including a toolchain-specific Quickstart guide):

• Keil™ RealView® Microcontroller Development Kit (MDK-ARM)

• IAR Embedded Workbench

• Code Sourcery GCC development tools

• Code Red Technologies development tools

• Texas Instruments’ Code Composer Studio™ IDE

– Complete documentation

– Quickstart application source code

– Stellaris® Firmware Development Package with example source code


September 5, 2010 11

Block DiagramFigure 1-2. DK-LM3S9B96 Development Board Block Diagram

Development Board SpecificationsBoard supply voltage: 4.75–5.25 Vdc from one of the following sources:

– Debugger (ICDI) USB cable (connected to a PC)

– USB Micro-B cable (connected to a PC)

– DC power jack (2.1 x 5.5mm from external power supply)

Break-out power output: 3.3 Vdc (100 mA max)

USB

USB

USB

T

StellarisTempest-class

LM3S9B96Microcontroller

QVGAColor LCD Module

I/O Signal Break-out

Switch

LED

Tempest LM 3S9B96 Development Board

I/O Signal Break-out

I/O s

igna

ls

DualUSB

DeviceController

Deb

ugJTAG/SWD Output/Input

Debug USB

Reset+3.3V

Regulator

SWD

/JTA

G M

ux

UART0

Debug

USB

Control+5V host supply

USBmicro-AB connector

OTG/Host/Device

Targ

et

Cab

le

MicroSD card slot

1GB

1MBSerial Flash

EPI

Touch

RJ45Jack+

MagneticsEthernet

PotThumbwheel Pot

8MB SDRAM

HeadphoneJack

Line OutJack

I2SAudio

CODEC

Line Output

Phones


Dimensions (excluding LCD panel):

– 4.50” x 4.25” x 0.60” (LxWxH) with SDRAM board

– 4.50” x 4.25” x 0.75” (LxWxH) with EPI breakout board

Analog Reference: 3.0 V +/-0.2%

RoHS status: Compliant

NOTE: When the LM3S9B96 Development Board is used in USB Host mode, the host connector is capable of supplying power to the connected USB device. The available supply current is limited to ~200 mA unless the development board is powered from an external 5 V supply with a =600mA rating.


Stellaris® LM3S9B96 Development Board Hardware Description

In addition to an LM3S9B96 microcontroller, the development board includes a range of useful peripheral features and an integrated in-circuit debug interface (ICDI). This chapter describes how these peripherals operate and interface to the microcontroller

LM3S9B96 Microcontroller OverviewThe Stellaris LM3S9B96 is an ARM Cortex-M3-based microcontroller with 256-KB flash memory, 80-MHz operation, Ethernet, USB, EPI, SAFERTOS™ in ROM, and a wide range of peripherals. See the LM3S9B96 Microcontroller Data Sheet (order number DS-LM3S9B96) for complete microcontroller details.

The LM3S9B96 microcontroller is factory-programmed with a quickstart demo program. The quickstart program resides in on-chip flash memory and runs each time power is applied, unless the quickstart has been replaced with a user program.

Jumpers and GPIO AssignmentsEach peripheral circuit on the development board is interfaced to the LM3S9B96 microcontroller through a 0.1” pitch jumper/shunt. Figure 2-1 on page 14 shows the factory default positions of the jumpers. The jumpers must be in these positions for the quickstart demo program to function correctly.

The development board offers capabilities that the LM3S9B96 cannot support simultaneously due to pin count and GPIO multiplexing limitations. For example, as configured, the board does not support SDRAM and I2S receive (microphone or line input) functions at the same time. The jumpers associated with I2S receive are omitted in the default configuration.

Table 2-1 lists all features and peripherals that are disconnected in the factory default configuration. Using these peripherals requires that other peripherals be disconnected. Appendix D, “Stellaris® LM3S9B96 Development Board Microcontroller GPIO Assignments,” on page 37 lists alternative jumper configurations used in conjunction with some of the StellarisWare™ example applications for this board.

See Appendix D, “Stellaris® LM3S9B96 Development Board Microcontroller GPIO Assignments,” on page 37, for a complete list of GPIO assignments. The table lists all default and alternate

Table 2-1. Board Features and Peripherals that are Disconnected in Factory Default Configuration

Peripheral Jumpers

I2S Receive (Audio Input) JP44, 45, 47, 49

Controller Area Network (CAN) JP14, 15

Ethernet Yellow Status LED (LED2) JP2

Analog 3.0V Reference JP33

C H A P T E R 2


assignments that are supported by the 0.1” jumpers and PCB routing. The LM3S9B96 has additional internal multiplexing that enables additional configurations which may require discrete wiring between peripherals and GPIO pins.

The ICDI section of the board has a GND-GND jumper that serves no function other than to provide a convenient place to ‘park’ a spare jumper. This jumper may be reused as required.

Figure 2-1. Factory Default Jumper Settings

ClockingThe development board uses a 16.0-MHz (Y2) crystal to complete the LM3S9B96 microcontroller's main internal clock circuit. An internal PLL, configured in software, multiples this clock to higher frequencies for core and peripheral timing.

A 25.0-MHz (Y1) crystal provides an accurate timebase for the Ethernet PHY.



ResetThe RESETn signal into the LM3S9B96 microcontroller connects to the reset switch (SW2) and to the ICDI circuit for a debugger-controlled reset.

External reset is asserted (active low) under any one of the three following conditions:

Power-on reset (filtered by an R-C network)

Reset push switch SW2 held down

By the ICDI circuit (U12 FT2232, U13D 74LVC125A) when instructed by the debugger (this capability is optional, and may not be supported by all debuggers)

The LCD module has special Reset timing requirements requiring a dedicated control line from the microcontroller.

Power SuppliesThe development board requires a regulated 5.0 V power source. Jumpers JP34-36 select the power source, with the default source being the ICDI USB connector. Only one +5 V source should be selected at any time to avoid conflict between the power sources.

When using USB in Host mode, the power source should be set to either ICDI or to EXT if a +5 V power supply (not included in the kit) is available.

The development board has two main power rails. A +3.3 V supply powers the microcontroller and most other circuitry. +5 V is used by the OTG USB port and In-circuit Debug Interface (ICDI) USB controller. A low drop-out (LDO) regulator (U5) converts the +5 V power rail to +3.3 V. Both rails are routed to test loops for easy access.

USBThe LM3S9B96’s full-speed USB controller supports On-the-Go, Host, and Device configurations. See Table 2-2 for USB-related signals. The 5-pin microAB OTG connector supports all three interfaces in conjunction with the cables included in the kit.

The USB port has additional ESD protection diode arrays (D1, D2,D5) for up to 15 kV of ESD protection.

U6, a fault-protected switch, controls and monitors power to the USB host port. USB0EPEN, the control signal from the microcontroller, has a pull-down resistor to ensure host-port power remains off during reset. The power switch will immediately cut power if the attached USB device draws

Table 2-2. USB-Related Signals

Microcontroller Pin Board Function Jumper Name

Pin 70 USB0DM USB Data- -

Pin 71 USB0DP USB Data+ -

Pin 73 USB0RBIAS USB bias resistor -

Pin 66 USB0ID OTG ID signal (input to microcontroller) OTG ID

Pin 67 USB0VBUS Vbus Level monitoring +VBUS

Pin 34 USB0EPE Host power enable (active high) EPEN

Pin 35 USB0PFLT Host power fault signal (active low) PFLT


more than 1 Amp, or if the switches’ thermal limits are exceeded by a device drawing more than 500 mA. USB0PFLT indicates the over-current status back to the microcontroller.

The development board can be either a bus-powered USB device or self-powered USB device depending on the power-supply configuration jumpers.

When using the development board in USB-host mode, power to the EVB should be supplied by the In-circuit Debugger (ICDI) USB cable or by a +5 V source connected to the DC power jack.

Note that the LM3S9B96’s USB capabilities are completely independent from the In-Circuit Debug Interface USB functionality.

DebuggingStellaris microcontrollers support programming and debugging using either JTAG or SWD. JTAG uses the TCK, TMS, TDI, and TDO signals. SWD requires fewer signals (SWCLK, SWDIO, and, optionally, SWO for trace). The debugger determines which debug protocol is used.

Debugging ModesThe LM3S9B96 development board supports a range of hardware debugging configurations. Table 2-3 summarizes these configurations.

Debug In ConsiderationsDebug Mode 3 supports board debugging using an external debug interface such as a Segger J-Link or Keil ULINK. Most debuggers use Pin 1 of the Debug connector to sense the target voltage and, in some cases, power the output logic circuit. Installing the VDD/PIN1 jumper will apply 3.3 V power to this pin in order to support external debuggers.

Debug USB OverviewAn FT2232 device from Future Technology Devices International Ltd implements USB-to-serial conversion. The FT2232 is factory-configured to implement a JTAG/SWD port (synchronous serial) on channel A and a Virtual COM Port (VCP) on channel B. This feature allows two simultaneous communications links between the host computer and the target device using a single USB cable. Separate Windows drivers for each function are provided on the Documentation and Software CD.

The In-Circuit Debug Interface USB capabilities are completely independent from the LM3S9B96’s on-chip USB functionality.

Table 2-3. Hardware Debugging Configurations

Mode Debug Function Use Selected by...

1 Internal ICDI Debug on-board LM3S9B96 microcontroller over Debug USB interface.

Default mode

2 ICDI out to JTAG/ SWD header

The development board is used as a USB to SWD/ JTAG interface to an external target.

Remove jumpers on TCk, TMS, TDI, TDO, and PIN1

3 In from JTAG/SWD header For users who prefer an external debug interface (ULINK, JLINK, etc.) with the development board.

Connecting an external debugger to the JTAG/SWD header



A small serial EEPROM holds the FT2232 configuration data. The EEPROM is not accessible by the LM3S9B96 microcontroller. For full details on FT2232 operation, go to www.ftdichip.com.

USB to JTAG/SWD The FT2232 USB device performs JTAG/SWD serial operations under the control of the debugger. A simple logic circuit multiplexes SWD and JTAG functions and, when working in SWD mode, provides direction control for the bidirectional data line.

Virtual COM PortThe Virtual COM Port (VCP) allows Windows applications (such as HyperTerminal) to communicate with UART0 on the LM3S9B96 over USB. Once the FT2232 VCP driver is installed, Windows assigns a COM port number to the VCP channel. Table 2-4 shows the debug-related signals.

Serial Wire Out (SWO)The development board supports the Cortex-M3 Serial-Wire Output (SWO) trace capabilities. Under debugger control, on-board logic can route the SWO datastream to the VCP transmit channel. The debugger software can then decode and interpret the trace information received from the Virtual Com Port. The normal VCP connection to UART0 is interrupted when using SWO. Not all debuggers support SWO.

See the Stellaris LM3S9B96 Microcontroller Data Sheet for additional information on the Trace Port Interface Unit (TPIU).

Color QVGA LCD Touch PanelThe development board features a TFT Liquid Crystal graphics display with 320 x 240 pixel resolution. The display is protected during shipping by a thin, protective plastic film which should be removed before use.

FeaturesFeatures of the LCD module include:

Kitronix K350QVG-V1-F display

320 x RGB x 240 dots

3.5” 262 K colors

Table 2-4. Debug-Related Signals


Pin 77 TDO/SWO JTAG data out or trace data out TDO

Pin 78 TDI JTAG data in TDI

Pin 79 TMS/SWDIO JTAG TMS or SWD data in/out TMS

Pin 80 TCK/SWCLK JTAG Clock or SWD clock TCK

Pin 26 PA0/U0RX Virtual Com port data to LM3S9B96 VCPRX

Pin 27 PA1/U0TX Virtual Com port data from LM3S9B96 VCPTX

Pin 64 RSTn System Reset RSTn


Wide temperature range

White LED backlight

Integrated RAM

Resistive touch panel

Control InterfaceThe Color LCD module has a built-in controller IC with a multi-mode parallel interface. The development board uses an 8-bit 8080 type interface with GPIO Port D providing the data bus. Table 2-4 shows the LCD-related signals.

BacklightThe white LED backlight must be powered for the display to be clearly visible. U7 (FAN5331B) implements a 20 mA constant-current LED power source to the backlight. The backlight is not normally controlled by the microcontroller, however, the control signal is available on a header. A jumper may be installed to disable the backlight by connecting it to GND. Alternatively, a wire may be used to control this signal from a spare microcontroller GPIO line.

Because the FAN5331B operates in a constant current mode, its output voltage will jump up if the LCD should become disconnected. To prevent over-voltage failure of the IC or diode D3, a zener (D4) clamps the voltage. The current will limit to 20 mA, but the total board current will be higher than when the LCD panel is connected. To avoid over-heating the backlighting circuit, install the BLON jumper to completely shut-down the backlighting circuit.

PowerThe LCD module has internal bias voltage generators and requires only a single 3.3 V dc supply.

Resistive Touch PanelThe 4-wire resistive touch panel interfaces directly to the microcontroller, using 2 ADC channels and 2 GPIO signals. See the StellarisWare™ source code for additional information on touch panel implementation.

Table 2-5. LCD-Related Signals


PE6/ADC1 Touch X+ X+

PE3 Touch Y- Y-

PE2 Touch X- X-

PE7/ADC0 Touch Y+ Y+

PB7 LCD Reset LRSTn

PD0..7 LCD Data Bus 0..7 LD0..7

PH7 LCD Data/Control Select LDC

PB5 LCD Read Strobe LRDn

PH6 LCD Write Strobe LWRn

- Backlight control BLON



I2S AudioThe LM3S9B96 development board has advanced audio capabilities using an I2S-connected Audio TLV320AIC23 CODEC. The factory default configuration has Audio output (Line Out and/or Headphone output) enabled. Four additional I2S signals are required for Audio input (Line Input and/or Microphone). All four audio interfaces are through 1/8” (3.5mm) stereo jacks. Table 2-6 shows the I2S audio-related signals.

The Audio CODEC has a number of control registers which are configured using the I2C bus signals. CODEC settings can only be written, but not read, using I2C. See the StellarisWare™ example applications for programming information and the TLV320AIX23B data sheet for complete register details.

The Headphone output can be connected directly to any standard headphones. The Line Output is suitable for connection to an external amplifier, including PC desktop speaker sets.

User Switch and LEDThe development board provides a user push-switch and LED (see Table 2-7).

Table 2-6. I2S Audio-Related Signals


I2C0SDA CODEC Configuration Data SDA

I2C0SCL CODEC Configuration Clock SCL

I2STXSD Audio Out Serial Data TXSD

I2STXWS Audio Out Framing signal TXWS

I2STXSCK Audio Out Bit Clock BCLKa

a. Shares GPIO line with Analog voltage reference. Jumper installed by default.

I2STXMCLK Audio Out System Clock MCLK

I2SRXSD Audio In Serial Data RXSDb

b. Shares GPIO line with LCD data bus – Port D. Jumper omitted by default.

I2SRXWS Audio In Framing signal RXWSb

I2SRXSCK Audio In Bit Clock BCLKb

I2SRXMCLK Audio In System Clock MCLKb

Table 2-7. Navigation Switch-Related Signals


PJ7 User Switch SWITCH

PF3 User LED LEDa

a. Shared with Ethernet Jack Yellow LED. This jumper is installed by default.


Stellaris® LM3S9B96 Development Board External Peripheral Interface (EPI)

The External Peripheral Interface (EPI) is a high-speed 8/16/32-bit parallel bus for connecting external peripherals or memory without glue logic. Supported modes include SDRAM, SRAM, and Flash memories, as well as Host-bus and FIFO modes.

The LM3S9B96 development kit includes an 8 MB SDRAM board in addition to an EPI break-out board. Other EPI expansion boards may be available.

SDRAM Expansion BoardThe SDRAM board provides 8 MB of memory (4M x 16) which, once configured, becomes part of the LM3S9B96’s memory map at either 0x6000.0000 or 0x8000.0000. The SDRAM interface multiplexes DQ00..14 and AD/BA0..14 without requiring external latches or buffers. Of the 32 EPI signals, only 24 are used in SDRAM mode, with the remaining signals used for non-EPI functions on the board.

Flash and SRAM Memory Expansion BoardThe optional Flash and SRAM Memory Expansion Board (DK-LM3S9B96-FS8) is a plug-in for the DK-LM3S9B96 development board. This expansion board works with the External Peripheral Interface (EPI) of the Stellaris microcontroller and provides Flash memory, SRAM, and an improved performance LCD interface.

For more information on the Flash and SRAM Memory Expansion Board (sold separately), see Appendix E, “Stellaris® LM3S9B96 Flash and SRAM Memory Expansion Board,” on page 41.

FPGA Expansion BoardThe FPGA Expansion Board (DK-LM3S9B96-FPGA) is an optional expansion board which connects directly to the External Peripheral Interface (EPI) port of the Stellaris DK-LM3S9B96 development board to demonstrate the machine-to-machine (M2M), high-bandwidth, parallel interface capability of the Stellaris microcontroller. Right out of the box, users are able to control and display the FPGA expansion board’s video on the DK-LM3S9B96 development board’s large, 3.5” touchscreen display.

For more information on the FPGA Expansion Board (sold separately), see Appendix F, “Stellaris® LM3S9B96 FPGA Expansion Board,” on page 49.

EM2 Expansion BoardThe EM2 Expansion Board (DK-LM3S9B96-EM2) is an optional expansion board which connects directly to the External Peripheral Interface (EPI) port of the Stellaris DK-LM3S9B96 development board. The EM2 Expansion Board provides a transition between the Stellaris External Peripheral Interface (EPI) connector and the RF Evaluation Module (EM) connector. The DK-LM3S9B96-EM2 enables wireless application development using Low Power RF and RF ID evaluation modules on the Stellaris DK-LM3S9B96 platform.

For more information on the EM2 Expansion Board (sold separately), see Appendix G, “Stellaris® LM3S9B96 EM2 Expansion Board,” on page 69.

C H A P T E R 3


Using the In-Circuit Debugger InterfaceThe Stellaris® LM3S9B96 Development Kit can operate as an In-Circuit Debugger Interface (ICDI). ICDI acts as a USB to the JTAG/SWD adaptor, allowing debugging of any external target board that uses a Stellaris microcontroller. See “Debugging Modes” on page 16 for a description of how to enter ICDI Out mode.

Figure 4-1. ICD Interface Out Mode

The debug interface operates in either serial-wire debug (SWD) or JTAG mode, depending on the configuration in the debugger IDE.

The IDE/debugger does not distinguish between the on-board Stellaris microcontroller and an external Stellaris microcontroller. The only requirement is that the correct Stellaris device is selected in the project configuration.

The Stellaris target board should have a 2x10 0.1” pin header with signals as indicated in Table C-1 on page 35. This applies to both an external Stellaris microcontroller target (Debug Output mode) and to external JTAG/SWD debuggers (Debug Input mode).

ICDI does not control RST (device reset) or TRST (test reset) signals. Both reset functions are implemented as commands over JTAG/SWD, so these signals are usually not necessary.

LM3S9B96 Dev Board Target Board

Stellaris MCU

USB to

JTAG/SWD

PC with IDE/debugger

Stellaris MCU

JTAG or SWD connects to the external microcontroller

Remove jumpers to use ICDI Out Feature

`

TCK

TMS

TDI

TDO

Target Cable

VDD

+3.3V

C H A P T E R 4


Stellaris® LM3S9B96 Development Board Schematics

This section contains the schematics for the DK-LM3S9B96 development board.

Micro, EPI connector, USB, and Ethernet on page 26

LCD CAN, Serial Memory, and User I/O on page 27

Power Supplies on page 28

I2S Audio Expansion Board on page 29

EPI and SDRAM Expansion Boards on page 30

In-circuit Debug Interface (ICDI) on page 31

A P P E N D I X A

1

1

2

2

3

3

4

4

5

5

6

6

D D

C C

B B

A A

Document Number:

RevSheetDate: of4/23/2009 1 6

Drawing Title:

Page Title:

Size

LM3S9B96 Development Board

Micro, EPI connector, USB and Ethernet

B

A

DB-LM3S9B96

10PF

C1

10PF

C2

PC0/TCKPC1/TMSPC2/TDIPC3/TDO

6

5

8

4

2

3

1

7

1CT:1

TX+

TX-

RX+

RX-1CT:1

Y+

Y-

G+

G-

3

8

7

4

5

6

1112

21

GL

GR

910

NC

GND

J1

J3011G21DNL

R649.9

+3.3V

R449.9

R549.9

R749.9

C18

0.1UF

+3.3V

C19

0.1UF

+3.3V

C1710pF

C1310pF

C1610pF

R8

330

R2

10K

M+3.3V

Stellaris Microcontroller

R9

330

+3.3V

+3.3V

PF2/LED1

1 2Y1

25.00MHz

C1410pF

10PF

C3

10PF

C4 +3.3V

C50.1UF

PJ2/EPI18PJ1/EPI17PJ0/EPI16

PG7/EPI31

PC4/EPI02PC5/EPI03PC6/EPI04PC7/EPI05

PE0/EPI08PE1/EPI09

PH4/EPI10PH5/EPI11

PG0/EPI13

C70.01UF

C90.1UF

C112.2UF

PH0/EPI06PH1/EPI07

PF4/EPI12

PH3/EPI00PH2/EPI01

R3

9.10K

OSC1OSC0

XTALPXTLN

M+3.3V

PB4/ADC10/EPI23PB5/EPI22PA5/SSI0TX

PA4/SSI0RX

PA2/SSI0CLK

Ethernet 10/100baseT

PG1/EPI14

PF5/EPI15

Y2

16.00MHz

123456789

10111213141516171819202122232425 26

272829303132333435363738394041424344454647484950

J2

DF12D-50DP

EPI Expansion Connector

PD2/EPI20PD3/EPI21

PH6/EPI26PH7/EPI27

PE2/EPI24PE3/EPI25

PH4/EPI10PH3/EPI00PH2/EPI01PH1/EPI07PH0/EPI06PJ1/EPI17PB5/EPI22PB4/ADC10/EPI23PE2/EPI24PE3/EPI25PJ3/EPI19PJ4/EPI28PJ5/EPI29PJ6/EPI30PD2/EPI20PD3/EPI21

PH7/EPI27PJ0/EPI16

PG1/EPI14PG0/EPI13 PC4/EPI02

PC5/EPI03PC6/EPI04PC7/EPI05

PH6/EPI26PH5/EPI11PE0/EPI08PE1/EPI09

+3.3V

PG7/EPI31PJ2/EPI18PF5/EPI15PF4/EPI12

+5V

Revision Date Description

History

0 11 Mar 09 Initial Prototype

R1

12.4K

RESETn

PJ3/EPI19PJ4/EPI28PJ5/EPI29PJ6/EPI30

PA3

PA1/U0TXPA0/U0RX

PE4/I2STXWSPE5/I2STXSD

PE6/ADC1PE7/ADC0

PJ7

PB0/USBIDPB1/USBVBUSPB2/I2C0SCLPB3/I2C0SDA

PD0/I2SRXSCK

PD4/I2SRXSD

PD6PD7

PB6/TXSCK/AVREFPB7/NMI

PF0PF1/TXMCLK

LED2

JP2

PF3/LED0

VBUS D- D+ ID G

1 2 3 4

G2

5

G1

J3

USB Micro AB

USB On-the-Go

+VBUS

PB0/USBIDOTG ID

JP4

+VBUS

JP3PB1/USBVBUS

PA0/U0RX26

PA1/U0TX27

PA2/SSI0CLK28

PA3/SSI0FSS29

PA4/SSI0RX30

PA5/SSI0TX31

PC0/TCK/SWCLK80

PC1/TMS/SWDIO79

PC2/TDI78

PC3/TDO/SWO77

PC4/EPI0S0225

PC5/EPI0S0324

PC6/EPI0S0423

PC7/EPI0S0522

PD0 10

PD1 11

PD2/EPI0S20 12

PD3/EPI0S21 13

PE2/EPI0S2495

PE3/EPI0S2596

PD6 99

PD7 100

GND9

PH7/EPI0S27 15

GND21

ERBIAS33

RST_n64

LDO 7

OSC048

OSC149

PB0/USB0ID 66

PB1/USB0VBUS 67

USB0DM 70USB0DP 71

PB4/EPI0S23 92

PB5/EPI0S22 91

PB6/AVREF 90

PB7/NMI 89

PB2/CCP0 72

USB0RBIAS 73

PE0/EPI0S0874

PE1/EPI0S0975

PE4/ADC36

PE5/ADC25

PA6/USB0EPEN34

PA7/USB0PFLT35

PE6/ADC12

PE7/ADC01

PF0 47

PF1 61

PF2/LED1 60

PF3/LED0 59

MDIO 58

TXON 46

TXOP 43

PF5/EPI0S15 41

PG0/EPI0S1319

PG1/EPI0S1418

XTLN17

XTLP16

PF4/EPI0S12 42

RXIP 40

RXIN 37

PG7/EPI0S3136

PH0/EPI0S06 86

PH1/EPI0S07 85

PH2/EPI0S01 84

PH3/EPI0S00 83

VDDA3

PD5 98PD4 97

GNDA4

VDD 8

VDD 20

VDD 32

VDD 44

VDD 56

VDD 68

VDD 81

VDD 93

PJ2/EPI0S1839

GND45

PJ654

GND57

PH5/EPI0S11 63

GND69

GND82

PJ1/EPI0S1787

GND94

PJ0/EPI0S1614

VDD25 38

PH6/EPI0S26 62

VDD25 88

PJ350

NC51

PJ452

PJ553

PJ755

PB3 65

PH4/EPI0S10 76

U1

LM3S9B96

C60.01UF

C80.01UF

C120.1UF

C100.1UF

M+3.3V

C152.2UF

C210.01UF

+3.3V

PD2/EPI20PD3/EPI21PB4/ADC10/EPI23PB5/EPI22

PE2/EPI24PE3/EPI25

LED1

JP1

PH6/EPI26PH7/EPI27

PA7/USBPFLT/CAN0TXPA6/USBEPE/CAN0RX

PD1/I2SRXWS

PD5/I2SRXMCLK

PE2/EPI24PE3/EPI25PD2/EPI20PD3/EPI21

PB4/ADC10/EPI23PB5/EPI22PH6/EPI26PH7/EPI27

1 2D2

B72590D0050H160

1 2D5

B72590D0050H160

12D1

B72590D0050H160

Indicates factory-default jumper position.

15 Apr 09 First production release

GN

D2

VIN 1VOUT5

PG 4EN 3

U16FAN2558S12X +5V

U16 Required only forLM3S9B96 Rev B1.See errata.

R60

10

R61

10

R60-61 = 10 Ohms for LM3S9B96 Rev B1 (see errata)R60,R11 = 0 Ohms for LM3S9B96 Rev C

Note:

A

Schematic page 1

1

1

2

2

3

3

4

4

5

5

6

6

D D

C C

B B

A A

Document Number:


Drawing Title:

Page Title:

Size


LCD, CAN, Serial Memory, User IO

B

A

DB-LM3S9B96

ResetSW2

SW-B3S1000RESETn

R1910K

+3.3V

User Switch

R18

330

Power

+3.3V

SW1

SW-B3S1000

microSD Card Slot

N/C DATA21

CS DATA32

DI CMD3

VDD4

CLOCK5

GND6

DO DATA07

RSV DATA18

FR1

9

FR2

10

FR3

11

FR4

12

J4

2908-05WB-MG+3.3V

C240.1UF

+3.3V

R1510K

R1610K

+3.3V

+3.3V

LED2Green

C260.1UF

XRYDXLYU

LCD_RSTnCSnSPICLKSPISDI

HSYNCVSYNCDCLK

AVDD

VCCDCRDWRPS0PS1PS2PS3

OE

LED_K

LED_A

LD1LD2LD3LD4LD5

LD6LD7LD8

LD10LD11

LD12LD13LD14LD15LD16LD17

LCD_D0LCD_D1LCD_D2LCD_D3LCD_D4

LCD_D5LCD_D6LCD_D7

LD0

LD9

TOUCH_YP

TOUCH_YNTOUCH_XP

TOUCH_XN

ILED+ 23456789

1011121314151617181920

1

M1

21222324252627282930313233343536373839404142434445464748495051525354555657585960

M2

J6

FPC_Socket_60pin

QV

GA

LC

D P

anel

R2110K

PB7/NMI

+3.3V

Thumbwheel Potentiometer

C320.1UF

C290.1UF

QVGA LCD Panelwith touch interface

LCD_D[0..7]

C280.01UF

C300.01UF

C310.01UF

C330.01UF

+3.3V

R1250K

ILED-

C230.1UF

R1410K

+3.3V

8-bit 8080 mode

PE6/ADC1

PE3/EPI25

PE2/EPI24

PE7/ADC0

X+JP16

Y-JP17

X-JP18

Y+JP19

LD0JP21

LD1JP22

LD2JP23

LD3JP24

LD4JP25

LD5JP26

LD6JP27

LD7JP28

PD2/EPI20

PD3/EPI21

PD6

PD7

LCD_D0

LCD_D1

LCD_D2

LCD_D3

LCD_D4

LCD_D5

LCD_D6

LCD_D7

LDC

JP29LRDn

JP30LWRn

JP31

PH7/EPI27

PH6/EPI26

LCD_DCLCD_RDnLCD_WRn

R11

330PF3/LED0

User LEDLED1Green

POT

JP7

SWITCH

JP6PJ7

PB4/ADC10/EPI23

LED

JP5

SI5

SCK6 nWP3

nCE1

nHOLD7 VDD 8

VSS 4SO2

U2

W25X80AVSSIG-ND

C250.1UF

+3.3V+3.3VR1310K

+3.3V 1MB Serial Flash

PA5/SSI0TX

PA2/SSI0CLK

PA4/SSI0RX

PA3SDCSn

JP9MOSI

JP10SCLK

JP11MISO

JP12

FLCSn

JP8PF0

SD_CSn

MOSI

MISO

SSICLK

FLASH_CSn

CANH 7

CANL 6TXD1

RXD4

RS8

GND2 VREF 5VCC 3

U3

SN65HVD1050D

+5V

CAN Transceiver

C270.1UF

TXD

JP14RXD

JP15

1 23 45 67 89 10

J5CANH

CANL

VREF_3.0V

PA7/USBPFLT/CAN0TX

PA6/USBEPE/CAN0RX

R1710K

LRSTn

JP20

R2010K

+3.3V

R1010K

+3.3V

PD1/I2SRXWS

CARD

JP13

PD4/I2SRXSD

PD5/I2SRXMCLK

PB5/EPI22

+VCAN

JP32

+5V

CAN Connector

+VCAN

PD0/I2SRXSCK

TERM

JP58

R58

120

C220.1UF


R59

100

Schematic page 2

1

1

2

2

3

3

4

4

5

5

6

6

D D

C C

B B

A A

Document Number:


Drawing Title:

Page Title:

Size


Power Supplies

B

A

DB-LM3S9B96

DBG+5V

VBUS Fault Protected Switch

+VBUS

GN

D2

IN5

EN4

OCn3

OUT 1

U6TPS2051BDBV

C402.2UF

C412.2UF

C432.2UF

SHDN4

VIN5 SW 1

GND2

FB 3

U7

FAN5333B

ILED+D3

FYV0704SMTF

+5V

C382.2UF

10uH

L1

NR4018T100M

LED Backlight Controller

C450.1UF

C460.1UF

C440.1UF

R2615

R2510K

ILED-24V

D4BZT52C24

+5V

EPEN

JP37PFLT

JP38

Backlight

JP39

PA7/USBPFLT/CAN0TX

PA6/USBEPE/CAN0RX USB0EPE

USB0PFLT

0.01UF

C39

C422.2UFC37

2.2UF

VOUT 5

NR 1ON3

GN

D2

VIN4

U5PQ1LA333MSPQ

C362.2UF

+5V

ICDI

JP34OTG

JP35EXT

JP36

+5V

+5V DC INPUT

PJ-002BH-SMT

1

23

J7

+VBUS

CATHODE1

ANODE2

NC3

U4

LM4040B30IDB

VREF 3.00V

JP33

R221.5K

+3.3V

C352.2UF

3.0V 0.2% Voltage Reference

Main +3.3V SupplyPower Source Selection

R2410K

R2310K

+3.3V

VREF_3.0V

PB6/TXSCK/AVREF

C340.1UF

GNDTP2

BLON

5.0VTP3

+5V

C200.1UF


+3.3V3.3VTP1

P3V

JP60

M3V

JP61

M+3.3V

GND

JP59

Schematic page 3

1

1

2

2

3

3

4

4

5

5

6

6

D D

C C

B B

A A

Document Number:


Drawing Title:

Page Title:

Size


I2S Audio Expansion Board

B

A

DB-LM3S9B96

1

32

J11

STX-3000

BVDD1

BCLK3

DOUT6

DIN4

LRCIN5

LRCOUT7

CLKOUT 2

HPVDD 8

LHPOUT 9

RHPOUT 10

HPGND 11

LOUT 12

ROUT 13

AVDD 14

AGND 15

VMID 16

MICBIAS17

MICIN18

RLINEIN19 LLINEIN20

nCS21 MODE22

SDIN23

SCLK24

XTI/MCLK25

XTO26

DVDD27

DGND28

U8

TLV320AIC23BPW

C57

0.47UFC58

0.47UFR3347K

R3547K

R36

100

R37

100

Audio Line Output

1

32

J10

STX-3000

4V

+

C55

220UF

4V

+

C54

220UF

R3247K

R3447K

C560.1UF

C592.2UF

C602.2UF

C612.2UF

C500.1UF

1

32

J9

STX-3000

R31

4.7K

R2810K 27PF

C47

C48

2.2UF

MICIN

R3010K

MICBIAS

Audio Headphone Output

Microphone Input

MCLK

LRC

RXSD

BITCLK

TXSD

Analog +3.3V 50mA Power Supply

C520.1UF

Line Input

SDA

JP40PB3/I2C0SDA

PB2/I2C0SCL

PE5/I2STXSD

PE4/I2STXWS

PD4/I2SRXSD

PD1/I2SRXWS

PF1/TXMCLK

SCL

JP41TXSD

JP42TXWS

JP43RXSD

JP44RXWS

JP45PB6/BCLK

JP46

0.01UF

C51C532.2UF

C492.2UF

VOUT 5

NR 1ON3

GN

D2

VIN4

U9PQ1LA333MSPQ

+5V

R274.7K

R294.7K

+3.3V +3.3V

PD5/I2SRXMCLK

PB6/TXSCK/AVREF

PD0/BCLK

JP47PD0/I2SRXSCK

1

32

J8

STX-3000

R54

4.7KR55

4.7K

R564.7K

R574.7K

27PF

C76

27PF

C78

C77

0.47UF C79

0.47UF

PD5/MCLK

JP49

PF1/MCLK

JP48


Rework 2: Loop TXWS to RXWS.

Schematic page 4

1

1

2

2

3

3

4

4

5

5

6

6

D D

C C

B B

A A

Document Number:


Drawing Title:

Page Title:

Size


EPI and SDRAM Expansion Boards

B

A

DB-LM3S9B96

A023 DQ0 2

BA020

BA121

CLK38

CKE37

WE16

DQMH39

NC 40

RAS18

CAS17

VSS28

VSSQ6

VSSQ12

VSSQ46

VSSQ52

VSS41

VSS54

VDDQ 3

VDDQ 9

VDDQ 43

VDDQ 49

VDD 1

VDD 14

VDD 27

A124

A225

A326

A429

A530

A631

A732

A833

A934

A1022

A1135

NC 36

DQ1 4

DQ2 5

DQ3 7

DQ4 8

DQ5 10

DQ6 11

DQ7 13

DQ8 42

DQ9 44

DQ10 45

DQ11 47

DQ12 48

DQ13 50

DQ14 51

DQ15 53CS19

DQML15

U10

MT48LC4M16A2

AD0AD1AD2AD3AD4AD5AD6AD7

AD8AD9AD10AD11D12BA0/D13BA1/D14D15

AD8AD9AD10AD11

CSnWEnRASnCASn

SDCLKSDCKEDQM1DQM0

BA0/D13BA1/D14

AD0AD1AD2AD3AD4AD5AD6AD7

+3.3V

8MB SDRAM

C650.1UF

C640.01UF

C630.01UF

C660.1UF

+3.3V

Expansion Connector

SDRAM Expansion Board

1234567891011121314151617181920212223242526

272829303132333435363738394041424344454647484950

J12

DF12A-50DS

+3.3V

C622.2UF

AD2AD3AD4AD5

SDCLKCASnD15D12

AD9AD8AD11

BA0/D13BA1/D14

DQM0

SDCKECSnWEnRASn

DQM1AD6AD7AD1AD0AD10

Expansion Connector

1234567891011121314151617181920212223242526

272829303132333435363738394041424344454647484950

J15

DF12A-50DS

EPI Signal Breakout Board

X_PH4/EPI10X_PH3/EPI00X_PH2/EPI01X_PH1/EPI07X_PH0/EPI06X_PJ1/EPI17X_PB5/EPI22X_PB4/EPI23X_PE2/EPI24X_PE3/EPI25X_PJ3/EPI19X_PJ4/EPI28X_PJ5/EPI29X_PJ6/EPI30X_PD2/EPI20X_PD3/EPI21

X_PH7/EPI27X_PJ0/EPI16

X_PG1/EPI14X_PG0/EPI13X_PC4/EPI02

X_PC5/EPI03X_PC6/EPI04X_PC7/EPI05

X_PH6/EPI26X_PH5/EPI11X_PE0/EPI08X_PE1/EPI09

X_PG7/EPI31X_PJ2/EPI18X_PF5/EPI15X_PF4/EPI12

X+3.3VX+5V

Schematic page 5

1

1

2

2

3

3

4

4

5

5

6

6

D D

C C

B B

A A

Document Number:


Drawing Title:

Page Title:

Size


In-circuit Debug Interface (ICDI)

B

A

DB-LM3S9B96

GND18

GND25

GND34

ADBUS0 24

ADBUS1 23

ADBUS2 22

ADBUS3 21

ADBUS4 20

ADBUS5 19

ADBUS6 17

ADBUS7 16

ACBUS0 15

ACBUS1 13

ACBUS2 12

ACBUS3 11

BDBUS0 40

BDBUS1 39

BDBUS2 38

BDBUS3 37

BDBUS4 36

BDBUS5 35

BDBUS6 33

BDBUS7 32

BCBUS0 30

BCBUS1 29

BCBUS2 28

BCBUS3 27

SI/WUA 10

SI/WUB 26

GND9

AGND45

VCC 3

VCC 42

VCCIOA 14

VCCIOB 31

AVCC 46

PWREN# 41

XTOUT44 XTIN43

EECS48

EESK1

EEDATA2

TEST47

RESET#4

RSTOUT#5

3V3OUT6

USBDM8

USBDP7

U12

FT2232D

+3.3V

DBG+5V

R41 27

R42 27

+3.3V

+3.3V

DBG_JTAG_EN

R3910K

R40

1.5K

R441.5K

R45

330

+5V

+5V

+5V+5V

FT_TCKFT_TDI/DIFT_TDO/DOFT_TMS/OUTEN

0.1UF

C710.1UF

C72

0.1UF

C73

0.1UF

C74

0.1UF

C75

0.1UF

C70

USB Device Controller

Channel A : JTAG / SW Debug

Channel B : Virtual Com Port

5V D- D+ ID G

1 2 3 4

7

5

6

J13 54819-0572

FT_SRSTN

Debugger USB Interface

R43USBSH

CS 1

SK 2

DI 3

DO 4GND5 ORG6 NC7 VCC8

1K 64X16

U11

CAT93C46

1 2Y3

6.00MHz

27PF

C68

27PF

C69

SWO_EN

0.01UF

C67

2 3

1

U14A

SN74LVC125A

5 6

4

U13BSN74LVC125A

98

10

U13CSN74LVC125A

12 11

13

U14DSN74LVC125A2 3

1

U13ASN74LVC125A

56

4

U14BSN74LVC125A

9 8

10

U14CSN74LVC125A

2 3

1

U15ASN74LVC126A

5 6

4

U15BSN74LVC126A

98

10

U15CSN74LVC126A

1211

13

U15DSN74LVC126A

VCP_TX_SWO

DBGENn

12 11

13

U13DSN74LVC125A

1234567891011121314151617181920

J14

2X10 HDR-SHRD+3.3V

TDI

TCK

R46

27

TMS_SWDIO

SRSTN

TDO_SWO

VCP_TX

R47

27R48

27R49

27R50

27

PIN1

JP57

TCK

JP50PC0/TCK

PC1/TMS

PC2/TDI

PC3/TDO

TMS

JP51TDI

JP52TDO

JP53

TCK

TDI

TMS_SWDIO

TDO_SWO

TDI

TMS_SWDIO

TCK

TDO_SWO

SRSTN

R3810K

+3.3v

RESETnRSTn

JP54

SRSTN

PA1/U0TXVCPTX

JP55

PA0/U0RXVCPRX

JP56

VCP_RX

VCP_RX

VCP_TX

JTAG/SWD In/Out

147

VCC

GND

U14ESN74LVC125A

147

VCC

GND

U13ESN74LVC125A

147

VCC

GND

U15ESN74LVC126A

+3.3V +3.3V +3.3V

0.1UF

C80

+3.3V

R5110K

+3.3V

R5210K

R5310K


Schematic page 6


Stellaris® LM3S9B96 Development Board Component Locations

This appendix contains details on component locations, including:

Component placement plot for top (Figure B-1)

A P P E N D I X B


Figure B-1. Component Placement Plot for Top


Stellaris® LM3S9B96 Development Board Connection Details

This appendix contains the following sections:

DC Power Jack (see page 35)

ARM Target Pinout (see page 35)

DC Power JackThe EVB provides a DC power jack for connecting an external +5 V regulated (+/-5%) power source.

The socket is 5.5 mm dia with a 2.1 mm pin.

ARM Target PinoutIn ICDI input and output mode, the Stellaris® LM3S9B96 Development Kit supports ARM’s standard 20-pin JTAG/SWD configuration. The same pin configuration can be used for debugging over serial-wire debug (SWD) and JTAG interfaces.

Insert Jumper VDD/PIN1 Jumper (JP57) only when using the development board with an external debug interface such as a ULINK or JLINK.

Table C-1. Debug Interface Pin Assignments

Function Pin Number

TDI 5

TDO/SWO 13

TMS/SWDIO 7

TCK/SWCLK 9

System Reset 15

VDD 1

GND 4, 6, 8, 10, 12, 14, 16, 18, 20

No Connect 2, 3, 11, 17, 19

Center Positive (+)

A P P E N D I X C


Stellaris® LM3S9B96 Development Board Microcontroller GPIO Assignments

Table D-1 shows the pin assignments for the LM3S9B96 microcontroller.

Table D-1. Microcontroller GPIO Assignments

LM3S9B96 GPIO Pin Development Board Use

Number Description Default Function Default Use Alt. Function Alternate Use

26 PA0 U0Rx Virtual Com Port

27 PA1 U0Tx Virtual Com Port

28 PA2 SSI0Clk SPI

29 PA3 SSI0Fss SD Card CSn

30 PA4 SSI0Rx SPI

31 PA5 SSI0Tx SPI

34 PA6 USB0EPEN USB Pwr Enable CAN0RX

35 PA7 USB0PFLT USB Pwr Fault CAN0TX

66 PB0 USB0ID USB OTG ID

67 PB1 USB0VBUS USB Vbus

72 PB2 I2C0SCL Audio I2C

65 PB3 I2C0SDA Audio I2C

92 PB4 ADC10 Potentiometer EPI0S23 EPI Breakout

91 PB5 PB5 LCD RDn EPI0S22 EPI Breakout

90 PB6 PB6 I2STXSCK AVREF Ext Volt Ref

89 PB7 PB7 LCD RST

80 PC0 TCK/SWCLK JTAG

79 PC1 TMS/SWDIO JTAG

78 PC2 TDI JTAG

77 PC3 TDO/SWO JTAG

25 PC4 EPI0S2 SDRAM D02 EPI0S02




A P P E N D I X D


10 PD0 PD0 LCD Data 0 I2SRXSCK I2S Audio In

11 PD1 PD1 LCD Data 1 I2S0RXWS I2S Audio In

12 PD2 PD2 LCD Data 2 EPI0S20 EPI Breakout

13 PD3 PD3 LCD Data 3 EPI0S21 EPI Breakout

97 PD4 PD4 LCD Data 4 I2SRXSD I2S Audio In

98 PD5 PD5 LCD Data 5 I2SRXMCLK I2S Audio In

99 PD6 PD6 LCD Data 6

100 PD7 PD7 LCD Data 7

74 PE0 EPI0S8 SDRAM D8 EPI0S08

75 PE1 EPI0S9 SDRAM D9 EPI0S09

95 PE2 PE2 Touch XN EPI0S24

96 PE3 PE3 Touch YN EPI0S25

6 PE4 I2STXWS I2S Audio Out

5 PE5 I2STXSD I2S Audio Out

2 PE6 ADC1 ADC Touch XP

1 PE7 ADC0 ADC Touch YP

47 PF0 PF0 Flash CSn

61 PF1 I2STXMCLK I2S Audio Out

60 PF2 LED1 Green Enet LED

59 PF3 PF3 User LED LED0 Yw Enet LED

42 PF4 EPI0S12 SDRAM D12

41 PF5 EPI0S15 SDRAM D15

19 PG0 EPI0S13 SDRAM D13

18 PG1 EPI0S14 SDRAM D14

36 PG7 EPI0S31 SDRAM CLK

86 PH0 EPI0S06 SDRAM D06





Table D-1. Microcontroller GPIO Assignments (Continued)






62 PH6 EPI0S26 LCD_WRn EPI0S26 EPI Breakout

15 PH7 EPI0S27 LCD_DC EPI0S27 EPI Breakout

14 PJ0 EPI0S16 SDRAM DQM

87 PJ1 EPI0S17 SDRAM DQM

39 PJ2 EPI0S18 SDRAM CAS

50 PJ3 EPI0S19 SDRAM RAS

52 PJ4 EPI0S28 SDRAM WEn

53 PJ5 EPI0S29 SDRAM CSn

54 PJ6 EPI0S30 SDRAM SDCKE

55 PJ7 PJ7 User Switch

Table D-1. Microcontroller GPIO Assignments (Continued)




Stellaris® LM3S9B96 Flash and SRAM Memory Expansion Board

This document describes the Flash and SRAM memory expansion board (DK-LM3S9B96-EXP-FS8) plug-in for the DK-LM3S9B96 development board. This expansion board works with the External Peripheral Interface (EPI) port of the Stellaris microcontroller and provides Flash memory, SRAM, and an improved performance LCD interface.

Figure E-1. Flash and SRAM Memory Expansion Board

FeaturesThe DK-LM3S9B96-EXP-FS8 memory expansion board has the following features:

8 Megabytes of Flash memory

1 Megabyte of SRAM

Memory-mapped LCD I/F for improved LCD performance

1 kilobit of I2C memory for storing configuration data

Power LED indicator

InstallationTo install the expansion board on the DK-LM3S9B96 development board, do the following:

1. Remove the DK-LM3S9B96-EXP-FS8 memory expansion board from the antistatic bag.

2. On the DK-LM3S9B96 board, remove any installed board on EPI connector J2.

A P P E N D I X E


3. On the DK-LM3S9B96 board remove the shunt jumpers on JP16-JP31 and the JP39 headers as shown in Figure E-1 on page 41.

Figure E-2. Removing EPI Board from DK-LM3S9B96 Development Board

4. Install the two snap-in nylon standoffs on mounting holes above the EPI connector J2.

5. Place the expansion board on top of the DK-LM3S9B96 board and align the standoffs, the EPI connector, and the 2x17 J2 header.

6. Press firmly downward until the board snaps in, then verify that the board is firmly seated on the EPI connector, the 2x17 header, and the standoffs.

7. When powering up the board, verify that the power indicator LED D1 is lit.

Remove board

Remove jumpers



Hardware DescriptionThe Flash and SRAM memory expansion board is designed for use with the Stellaris EPI module configured in Host Bus 8 address/data multiplexed mode. This mode requires the use of an external 8-bit latch for storing the lower 8 address lines A[7:0] transmitted during the address phase of an EPI transfer. This latch can be seen on the expansion board block diagram shown in Figure E-3.

Figure E-3. Flash/SRAM/LCD IF Expansion Board Block Diagram

Functional DescriptionThe Flash and SRAM memory expansion board schematics are described in this section. The first page of the schematics shows the memory devices and address latch part of the design. The second page shows the LCD I/F and regulator.

Flash/SRAM (Schematic 1 on page 47)Page 1 of the schematics shows the EPI connector, address latch, and memory devices.

EPI ConnectorThe EPI connector J1 is a 50-pin receptacle with 0.5 mm pitch that plugs into the EPI header on the DK-LM3S9B96 board. The 32 EPI signals and the 2 I2C0 signals from the LM3S9B96 are provided on this connector. It also provides 5 V for the on-board DC regulator. Note that not all EPI signals are used in this design.

MA[7:0]

MAD[7:0]EPI[27:8]

EPI[7:0]

OEnWRn

EPI30

EPI Connector

FLASH/SRAM/LCD IF Board

D QLMA[27:8]

ALEMA27

EPI29EPI28

MAD[7:0]

AD

SRAM

WEOE

1MB

AD

FLASH

WE

CSOE

8MB

LCD Connector

LCD ControlLCD

DECODELCD Data

CE2MA27MA26 CE1


8-bit LatchThis 8-bit latch is used to store the lower 8-bits of the address, which are transmitted during the address phase of an EPI transfer. The EPI must be configured in Host bus 8 mode 0 mode (HB8 ADMUX), with EPI30 configured as an Address Latch Enable (ALE) signal to control this latch.

Flash MemoryThe Flash memory used is a 64 Mbit, 90-nsec Spansion S29GL064N90TFI040. This 8/16 bit memory is used in 8-bit mode. Note that MA27 is used as a chip select signal for this memory.

SRAMThe SRAM used is an 8 Mbit, 45 nsec Cypress Semiconductor CY62158EV30LL-45ZSX, which is an 8-bit memory. Note that MA27 and MA26 are used as chip selects for this memory.

I2C MemoryThis I2C serial memory is used for storing configuration data. This is a 1 kilobit On-Semiconductor memory.

LCD I/F, Power (Schematic 2 on page 48)Page 2 of the schematics shows the LCD_DECODE CPLD, LCD interface connector, and the 3.3 V regulator.

LCD_DECODE CPLDThe LCD DECODE CPLD provides address latch and decode for the LCD interface. The LCD Command and Data registers are mapped on the EPI memory space to streamline access to these registers. The LCD panel control signals L_RDn, L_RWn, and L_DC and the L_D bus are controlled by decode logic on the CPLD with timing derived from EPI signals and do not require direct control from the microcontroller. The LCD latch register is provided to control the XN and YN signals used for the touchscreen and also the reset signal to the LCD.

The LCD backlight signal L_BL is controlled by the Stellaris GPIO PE2 (MA[24]). PE2 can be programmed as a GPIO for ON/OFF control of the LCD. A second option is to configure PE2 for use as CCP2 or CCP4 with a PWM output for brightness control.

The TP1-TP4 testpoints connect to the CPLD JTAG signals and, along with TP5 and TP6, provide an interface for test and programming of the CPLD.

LCD Interface ConnectorThe LCD Interface Connector J2 is a 2x17 socket that connects to headers JP16-JP31 and JP39 on the DK-LM3S9B96. All signals previously driven to the LCD from the Stellaris MCU are replaced by equivalent signals driven from the LCD_DECODE CPLD.

DC RegulatorDC regulator U4 receives 5 V from the EPI connector and provides 3.3 V for the board. LED D1 provides a power indicator and lights when the regulator is providing power to the board.



Memory MapThe DK-LM3S9B96-EXP-FS8 expansion board memory map is shown in Table E-1 and Table E-2 shows the LCD Latch register.

The LCD Latch register is implemented as a set/clear register. To set a bit, the corresponding bit must be set when writing to the LCD Latch Set register. To clear a bit, the corresponding bit must be set when writing to the LCD Latch Clear register.

XN When clear, the L_XN signal is set to clear. When set, the L_XN signal is tri-stated. This signal is used for the X- input to the touchscreen.

YN When clear, the L_YN signal is set to clear. When set, the L_YN signal is tri-stated. This signal is used for the Y- input to the touchscreen.

RST When clear, the L_RSTN signal is set to clear. When set, the L_RSTN signal is reset. This signal is used to reset the LCD panel.

Table E-1. Flash and SRAM Memory Expansion Board Memory Map

Device A[27:26] A[2:0] Description Access Base address

FLASH 0X XXX Flash memory (8 Megabytes) R/W 0x6000.0000

SRAM 10 XXX SRAM (1 Megabyte) R/W 0x6800.0000

CPLD11 000 LCD latch set R/W 0x6C00.0000

11 001 LCD latch clear R/W 0x6C00.0001

LCD11 010 LCD command port Ra/W

a. For reads to the LCD Command and Data Port registers, the corresponding LCD Port Read Start register must be read first, followed by a 500 nsec delay before reading this register.

0x6C00.0002

11 011 LCD data port Ra/W 0x6C00.0003

LCD11 110 LCD command port read start R 0x6C00.0006

11 111 LCD data port read start R 0x6C00.0007

Table E-2. LCD Latch Register

7 6 5 4 3 2 1 0

Reserved RST YN XN

0 0 0 0 0 R/W R/W R/W


Component LocationsFigure E-4 shows the details of the component locations.

Figure E-4. Component Placement Plot for Top and Bottom

SchematicsThis section shows the schematics for the DK-LM3S9B96-EXP-FS8 memory expansion board:

Flash, SRAM on page 47

LCD Interface on page 48

Top Bottom

1

1

2

2

3

3

4

4

5

5

6

6

D D

C C

B B

A A

Document Number: Rev

SheetDate: of7/21/2009 1 2

B

Designer:

Drawn by:

Approved:

Drawing Title:

Page Title:

Size

Arnaldo Cruz

Arnaldo Cruz

* 0001

FLASH / SRAM / LCD IF board for DK-LM3S9B96

FLASH, SRAM

B

108 Wild Basin Rd.Suite 350Austin, TX 78746

TI AEC - Austin

Revision History

Revision

A 5/29/2009 Released for manufacturing.

Date Description

3.3V

MA0MA1MA2MA3MA4MA5MA6MA7MA8MA9MA10MA11MA12MA13MA14MA15MA16MA17MA18

MAD0MAD1MAD2MAD3MAD4MAD5MAD6MAD7

R2 10K

PG0/EPI13PG1/EPI14PH7/EPI27PJ0/EPI16PD3/EPI21PD2/EPI20PJ6/EPI30PJ5/EPI29PJ4/EPI28PJ3/EPI19PE3/EPI25PE2/EPI24PB4/EPI23PB5/EPI22PJ1/EPI17PH0/EPI6PH1/EPI7PH2/EPI1PH3/EPI0PH4/EPI10

1234567891011121314151617181920212223242526

272829303132333435363738394041424344454647484950

J1

DF12A-50DS



PE1/EPI9PE0/EPI8PH5/EPI11PH6/EPI26

3.3V

3.3V5V

MA8MA9

MA10MA11

MA12

MA13MA14

MA15

MA16

MA17MA18

MA19

MA20MA21

MA22MA23MA24MA25

MA26

MAD0MAD1

MAD2MAD3MAD4MAD5

MAD6MAD7

TP7

3.3V

MA0MA1MA2MA3MA4MA5MA6MA7MA8MA9MA10MA11MA12MA13MA14MA15MA16

MA27

TP8

ALE

R1 0

C40.1uF

C50.1uF

C10.1uF

3.3V

C100.1uF

R5 2.80k

3.3V

R6 2.80k

I2CSCLI2CSDA

MA19MA20MA21MA22


A05 DQ0 9

A14

A23

A32

A41

A544

A643

A742

A839

A928

A1027

A1126

A1225

DQ1 10

DQ2 13

DQ3 14

DQ4 31

DQ5 32

DQ6 35

DQ7 36

A1324

A1423

A1522

A1621

A1720

WE17 OE41

CE16

VSS12

VSS34 VCC 11

8Mbit

CE240

NC 7

NC 8

NC 15

NC 16

NC 29

NC 30

NC 37

NC 38

A1918 A1819

VCC 33

U2

CY62158EV30

MA0MA1MA2MA3MA4MA5MA6MA7

3.3V

C120.1uF


MA17MA18MA19

MA26MA27

MA27

EPI I/F

3.3V

R410K

C110.1uF

Decode Table

Device

FLASH 0X

MA[27:26]

SRAM

LCD

10

11

GND10 VCC 20

D13

D24

D37

D48

D513

D614

D717

D818

Q1 2

Q2 5

Q3 6

Q4 9

Q5 12

Q6 15

Q7 16

Q8 19

OE1 LE11

U3

74LVC373

Flash memory

SRAM memory

LCD Latch/Port

Description

MAD[7..0]

MA[27..0]

MAD[7..0]

MA[27..0]

MOEnMWEn

MOEnMWEn

MWEn

MOEn

F_RSTn

R310K

3.3V

ALE

A01

A12

A23 SDA 5

GND4

SCL 6

WP7

VCC 8

1K - 128X8

U5

CAT24C01

FLASH

SRAM

Note: R1 is not fitted

B 7/17/2009 Changed J2 to top entry, moved to bottom. Added R9-R11.

A025 DQ0 29

A124

A223

A322

A421

A520

A619

A718

A88

A97

A106

A115

A124

DQ1 31

DQ2 33

DQ3 35

DQ4 38

DQ5 40

DQ6 42

DQ7 44

A133

A142

A151

A1648

A1717

RDY 15

WE11 OE28 CE26

VSS27

VSS46 VCC 37

64Mbit

BYTE47

DQ8 30

DQ9 32

DQ10 34

DQ11 36

DQ12 39

DQ13 41

DQ14 43

DQ15/A-1 45

RP12

A1816

A199

A2010

A2113

VPP/WP 14

U1

S29GL064N

Flash, SRAM

1

1

2

2

3

3

4

4

5

5

6

6

D D

C C

B B

A A



B

Drawing Title:

Page Title:

SizeB

LCD Interface

FLASH / SRAM / LCD IF board for DK-LM3S9B96

0001

L_YNL_XN L_D4

L_D1

L_D0L_D3L_D6L_D7L_D2L_D5

L_RSTnL_BL

L_D0L_D1L_D2L_D3L_D4L_D5L_D6L_D7

3.3V

C20.1uF

L_RDn

MOEn

L_D[7..0]

MAD[7..0] MAD[7..0]

MA[27..0] MA[27..0]

3.3V

C64.7uFC8

4.7uF

5V

R7330

PWR

D1GREEN_LED

R8 10K

C90.1uF

F_RSTn

F_RSTn

3.3V

L_DC

A0/GOE044

A145

A246

A347

A448

A52

A74 A63

A87

A98

A109

B0 20

B1 21

B2 22

B3 23

B4 24

B5 26

B6 27

B7 28

B8 31

B9 32

B10 33

B11 34

B12 38

B13 39

B14 40

A1214

A1315

A1416

A1517

TDI1

TCK11

TMS25

TDO35

GND015

GND113 GND1129

GND237

VCC01 6

VCC1 12VCC11 30

VCC2 36

A1110

CLK2/IN219 CLK1/IN118

B15/GOE1 41

CLK3/IN342

CLK0/IN043

U6

LC4032V


MA24MA25MA26MA27

ALE

L_WRn

C30.1uF

C70.1uF

C130.1uF

CPLD_TCKCPLD_TMSCPLD_TDICPLD_TDO

TP1TP2TP3TP4TP5TP6

VIN1 VOUT 5

SHDN3

GND2 NR 4

U4

TPS73033

MWEn

LCD_DECODE CPLD

L_WRn

L_YP

L_XP

LCD I/F

L_DC

L_BL

L_YN

L_XN

L_D0

L_D1

L_D2

L_D3

L_D4

L_D5

L_D6L_D7

L_RSTn

L_RDn

246810121416182022242628303234

13579

111315171921232527293133

J2

SMT Socket 2x17

R9 10KR10 10KR11 10K

LCD Interface


Stellaris® LM3S9B96 FPGA Expansion BoardThis chapter describes the FPGA expansion board for the DK-LM3S9B96 development board.The FPGA expansion board provides a quick start platform to evaluate the capabilities of the Stellaris External Peripheral Interface (EPI) using the highly integrated DK-LM3S9B96 development platform.

This combination adds full-screen motion video to the powerful, easy-to-use StellarisWare® GUI tools. Figure F-1 shows a photo of the FPGA expansion board.

Figure F-1. FPGA Expansion Board

FeaturesThe LM3S9B96 FPGA memory expansion board has the following features:

Xilinx Spartan 3E FPGA with 100k system gates

1/13" CMOS VGA (640 x 480) Color Camera Module

1 MB of asynchronous 10 nsec SRAM for graphics/video buffers

Standard 1 x 6 and 2 x 5 JTAG headers for FPGA programming

1 kilobit of I2C memory for storing configuration data

8 FPGA test pads provide 5 inputs and 3 I/Os

All necessary power regulation

The default FPGA image adds the following features:

EPI operation in GPM D16-A12 mode at 50 MHz, up to 100 MB/s

Graphical on-screen-display (OSD) overlaid on moving QVGA video

A P P E N D I X F


Widget-based touchscreen user interface

Screen capture to SDCard or USB stick in Windows bitmap (BMP) format

Brightness, saturation, tint/hue, and sharpness picture controls

Mirror/Flip/Normal Picture controls

InstallationTo install the expansion board on the DK-LM3S9B96 development board, do the following:

1. Remove the LM3S9B96 FPGA memory expansion board from the antistatic bag.

2. On the DK-LM3S9B96 board, remove any installed board on EPI connector J2.

3. On the DK-LM3S9B96 board, remove the shunt jumpers on JP16-JP31 and the JP39 headers as shown in Figure F-1 on page 49.

4. Place the expansion board on top of the DK-LM3S9B96 board and press firmly downward until the board snaps in.

5. Connect the the male EPI expansion connector on the bottom side of the FPGA expansion board to the female EPI expansion connector on the DK-LM3S9B96 development board (J2). The LCD header pins should fit through the holes on the PCB.

6. Use the included jumper wire to provide 5 V power to J5 from any of the three upper pins immediately below and to the right of the EXT+5V connector on the development board.

7. When powering up the board, verify that the power indicator LED D1 is lit.



Figure F-2. Removing EPI Board from DK-LM3S9B96 Development Board

Remove board

Remove JP16-31

5 V Power

Remove POT/PB4

jumpers

jumper


Hardware DescriptionThe FPGA expansion board is designed for use with the Stellaris EPI module. Figure F-3 shows a simplified system block diagram. Components of the default FPGA board are shown in half-tone outline.

Figure F-3. FPGA Expansion Board Block Diagram

FPGAThe FPGA expansion board features a Xilinx Spartan 3e FPGA, which interfaces to the Stellaris® microcontroller through its EPI port and acts as a crossbar to the rest of the peripherals.

CameraThe Omnivision OV7690 camera provides color VGA images at up to 30 frames per second to the FPGA over an 8-bit wide parallel interface. It is configured by the Stellaris microcontroller via I2C.

SRAMThe 1 MB, 8-bit wide, 10 ns SRAM is nominally used as a set of frame buffers. 16 bits of the 20-bit address space are latched and multiplexed with its data. Access time may be dependent on the previous address.

Configuration PROMA Xilinx standard configuration PROM holds the default FPGA image and automatically uploads it at power-on.

Configuration PushbuttonTo reload the configuration PROM image to the FPGA, press the configuration pushbutton. This allows you to load a new image via JTAG without resetting the rest of the system.



Test PortEight uncommitted FPGA pins are brought to test pads. Five of the FPGA pins can only be used as inputs. The remaining three FPGA pins can be used as inputs or outputs.

Camera ConnectorThe camera is hosted by the FPC Connector P1 located to the left of the FPGA. To insert or remove the camera, first open the latch by grasping either side of the connector and gently lifting straight up. With the latch open, the camera moves easily; do not force. The camera faces away from the FPGA. Close the latch by pushing down on it gently before use.

Caution – Handle the camera carefully when inserting or removing it from the board. Never force the camera into a different position, doing so could damage the camera.

5 V Power PinJ5 is used to provide 5-V power to the FPGA expansion board's regulators. This must be connected for successful board operation. Connect the the male EPI expansion connector on the bottom side of the FPGA expansion board to the female EPI expansion connector on the DK-LM3S9B96 development board (J2). The LCD header pins should fit through the holes on the PCB.

24-MHz OscillatorThe camera and the camera interface portion of the FPGA are clocked by a 24-MHz external oscillator.

External Peripheral Interface (EPI) ModuleThe External Peripheral Interface (EPI) module provides a slave interface for use with the Stellaris microcontroller’s EPI controller configured in general-purpose mode A12-D16. The direction of the signal allocation is in relation to the FPGA (for example, a signal labeled In is an input to the FPGA, a signal labelled Out is an output from the FPGA). See Table F-8 on page 63 for a list of the EPI signals.

NOTE: Only 16-bit or 32-bit transfers are allowed for this interface.

Using the Widget InterfaceThis section provides information about writing your own graphics using the widget interface for the FPGA expansion board.

Writing Your Own Stellaris ApplicationThe Stellaris microcontroller communicates with the default FPGA image through a memory-mapped interface. To get started, you must first configure the EPI port by doing the following:

1. Configure the GPIO.

2. Configure the EPI port and map it into memory at 0xA000.0000.

Code Example F-1 Configuring the EPI PortEPIModeSet(EPI0_BASE, EPI_MODE_GENERAL); //General Purpose modeEPIDividerSet(EPI0_BASE, 1); //Divide system clock by 2


EPIConfigGPModeSet(EPI0_BASE,(EPI_GPMODE_DSIZE_16 //16 Bit data| EPI_GPMODE_ASIZE_12 //12 Bit address| EPI_GPMODE_WORD_ACCESS //Use Word Access Mode| EPI_GPMODE_READWRITE //Use read and write strobe pins| EPI_GPMODE_READ2CYCLE //Reads take two cycles| EPI_GPMODE_CLKPIN //EPI outputs clock to peripheral| EPI_GPMODE_RDYEN ), //Peripheral emits a ready signal0, //Not using frame signal, so ignore0); //Not using clock enable, so ignore

EPIAddressMapSet(EPI0_BASE,EPI_ADDR_PER_SIZE_64KB //64kB memory space | EPI_ADDR_PER_BASE_A); //EPI base address is 0xA0000000

Memory MapThe LM3S9B96 FPGA expansion board memory map is shown in Table F-1. The default Stellaris code maps this into the 0xA000.0XXX memory space. Detailed descriptions for each register are provide in “Register Descriptions” on page 55.

NOTE: Ten bits are used for addressing, but the EPI controller allocates a 12-bit address space. The result is that 0x0A00.0000 is equivalent to 0x0A00.0400, 0x0A00.0800, and 0x0A00.0C00.

Table F-1. FPGA Expansion Board Memory Map

Register A[10:1] Size Register Name Access See Page

VERSION 000 [15:0] Board and FPGA Design Version R 55

SYSCTRL 002 [15:0] System Control R/W 56

IRQEN 004 [15:0] Interrupt Enable R/W 57

IRQSTAT 006 [15:0] Interrupt Status R/W 57

MEMPAGE 008 [10:0] Memory Page R/W 58

TPAD 00A [7:0] Test Pad R/W 58

LCTRL010 [3:0] LCD Control Set R/W

58012 [3:0] LCD Control Clear R/W

CHRMKEY 022 [15:0] Chroma Key R/W 59

VCRM 026 [8:0] Video Capture Row Match R/W 59

VML 030 [15:0] Video Memory Address Low R/W 59

VMH 032 [4:0] Video Memory Address High R/W 59

VMS 034 [11:0] Video Memory Stride R/W 59

LRM 036 [7:0] LCD Row Match R/W 59

LVML 040 [15:0] LCD Video Memory Address Low R/W 60

LVMH 042 [4:0] LCD Video Memory Address High R/W 60

LVMS 044 [11:0] LCD Video Memory Stride register (in bytes). R/W 60



Register DescriptionsThis section provides the detailed register information for the FPGA expansion board.

Version RegisterThe Version register communicates the revision numbers of the PCB, the FPGA RTL, and the Stellaris silicon. A dummy write of 0x0000 to this register determines if the Stellaris silicon is revision C (or higher) and configures the EPI clocking circuit appropriately. This is required during initialization for proper operation.

Bit Name Description

PCB Board Version: Revision level of the FPGA expansion board.

RevC: This bit is high if the FPGA believes it is communicating with Revision C of the silicon (or higher). This bit is only valid after being initialized as described above.

RTL Version Revision level of the code running in the FPGA expansion board.

LGML 050 [15:0] LCD Graphics Memory Address Low R/W 60

LGMH 052 [4:0] LCD Graphics Memory Address High R/W 60

LGMS 054 [11:0] LCD Graphics Memory Stride R/W 60

MPNC 056 [9:0] Memory Port Number of Columns R/W 60

MPR 058 [8:0] Memory Port Current Row R/W 60

MPC 05A [9:0] Memory Port Current Column R/W 60

MPML 05C [15:0] Memory Port Address Low R/W 60

MPMH 05E [4:0] Memory Port Address High R/W 60

MPMS 060 [11:0] Memory Port Stride R/W 60

MPORT 080 [15:0] Memory Port R/W 61

MEMWIN 400 [15:0] Memory Window R/W 61

Table F-2. Version Register

VERSION: 0xA000.0000

15 14 13 12 11 10 9 8

PCB Board Version 0 0 RevC

R R R R R R R R

7 6 5 4 3 2 1 0

RTL Major Version RTL Minor Version

R R R R R R R R

Table F-1. FPGA Expansion Board Memory Map (Continued)

Register A[10:1] Size Register Name Access See Page


System Control RegisterThe System Control register provides access to configuration bits for the video capture and display system. It is implemented as a read-modify-write register and includes LCD and capture modes.


VCEN Video capture DMA enable. Enables video capture to memory. Disabling this bit captures the remainder of the current frame, and then stops.

LVDEN LCD Video DMA enable. Enables DMA from the video memory region to the LCD.

LGDEN LCD Graphics DMA enable. Enables DMA from the graphics memory region to the LCD.

CMKEN Chroma key enable.

VSCALE Video scale control. Scales the video during output to the LCD. If set, the LCD DMA engine skips every other pixel and every other row during LCD video DMA output (Graphics DMA is not affected). As a result, the video object displays at ¼ its normal size.

MPRI Memory port row increment. If set to 0, any read or write to the memory port auto increments the MPC register at the end of the transfer by 1. If MPC is at the last column (MPNR-1), then it sets to 0 and the MPR increments by 1. If the end of the row is reached, then it increments by columns. If set to 1, any read or write increments by rows.

VCQVGA Video Capture is QVGA/VGA. If set to 0, the video capture controller assumes that the camera is configured for VGA capture. If set to 1, it assumes that the camera is configured for QVGA. This only affects video capture; the camera’s I2C and LCD settings must be reconfigured manually.

VCTEST Video Capture Test. When set to 1, the incoming pixel stream is ignored and replaced with a test pattern.

PCBrA PCB is Revision A. An early internal revision of the PCB had a different pin configuration for the camera data port. Setting this bit to 1 provides backwards compatibility.

Table F-3. System Control Register

SYSCTRL: 0xA000.0002

15 14 13 12 11 10 9 8

0 0 0 0 0 0 0 PCBrA

R R R R R R R R/W

7 6 5 4 3 2 1 0

VCTEST

VCQVGA MPRI VSCAL

ECMKE

N LGDEN LVDEN VCEN

R/W R/W R/W R/W R/W R/W R/W R/W



Interrupt Enable RegisterThe Interrupt Enable register masks or enables interrupts from the FPGA to the Stellaris LM3S9B96 microcontroller. Masked interrupts will not assert the IRQ line, but they will still appear in the Interrupt Status Register.


VCFSIE Video capture frame start interrupt enable.

VCFEIE Video capture frame end interrupt enable.

VRMIE Video capture row match interrupt enable.

LTSIE LCD transfer start interrupt enable.

LTEIE LCD transfer end interrupt enable.

LRMIE LCD display row match interrupt enable.

Interrupt Status RegisterThe Interrupt Status register reports and clears interrupts from the camera and LCD systems. An interrupt latches its corresponding bit high until cleared by writing a 1 to it.


VCFSI Video capture frame start interrupt. Clear the interrupt by setting the corresponding bit to 1. Setting the bit to 0 has no effect.

Table F-4. Interrupt Enable Register

IRQEN: 0xA000.0004

15 14 13 12 11 10 9 8

0 0 0 0 0 0 0 0

R R R R R R R R

7 6 5 4 3 2 1 0

0 0 LRMIE LTEIE LTSIE VRMIE VCFEIE VCFSIE

R R R/W R/W R/W R/W R/W R/W

Table F-5. Interrupt Status Register

IRQSTAT: 0xA000.0006

15 14 13 12 11 10 9 8

0 0 0 0 0 0 0 0

R R R R R R R R

7 6 5 4 3 2 1 0

0 0 LRMI LTEI LTSI VRMI VCFEI VCFSI

R R R/W R/W R/W R/W R/W R/W


VCFEI Video capture frame end interrupt. Clear the interrupt by setting the corresponding bit to 1. Setting the bit to 0 has no effect.

VRMI Video capture row match interrupt. Clear the interrupt by setting the corresponding bit to 1. Setting the bit to 0 has no effect.

LTSI LCD transfer start interrupt. Clear the interrupt by setting the corresponding bit to 1. Setting the bit to 0 has no effect.

LTEI LCD transfer end interrupt. Set to 1 to clear the corresponding bit. Clear the interrupt by setting the corresponding bit to 1. Setting the bit to 0 has no effect.

LRMI LCD display row match interrupt. Clear the interrupt by setting the corresponding bit to 1. Setting the bit to 0 has no effect.

Memory Page RegisterThe Memory Page register selects to memory page to access.

Test PadRegisterThe Test Pad register is used to access the on-board test pads TP1-TP8, which are connected to unused FPGA pins.


TP1-TP3 Test Pins 1-3. These are connected to FPGA I/O pins. Writing a 1 sets the corresponding test pin output to 1. Writing a 0 sets the corresponding test pint output to 0. Reading these bits returns the value at the corresponding test pin input.

NOTE: The FPGA output driver for these signals is always enabled.

TP4-TP8 Test Pins 4-8.These are connected to FPGA input pins. Writing these bits has no effect. Reading these bits returns the value at the corresponding test pin input.

LCD Control RegisterThe LCD Control register is implemented as a set/clear register and contains four bits for LCD panel control. To set a bit, set the corresponding bit to 1 when writing to the LCD Control Set register. To clear a bit, set the corresponding bit when writing to the LCD Control Clear register.

Table F-6. Test Pad Register

TXPAD: 0xA000.000A

15 14 13 12 11 10 9 8

0 0 0 0 0 0 0 0

R R R R R R R R

7 6 5 4 3 2 1 0

TP8 TP7 TP6 TP5 TP4 TP3 TP2 TP1

R R R R R R/W R/W R/W




XN LCD panel touchscreen X control. When set to 0, the LCD Xn signal is set to 0. When set to 1, the LCD Xn signal is tri-stated.

YN LCD panel touchscreen Y control. When set to 0, the LCD Yn signal is set to 0. When set to 1, the LCD Yn signal is tri-stated.

RST LCD panel reset control. When set to 0, the LCD RSTn signal is set to 0. When set to 1 the LCD RSTn signal is set to 1.

BL LCD backlight control. When set to 0, the LCD panel backlight is turned off. When set to 1, the LCD panel backlight is turned on.

Chroma Key RegisterThe CHRMKEY register contains the RGB values to compare for graphics overlay operation. During LCD screen updates, data from graphics memory is compared with this register, if a match occurs, the corrsponding frame video pixel is sent to the output instead.

Video Capture Row Match RegisterDuring video capture, at the start of a row, the current row value is compared with the VCRM register. A match generates an interrupt if enabled.

Video Memory Address Low RegisterThe VML register provides a pointer to the start of video capture memory and contains the lower 16-bits of the address.

Video Memory Address High RegisterThe VMH register provides a pointer to the start of video capture memory and contains the higher 16-bits of the address.

Video Memory Stride RegisterThe VMS register specifies the number of locations in video memory between successive array elements (stride) and is measured in bytes. Using stride enables better processing time.

LCD Row Match RegisterDuring LCD display DMA output, at the start of each row, the current row value is compared with the LRM register. A match generates an interrupt if enabled.

Table F-7. LCD Control Register

LCDCTRL: 0xA000.0012

15 14 13 12 11 10 9 8

0 0 0 0 0 0 0 0

R R R R R R R R

7 6 5 4 3 2 1 0

0 BL RST YN XN

R R R R R/2 R/W R/W R/W


LCD Video Memory Address Low RegisterThe LVML register provides a pointer to the start of video data for transfer to the LCD. This contains the lower 16-bits of the address.

LCD Video Memory Address High RegisterThe LVMH register provides a pointer to the start of video data for transfer to the LCD. This contains the higher 16-bits of the address.

LCD Video Memory Stride RegisterThe LVMS register specifies the number of bytes between the first pixels on adjacent rows in LCD video memory. Recommended to be either the length of a row (in bytes), or the next highest power of two.

LCD Graphics Memory Address Low RegisterThe LGML register provides a pointer to the start of graphics memory for output to the LCD and contains the lower 16-bits of the address.

LCD Graphics Memory Address High RegisterThe LGMH register provides a pointer to the start of graphics memory for output to the LCD and contains the higher 16-bits of the address.

LCD Graphics Memory Stride RegisterThe LGMS register specifies the number of bytes between the first pixels on adjacent rows in LCD graphics memory. Recommended to be either the length of a row (in bytes), or the next highest power of two.

Memory Port Number of Columns RegisterThe MPNC register specifies the number of columns (in pixels) of the memory port.

Memory Port Current Row RegisterThe MPR register identifies the selected row in the memory port.

Memory Port Current Column RegisterThe MPC register identifies the selected column in the memory port.

Memory Port Address Low RegisterThe MPML register contains the lower address bits of the memory region accessed by the memory port.

Memory Port Address High RegisterThe MPMH register contains the upper address bits of the memory region accessed by the memory port.

Memory Port Stride RegisterThe MPMS register specifies the number of bytes between the first pixels on adjacent rows in the memory port. Recommended to be either the length of a row (in bytes), or the next highest power of two.



Memory Port RegisterThe MPORT register allows sequential video/graphics memory plane access. A write (read) to this port generates a memory write (read) to the memory location calculated as follows:

Mem address = {MPH:MPL} + MPR x MPS + MPC.

After the transfer, if the MPC is not at the last pixel of the row, it automatically increments by 1. If the MPC is at the last pixel of the row, it sets to 0 and the MPR is incremented by MPS.

Memory Window RegisterUse the MEMPAGE register to select the active page (1 Kbyte page).

Loading a New Image to the FPGAThe FPGA can be re-imaged using any of the JTAG tool chains that support the Xilinx Spartan 3e XC3S100e. Two standard JTAG interfaces are provided with the FPGA expansion board: 2 x 7 with 2mm pitch and 1 x 6 with .1" pitch. Once connected, your JTAG scan chain should show an XC3S100e FPGA and an XCF01S PROM.

NOTE: Images loaded into the PROM must be set to use CCLK as the startup clock. Images loaded direct to the FPGA may use either CCLK or JTAG CLK.

Figure F-4. FPGA Boundary Scan

NOTE: The LM3S9B96 FPGA boots in JTAG mode, but transitions to serial mode once configured by the PROM. If your programmer is JTAG-only, you may need to clear the PROM and power cycle before you can directly program the FPGA via JTAG. This issue is rare since most tools support both modes. Check with your tool manufacturer for updates.


Installing the SoftwareTo install the software, do the following:

1. Plug the provided cable into J4 (on the right side of the board), taking care to ensure proper alignment and orientation. The silk-screened signal names should match, with the exception that 2.5 V corresponds to VDD. When correctly aligned, the “JTAG-SPI Full Speed" text should face in toward the FPGA.

Modifying the Default ImageThis section provides the descriptions for the default FPGA image blocks.

Default FPGA Image BlocksConfiguration Registers

The configuration registers are transparently mapped into the Stellaris microcontroller's memory, and are used to control the flow of the video streams. “Register Descriptions” on page 55 provides the detailed register maps. This is contained within the vregs.v file.

Memory WindowerThe memory windower allows the Stellaris microcontroller to work with a rectangular portion of a frame buffer. For example, this can be used to pull macro-cells for JPEG compression. This is contained within the mport.v file.

Memory ArbiterThe memory arbiter negotiates access to the external SRAM. The camera capture block is given highest priority. This is contained within the arb.v file.

Video CompositorThe video compositor assembles the final image from the video and graphics frame buffers, and passes it directly to the LCD Interface. It also converts the camera's VGA resolution to the LCD's QVGA resolution by either downsampling. This is contained within the vlcd.v file.

LCD I/FThe LCD interface connects to the Kitronix 3.5" LCD display using an 8-bit parallel mode. This is usually driven by the Video Compositor, but can also be driven directly by the EPI interface. This is contained within the vregs.v file.

Camera I/FThe camera interface block captures pixel data from the Omnivision OV7690's 8-bit digital video port and synchronization signals. This is contained within vcapture.v

Camera FIFOThe Camera FIFO serves two main purposes: reclocking and flow control. The camera and camera interface run in their own 12-/24-MHz clock domain, whereas the rest of the system runs off of the EPI clock or twice the EPI clock. The FIFO bridges these difference clock domains. The camera does not support any flow control functions; once triggered, it proceeds through an entire image. In order to prevent loss of pixels, this FIFO is 64 elements deep. This is contained within the vcapture.v and async_fifo_64.v files.



EPI Signal DescriptionsTable F-8 provides the EPI module’s signal descriptions.

Table F-8. EPI Signal Descriptions

EPI Signal Port FPGA Signal Direction Description

EPIOS[31] PG7 CLK In EPI Clock

EPIOS[30] PJ6 E_IRQn Out Interrupt Signal to Microcontrollera

a. Configure as Stellaris GPIO input with negative level sensitive interrupts. During power up/reset is used for PLL lock status.

EPIOS[29] PJ5 E_RD In EPI Read Strobe

EPIOS[28] PJ4 E_WR In EPI Write Strobe

EPIOS[27] PH7 E_RDY Out EPI Ready Signal

EPIOS[26] PH6 E_RSTn In FPGA Reset Signal b

b. Configure as Stellaris GPIO output.

EPIOS[25:16]PE3,PE2,PB4,

PB5,PD3,PD2,PJ3, PJ2,PJ1,PJ0

E_ADDR[10:1] In EPI Address Bus

EPIOS[15:0]

PF5,PG1,PG0,PF4, PH5,PH4,PE1,PE0, PH1,PH0,PC7,PC6, PC5,PC4,PH2,PH3

E_DATA[15:0] I/O EPI Data Bus


Component LocationsFigure F-5 shows the details of the component locations from the top view and Figure F-6 shows the details of the component locations from the bottom view.

Figure F-5. Component Placement Plot for Top



Figure F-6. Component Placement Plot for Bottom

SchematicsThis section shows the schematics for the LM3S9B96 FPGA memory expansion board:

EPI, LCD, Camera I/F on page 66

SRAM, Power, JTAG on page 67

1

1

2

2

3

3

4

4

5

5

6

6

D D

C C

B B

A A



B

Designer:

Drawn by:

Approved:

Drawing Title:

Page Title:

Size

Arnaldo Cruz

Arnaldo Cruz

* 0001

FPGA board for DK-EPI

EPI, LCD, Camera I/F

B

108 Wild Basin Rd.Suite 350Austin, TX 78746

TI AEC - Austin

Revision History

Revision

A 6/24/2009 Released for manufacturing.

Date Description

PG0/EPI13PG1/EPI14PH7/EPI27PJ0/EPI16PD3/EPI21PD2/EPI20PJ6/EPI30PJ5/EPI29PJ4/EPI28PJ3/EPI19PE3/EPI25PE2/EPI24PB4/EPI23PB5/EPI22PJ1/EPI17PH0/EPI6PH1/EPI7PH2/EPI1PH3/EPI0PH4/EPI10

1234567891011121314151617181920212223242526

272829303132333435363738394041424344454647484950

J1

DF12A-50DS



PE1/EPI9PE0/EPI8PH5/EPI11PH6/EPI26

EPI8EPI9

EPI11

EPI12

EPI13EPI14

EPI15

EPI16

EPI17EPI18

EPI19

EPI20EPI21

EPI22EPI23EPI24EPI25

EPI26

EPI0EPI1

EPI2EPI3EPI4EPI5

EPI6EPI7

EPI27

R1 2.80k

3.3V

R2 2.80k

I2CSCLI2CSDA

EPI I/F

EPI[31..0]

BA

NK

0

IO_L10N_0/HSWAP143 IO_L10P_0142 IO_L09N_0140 IO_L09P_0139 IO_L08N_0/VREF_0135 IO_L08P_0134 IO132 IO_L07N_0/GCLK11131 IO_L07P_0/GCLK10130 IO_L05N_0/GCLK7126 IO_L05P_0/GCLK6125 IO/VREF_0124 IO_L04N_0/GCLK5123 IO_L04P_0/GCLK4122 IO_L02N_0117 IO_L02P_0116 IO_L01N_0113 IO_L01P_0112U1A

XC3S100E-4TQG144C

BA

NK

1

IO_L10N_1/LDC2106 IO_L10P_1/LDC1105 IO_L09N_1/LDC0104 IO_L09P_1/HDC103 IO/A098 IO_L08N_1/A197 IO_L08P_1/A296 IO_L07N_1/A3/RHCLK794 IO_L07P_1/A4/RHCLK693 IO_L06N_1/A5/RHCLK592 IO_L06P_1/A6/RHCLK4/IRDY191 IO_L05N_1/A7/RHCLK3/TRDY188 IO_L05P_1/A8/RHCLK287 IO_L04N_1/A9/RHCLK186 IO_L04P_1/A10/RHCLK085 IO/VREF_183 IO_L03N_1/A1182 IO_L03P_1/A1281 IO_L02N_1/A1377 IO_L02P_1/A1476 IO_L01N_1/A1575 IO_L01P_1/A1674U1B

XC3S100E-4TQG144C

IP141 IP111 IP114 IP_L03P_0119 IP_L03N_0120 IP_L06P_0/GCLK8128 IP_L06N_0/GCLK9129 IP136

IP78 IP84 IP89 IP101 IP107 IP/VREF_195

IP38 IP41 IP_L03P_247 IP_L03N_2/VREF_248 IP_L06P_2/RDWR_B/GCLK056 IP_L06N_2/M2/GCLK157 IP69

IP6 IP/VREF_312 IP18 IP24 IP36

IP/VREF_266

IP/VREF_331

U1E

XC3S100E-4TQG144C

EPI10

EPI28EPI29EPI30

EPI31

EPI13EPI14

EPI16

EPI17

EPI19

EPI20EPI21

EPI22EPI23EPI24

EPI25

EPI0EPI1

EPI6EPI7

EPI27

EPI10

EPI28

EPI29EPI30

EPI8EPI9

EPI11

EPI12EPI15EPI18

EPI26

EPI2EPI3EPI4EPI5

EPI31

HREF

VSYNC

PXLCLK

PWDNXVCLK

I2CSCLI2CSDA

DVP0

DVP1

DVP[7..0]

2.8VD

SIOD

SIOC

XVCLKR

L_WRn

L_XN

L_YNL_D4L_D1

L_D0L_D3L_D6L_D7L_D2L_D5

L_RSTn

L_YP

L_XP

L_BLQ

LCD I/F

L_DC

L_BL

L_YN

L_XN

L_D0

L_D1

L_D2

L_D3

L_D4

L_D5

L_D6L_D7

L_RSTn

L_RDnL_DC

L_RDn

L_WRn

BA

NK

2

IO_L10N_2/CCLK 71IO_L10P_2/VS0/A17 70IO_L09N_2/VS1/A18 68IO_L09P_2/VS2/A19 67IO_L08N_2/DIN/D0 63IO_L08P_2/M0 62IO/M1 60IO_L07N_2/D1/GCLK3 59IO_L07P_2/D2/GCLK2 58IO_L05N_2/D3/GCLK15 54IO_L05P_2/D4/GCLK14 53IO/D5 52IO_L04N_2/D6/GCLK13 51IO_L04P_2/D7/GCLK12 50IO_L02N_2/MOSI/CSI_B 44IO_L02P_2/DOUT/BUSY 43IO_L01N_2/INIT_B 40IO_L01P_2/CSO_B 39U1C

XC3S100E-4TQG144C

X_CCLK

X_INIT_B

X_DAT

L_D0

L_D1

L_D2

L_D3

L_D4

L_D5

L_D6L_D7

L_XNL_YN

L_RSTn

L_RDn

L_DC

L_WRn

R2110K

3.3V

OE1

GND2 VDD 4

OUT 3U8

24.000MHz

R2310K

3.3V

3.3V

C48

0.1uF

CLK24M3.3V2.8VD

3.3V

C24

0.1uF

C23

0.1uF

R192.80k

R202.80k

2.8VD

5V

R6 1.0K

R4 1.0KR5 1.0K

SCL13

SDA14

GND1 VREF1L 2EN8

VREF2H 7

SCL2 6

SDA2 5

U7

PCA9306

R310

3.3V3.3V

PXLCLK

246810121416182022242628303234

13579

111315171921232527293133

J2

SMT Socket 2x17

1

23

Q3MMBT3904L_BL R24 2.80k

PWDNR

3.3V

C490.1uF

A01

A12

A23 SDA 5

GND4

SCL 6

WP7

VCC 8

1K - 128X8

U9

CAT24C01

Changed camera connector P1 to vertical connector.8/19/2009B

1B 3

2B 61A2

2A5

1OE1

2OE7

GND4 VCC 8

U10

SN74CB3T3306C50

0.1uF

2.8VD

XVCLKRPWDNR

1

M4

4

6

8

10

12

14

16

18

20

22

24

23

5

7

9

11

13

15

17

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21

23

M3

M2 M1

P1

FPC_Socket_24pin

2.8VA

DVP2

DVP3

DVP4

DVP5

DVP6

DVP7

HREFVSYNC

DVP7DVP6DVP5DVP4DVP0DVP3DVP1

DVP2

TP4TP5TP6TP7TP8

Board width increased by 110mils. Added test pads.

TP4TP5TP6TP7TP8

Released for manufacturing.

100 Mil Mask

FID340 Mil Pad

100 Mil Mask

FID140 Mil Pad

100 Mil Mask

FID240 Mil Pad

Fiducials

100 Mil Mask

FID640 Mil Pad

100 Mil Mask

FID440 Mil Pad

100 Mil Mask

FID540 Mil Pad

Top

Bottom

R22330

EPI, LCD, Camera I/F

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1

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2

3

3

4

4

5

5

6

6

D D

C C

B B

A A



B

Drawing Title:

Page Title:

SizeB

SRAM, Power, JTAG

FPGA board for DK-EPI

3.3V

DONE72

PROG_B1

TCK110

TDI144

TDO109

TMS108

U1F

XC3S100E-4TQG144C

VCCAUX 137

VCCAUX 65

VCCAUX 30

VCCAUX 102

VCCINT 80

VCCINT 9

VCCINT 45

VCCINT 115

VCCO_0138

VCCO_0121

VCCO_1100

VCCO_179

VCCO_242 VCCO_264 VCCO_249

VCCO_313 VCCO_328

U1G

XC3S100E-4TQG144C

GND 133GND 11GND 19GND 27GND 37GND 46

GND55 GND61 GND90 GND99 GND118 GND127 GND73U1H

XC3S100E-4TQG144C

2.8V

C74.7uFC9

4.7uF

5V

R12330

PWR

D1GREEN_LED

R13 10K

C100.1uF

3.3V

MA0MA1MA2MA3MA4MA5MA6MA7MA8MA9MA10MA11MA12MA13MA14MA15MA16

C50.1uF

C60.1uF


MA17MA18MA19

MCS_n

MWE_nMOE_n

GND4 VCC 7

1OE1 1LE48

2D235

2D333

2D432

2D530

2D629

2D727

2D826

2D136 2Q1 13

2Q2 14

2Q3 16

2Q4 17

2Q5 19

2Q6 20

2Q7 22

2Q8 23

1D147

1D246

1D344

1D443

1D541

1D640

1D738

1D837

1Q1 2

1Q2 3

1Q3 5

1Q4 6

1Q5 8

1Q6 9

1Q7 11

1Q8 12

2OE24 2LE25

GND45

GND10

GND39

GND15

GND34

GND21

GND28

VCC 42

VCC 18

VCC 31

U3

74LVC16373




3.3V

C1

0.1uF

C2

0.1uF

C3

0.1uF

C4

0.1uF

MA[20..0]

MAD[7..0]

3.3V

1.2V

2.5V

A03 D0 9

A14

A25

A36

A47

A516

A617

A718

A819

A920

A1026

A1127

A1228

D1 10

D2 13

D3 14

D4 31

D5 32

D6 35

D7 36

A1329

A1430

A1538

A1639

A1740

A1841

NC 1

NC 2

NC 21

NC 22

NC 23

NC 24

NC 43

NC 44

WE15 OE37 CE8

VSS12

VSS34 VDD 11

VDD 33

A1925

NC_A2042

1Mx8

U4

IS61WV10248

MA20

ALE1ALE2

MCS_n

MWE_n

MOE_n

BA

NK

3

IO 10IO 29IO_L10N_3 35IO_L10P_3 34IO_L09N_3 33IO_L09P_3 32IO_L08N_3 26IO_L08P_3 25IO_L07N_3/LHCLK7 23IO_L07P_3/LHCLK6 22IO_L06N_3/LHCLK5 21IO_L06P_3/LHCLK4/TRDY2 20IO_L05N_3/LHCLK3/IRDY2 17IO_L05P_3/LHCLK2 16IO_L04N_3/LHCLK1 15IO_L04P_3/LHCLK0 14IO_L03N_3 8IO_L03P_3 7IO_L02N_3/VREF_3 5IO_L02P_3 4IO_L01N_3 3IO_L01P_3 2U1D

XC3S100E-4TQG144C

X_CCLK

X_INIT_B

X_DAT

R9330

2.5V

R810K

2.5V

DO 1CLK3

OE/RESET8

TDO17

VCCINT 18

1Mbit

CE10

CF7

CEO 13

TMS5

VCCO 19

VCCJ 20GND11

NC 2

TCK6

NC 9

TDI4

NC 12

NC 14

NC 15

NC 16

U2

XCF01S

R1110

R710K

3.3V

5V

C2210uF

C14

0.1uF

C13

0.1uF

R1861.9K

R1636.5KR17

15.4K

VIN1 VOUT 5

SHDN3

GND2 NR 4

U6

TPS79228C80.1uF

1

23

Q1FDN338P

5V

1.2V

1

23

Q2FDN338P

5V

3.3V

C16 10pF2.5V

MAD1MAD2MAD3

MAD4MAD5MAD6MAD7

MA16MA17MA18

MA19

MA20

MAD0

L1 6.8uH

L2 6.8uH

R100.033

R140.033

C191500pF

C201500pF

C211500pF

5V

C330.1uF

C340.1uF

C350.1uF

C360.1uF

C370.1uF

C380.1uF

C390.1uF

C400.1uF

C250.1uF

C260.1uF

C270.1uF

C290.1uF

C300.1uF

C310.1uF

C4610uF

R15 61.9K

3.3V

GND6

VIN113

VIN28

VIN320

EN117

EN24

EN33

SS116

SS25

SS319

IS1 12

IS2 9

SW1 14

SW2 7

FB1 11

FB2 10

FB3 2VOUT3 1

GND15

GNDPAD

AGND 18

U5

TPS75003

L3 3.3uH

L4 3.3uH

2.8VA

2.8VD

C430.1uF

C440.1uF

C450.1uF

1 23 4

SW1

Tactile Switch

D2SS22

D3SS22

C4210uF

C410.1uF

C280.1uF

C320.1uF

C4710uF

+ C1168uF

+ C1268uF

+ C1868uF

L1N

L2N

C15

0.1uF

L_BL

1

5V

J5

HDR-1X1

TP1

TP2TP3

12345678910

12131411

Xilinx JTAG

J3

2X7 HDR-SHRD

123456

JTAG

J4

HDR-1X6

2.5V

C17

0.1uF

TDITMS

TDOTCK

TP1

TP2TP3

SRAM, Power, JTAG


Stellaris® LM3S9B96 EM2 Expansion BoardThis document describes the Stellaris® LM3S9B96 EM2 Expansion Board (DK-LM3S9B96-EM2) for the DK-LM3S9B96 development board. The EM2 expansion board provides a transition between the Stellaris External Peripheral Interface (EPI) connector and the RF Evaluation Module (EM) connector. The DK-LM3S9B96-EM2 enables wireless application development using Low Power RF (LPRF) and RF ID evaluation modules on the Stellaris DK-LM3S9B96 platform.

Figure G-1. EM2 Expansion Board

FeaturesThe DK-LM3S9B96-EM2 expansion board has the following features:

2 sets of EM connectors to support up to 2 RF evaluation modules

1 kilobit of I2C memory for storing configuration data and EM2 expansion board detection

EM digital and analog audio signal headers

EM MOD1 SDIO connection headers

32 Khz oscillator for slow clock source to primary EM2 expansion board connector

InstallationTo install the EM2 expansion board on the DK-LM3S9B96 development board, do the following:

1. On the DK-LM3S9B96 board (shown in Figure G-2 on page 70), remove any installed board on EPI connector J2 (A).

A P P E N D I X G


2. On the DK-LM3S9B96 board (shown in Figure G-2), confirm that shunt jumpers on JP16-JP31 (B) are installed to enable the LCD touch screen. JP39 (C), the leftmost jumper indicated, should remain uninstalled.

Figure G-2. Removing EPI Board from DK-LM3S9B96 Development Board

3. Place the EM2 expansion board on top of the DK-LM3S9B96 board while aligning the male EPI expansion connector on the bottom side of the EM2 expansion board with the female EPI expansion connector on the DK-LM3S9B96 development board (J2).

(A) Remove board

(B) Confirm shunt jumpers(JP16-JP31) installed

(C) Leave JP39 uninstalled



Figure G-3. EM2 Expansion Board

4. Press firmly downward until the board snaps in place.

Figure G-4. Assembled DK-LM3S9B96 Development Board with EM2 Expansion Board

Male EPI expansion connector

Bottom side of EM2 module

EM2 Expansion Board


Installation of EM Modules onto the EM2 Expansion Board

The EM2 expansion board has a primary EM header (MOD1) and a secondary EM header (MOD2) as indicated on the silk screen (see Figure G-5). The secondary EM header is rotated 180 degrees from the primary EM header.

There are many types of EM modules that can be installed onto the EM2 expansion board. See the README First document for the EM module you are installing to determine if there is a specific requirement or recommendation for which header the EM module should be installed in. If installing a single module and if there is no specific requirement or recommendation in the module’s README First document indicating which slot it should be installed in, install the single module into the primary EM header (MOD1).

To install an EM module into the primary module EM slot of the EM2 expansion board, do the following:

1. Attach any supplied antennas to the EM module.

2. Locate the two 20-pin sockets on the back side of the EM module. Note the tab on the side of each of the 20-pin sockets. This tab denotes pin 1 and aligns with the 20-pin headers on the EM2 expansion board that contain slots near pin 1 for the tab. See Figure G-5 for details.

Figure G-5. Connecting an EM Module to the EM2 Expansion Board

3. Align the two 20-pin sockets on the EM module over the 20-pin headers on the EM2 expansion board that are within the primary EM silkscreen.

20-pin sockets

Primary EM header (MOD1) - 20-pin headers

Bottom side of EM moduleTop side of EM2 expansion board

on EM module

Pin 1 tab

Pin 1 slot

Secondary EM header (MOD2) - 20-pin headers



4. Use a slight pressure to seat the EM module firmly on the EM2 expansion board. See Figure G-6 on page 73 for fully assembled DK-LM3S9B96 board with EM2 expansion board and wireless EM module.

Figure G-6. Fully Assembled DK-LM3S9B96 Board with EM2 Expansion Board and Wireless EM Module

Follow these same steps for installing a second module into the secondary EM header location which will be oriented 180 degrees from the primary EM header location.

NOTE: The secondary EM header should only be used when two EM modules are installed in the system or when specifically indicated in the EM module’s README First document.

EM2 expansion board

EM module

Antenna for EM module

DK-LM3S9B96 board


Hardware DescriptionThe block diagram for the EM2 expansion board is shown in Figure G-7.

Figure G-7. EM2 Expansion Board Block Diagram

Primary EM HeaderThe primary EM header should always be used when only one EM module is installed unless otherwise indicated in the README First document for the EM module you are installing.

The primary EM header connects three buses to the EPI connector that are also shared with the secondary EM header. These buses are I2C, UART1, and SPI.

NOTE: The primary and secondary EM headers have a unique SPI chip select signal, but share the data and clock signals.

The primary EM header contains four GPIO connections to the EPI connector. These GPIOs can be used as inputs or outputs depending upon the EM module installed. In addition, four unique GPIOs are provided to each EM header.

EPI Connector

UART1

MOD1 GPIO

MOD2 GPIO

MOD1 SHUTDOWN

MOD2 SHUTDOWN

SPIMOD1 SPI_CS

MOD2 SPI_CS

MOD_I2C

AD_I2C

+3.3 V

CAT24C01EEPROM

32 KHZ OSC

/4

/4

/4

SDIO Header

I2S Audio

Header

AnalogAudio

Header

I2S Audio

Header

AnalogAudio

Header

+3.3 VI2CUARTSPI

SHUTDOWNGPIO

+3.3 VI2CUARTSPI

SHUTDOWNGPIO

SECONDARYEM

HEADER(MOD2)

PRIMARYEM

HEADER(MOD1)



The primary EM header contains one GPIO connection used to shut down and/or reset the EM module. The actual function depends on the EM module installed. The MODx_nSHUTD signal is pulled up to 3.3 V on the EM2 adapter. Each header has its own MODx_nSHUTD signal.

The primary EM header contains additional features not found on the secondary EM header including a 32-KHz oscillator input and a header for a 4-bit SDIO module. These features are not currently used by the EM modules available today but are available for future expansion.

Secondary EM HeaderThe secondary EM header should only be used when two EM modules are installed in the system or when specifically indicated in the EM module’s README First document.

CAT24C01 EEPROMThe EM2 board contains a 1-Kbit I2C EEPROM which connects to an I2C bus separate from the one connected to the EM headers. This EEPROM contains data that is used by the software drivers to auto detect that the EM2 expansion board is installed in the system. The EEPROM is normally write-protected. To make the EEPROM writeable, install a jumper between pins 2 and 3 of JPS1.

I2S HeaderThe primary EM header and the secondary EM header each contain connections to separate 6-pin I2S headers J2 and J4 respectively. These headers connect to the EM modules only and are not connected to the EPI header which connects to the DK-LM3S9B96. See the EM module’s documentation for more information on the functionality of this header.

Analog Audio HeaderThe primary EM header and the secondary EM header each contain connections to separate 4-pin analog audio headers J3 and J5 respectively. These headers connect to the EM modules only and are not connected to the EPI header which connects to the DK-LM3S9B96. See the EM module’s documentation for more information on the functionality of this header.

SDIO HeaderThe primary EM header contains a connection to 8-pin SDIO header J1. This header connects to the EM modules only and is not connected to the EPI header which connects to the DK-LM3S9B96. See the EM module’s documentation for more information on the functionality of this header.

EPI Signal DescriptionsFigure G-1 provides the EPI module's signal descriptions.

Table G-1. EPI Signal Descriptions

LM3S9B96 Function Port EM2 Signal Direction Description

PE1 PE1 SPI_CS1 Out SPI Chip Select for Primary EM Module

PJ4 PJ4 SPI_CS2 Out SPI Chip Select for Secondary EM Module

SSI1CLK PH4 SPI_CLK Out SPI Clock

SSI1Rx PF4 SPI_MISO In SPI Receive


SSI1TX PF5 SPI_MOSI Out SPI Transmit

U1RX PC6 MOD_UART_TX In Modulator UART TX, LM3S9B96 RX

U1TX PC7 MOD_UART_RX Out Modulator UART RX, LM3S9B96 TX

U1RTS PJ6 MOD_UART_CTS Out Modulator UART CTS, LM3S9B96 RTS

U1CTS PJ3 MOD_UART_RTS In Modulator UART RTS, LM3S9B96 CTS

I2C1SCL PJ0 MOD_I2C_SCL Out I2C Bus to EM Modules

I2C1SDA PJ1 MOD_I2C_SDA I/O I2C Bus to EM Modules

I2C0SCL PB2 AD_I2C_SCL0 Out I2C Bus to Auto Discovery EEPROM

I2C0SDA PB3 AD_I2C_SDA0 I/O I2C Bus to Auto Discovery EEPROM

PC4 PC4 MOD1_nSHUTD Out Shutdown/Reset Signal for Primary EM Module

PH5 PH5 MOD2_nSHUTD Out Shutdown/Reset Signal for Secondary EM Module

PH0 PH0 MOD1_GPIO0 I/O GPIO for Primary EM Module




PG0 PG0 MOD2_GPIO0 I/O GPIO for Secondary EM Module



PJ2 PJ2 MOD2_GPIO3 I/O GPIO for Secondary EM Module

Table G-1. EPI Signal Descriptions (Continued)

LM3S9B96 Function Port EM2 Signal Direction Description



Component LocationsFigure G-8 shows the details of the component locations.

Figure G-8. Component Placement Plot for Top and Bottom

SchematicsThis section shows the schematics for the EM2 expansion board:

EM2 Expansion Board on page 78

Top Bottom

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Primary EM header

Secondary EM header

Stellaris LM3S9B96 EPI header

32KHz ClockINSTALL RESISTOR R7 WHEN 2ndMODULE NEEDS SLOW CLK.

I2C chip to enable adapterboard auto discovery.

32KHz clock for BT boardsMOD1_SDIO_D0MOD_UART_CTSMOD1_SDIO_D1MOD_SLOWCLKMOD1_SDIO_D2

MOD1_SDIO_D3MOD_UART_RX

MOD_UART_TXMOD1_GPIO0

MOD_I2C_SDAMOD1_GPIO1MOD_I2C_SCL

MOD1_SDIO_CLKSPI_CLKMOD1_SDIO_CMDSPI_MOSI

SPI_MISO

MOD1_AUD_DATA_IN

MOD1_AUD_FSYNC

MOD1_GPIO2

MOD1_nSHUTD

MOD1_AUD_CLK

MOD1_GPIO3MOD1_nSHUTD

MOD1_AUD_ANA_L

MOD1_AUD_ANA_R

MOD1_AUD_DATA_OUT

MOD_UART_RTS

SPI_CS1

MOD1_AUD_DATA_OUTMOD1_AUD_DATA_INMOD1_AUD_FSYNCMOD1_AUD_CLK

MOD1_AUD_ANA_RMOD1_AUD_ANA_L

MOD_UART_CTS

MOD2_AUD_ANA_RMOD2_AUD_ANA_L

MOD_UART_RX

MOD_UART_TX

MOD_UART_RTS

MOD2_GPIO0 MOD2_AUD_DATA_IN

MOD2_AUD_FSYNC

MOD2_GPIO2

MOD2_nSHUTD

MOD2_AUD_CLK

MOD2_GPIO3

MOD_I2C_SDA

MOD2_nSHUTD

MOD2_GPIO1

MOD2_AUD_ANA_L

MOD2_AUD_DATA_OUT

MOD_I2C_SCL

MOD2_AUD_DATA_OUT

SPI_CS2

MOD2_AUD_ANA_R

SPI_CLK

MOD2_AUD_DATA_INMOD2_AUD_FSYNCMOD2_AUD_CLK

SPI_MOSI

SPI_MISO

MOD1_SDIO_CMDMOD1_SDIO_CLKMOD1_SDIO_D3MOD1_SDIO_D2MOD1_SDIO_D1MOD1_SDIO_D0

EPI13EPI14

EPI16

EPI30

EPI17EPI06

EPI01EPI00EPI10

EPI07

EPI04EPI05

EPI31

EPI15EPI12

EPI18

EPI09

EPI02

SPI_CS1

SPI_CLK

MOD1_GPIO0MOD_I2C_SDA

MOD1_GPIO1MOD1_GPIO2MOD1_GPIO3

MOD_UART_CTS

MOD2_GPIO0MOD2_GPIO1

SPI_MISOSPI_MOSI

MOD2_GPIO2MOD2_GPIO3

MOD1_nSHUTD

EPI19EPI28

MOD_UART_RTS

MOD2_nSHUTD

MOD_UART_TXMOD_UART_RX SEC_MOD_SCLK

WP_I2C

AD_I2C_SDA0AD_I2C_SCL0

MOD_SLOWCLK

SEC_MOD_SCLK

SPI_CS2

EPI11

PB2PB3

MOD_I2C_SCLAD_I2C_SCL0AD_I2C_SDA0

PB2PB3

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

Title

Size Document Number Rev

Date: Sheet of

DK-LM3S9B96_EM2DK-LM3S9B96_EM2DK-LM3S9B96_EM2DK-LM3S9B96_EM2 C

LM3S9B96 EM2 AdapterLM3S9B96 EM2 AdapterLM3S9B96 EM2 AdapterLM3S9B96 EM2 AdapterB

1 1Monday, July 12, 2010

Title


Date: Sheet of




Title


Date: Sheet of




R152.7KR152.7K

C41uFC41uF

JPS1I2C_WP

JPS1I2C_WP

1 32

J4

Header_1x6_100_430L

RFMOD2_I2SJ4

Header_1x6_100_430L

RFMOD2_I2S123456

J6

RECT_DF12A-50DS

LM3S9B96 EPI HeaderJ6

RECT_DF12A-50DS

LM3S9B96 EPI Header

123456789

10111213141516171819202122232425

50494847464544434241403938373635343332313029282726

R7 0

DNI

R7 0

DNI

R8 0R8 0

CC-P2CC-P1

MOD2

HPA_MB_MODULE_ASSY_RF

RF_MODULE-PORT_1A

TF

M-1

10-0

2-S

-D-K

-ATF

M-110-02-S

-D-K

-A

CC-P2CC-P1

MOD2


RF_MODULE-PORT_1A

TF

M-1

10-0

2-S

-D-K

-ATF

M-110-02-S

-D-K

-A

B7B7

B8B8

B9B9

B10B10

B11B11

B12B12

B13B13

B14B14

B15B15

B16B16

B17B17

B18B18

B19B19

B20B20

B1B1

B2B2

B3B3

B4B4

B5B5

B6B6

D1D1

D2D2

D3D3

D4D4

D5D5

D6D6

D7D7

D8D8

D9D9

D10D10

D11D11

D12D12

D13D13

D14D14

D15D15

D16D16

D17D17

D18D18

D19D19

D20D20

R132.7KR132.7K

R2

27

R2

27

123456789

10111213141516

R142.7KR142.7KU2

CAT24C01

U2

CAT24C01

A01

A12

A23

VSS4

SDA5SCL6WP7VCC8

J1

Header_1x8_100_430L

RFMOD1_SDIOJ1

Header_1x8_100_430L

RFMOD1_SDIO12345678

R6100KR6100K

XJ1

Shunt_100

XJ1

Shunt_100

R1110KR1110K

C210000pF

DNI

C210000pF

DNI

C310nFC310nF

C51uFC51uF

J2

Header_1x6_100_430L

RFMOD1_I2SJ2

Header_1x6_100_430L

RFMOD1_I2S123456

R1

27

R1

27

123456789

10111213141516

CC-P2CC-P1

MOD1


RF_MODULE-PORT_1A

TF

M-1

10-0

2-S

-D-K

-ATF

M-110-02-S

-D-K

-A

CC-P2CC-P1

MOD1


RF_MODULE-PORT_1A

TF

M-1

10-0

2-S

-D-K

-ATF

M-110-02-S

-D-K

-A

B7B7

B8B8

B9B9

B10B10

B11B11

B12B12

B13B13

B14B14

B15B15

B16B16

B17B17

B18B18

B19B19

B20B20

B1B1

B2B2

B3B3

B4B4

B5B5

B6B6

D1D1

D2D2

D3D3

D4D4

D5D5

D6D6

D7D7

D8D8

D9D9

D10D10

D11D11

D12D12

D13D13

D14D14

D15D15

D16D16

D17D17

D18D18

D19D19

D20D20

R3

27

R3

27

123456789

10111213141516

J3

Header_1x4_100_430L

RFMOD1_ANALOGJ3

Header_1x4_100_430L

RFMOD1_ANALOG1234

R5100KR5100K

R122.7KR122.7K

OSC1

MC_32.768kHz

OSC1

MC_32.768kHz

VCC4

OUT1

GND2

EN3

J5

Header_1x4_100_430L

RFMOD2_ANALOGJ5

Header_1x4_100_430L

RFMOD2_ANALOG1234

EM2 Expansion Board


ReferencesIn addition to this document, the following references are included on the Stellaris DK-LM3S9B96 Development Kit Documentation and Software CD and are also available for download at www.ti.com/stellaris:

Stellaris LM3S9B96 Microcontroller Data SheetKitronix LCD Data Sheet

StellarisWare Driver LibraryStellarisWare Driver Library User’s Manual, publication number SW-DRL-UG

Additional references include:FT2232D Dual USB/UART FIFO IC Data sheet, version 0.91, 2006, Future Technology Devices International Ltd.Texas Instruments TLV320AIC23BPM Audio CODEC Data Sheet

Information on development tool being used:

– RealView MDK web site, www.keil.com/arm/rvmdkkit.asp

– IAR Embedded Workbench web site, www.iar.com

– Code Sourcery GCC development tools web site,www.codesourcery.com/gnu_toolchains/arm

– Code Red Technologies development tools web site, www.code-red-tech.com

– Texas Instruments’ Code Composer Studio™ IDE web site, www.ti.com/ccs

A P P E N D I X H

http://www.keil.com/arm/rvmdkkit.asp

http://www.iar.com

http://www.codesourcery.com/gnu_toolchains/arm/

http://www.code-red-tech.com/

http://www.code-red-tech.com/

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the latest relevant information before placing orders and should verify that such information is current and complete. All products aresold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standardwarranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except wheremandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products andapplications using TI components. To minimize the risks associated with customer products and applications, customers should provideadequate design and operating safeguards.

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http://www.dlp.com

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http://dsp.ti.com

http://www.ti.com/industrial

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http://logic.ti.com

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http://power.ti.com

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http://microcontroller.ti.com

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http://www.ti.com/wireless-apps

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Stellaris LM3S9B96 Development Kit User's Manual (Rev. G) · 2011-08-06 · Block Diagram ......

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Transcript of Stellaris LM3S9B96 Development Kit User's Manual (Rev. G) · 2011-08-06 · Block Diagram ......