Status Report 2010.8.6 Atsushi Nukariya. FPGA training course ・ I solved 15 problems which are...
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Transcript of Status Report 2010.8.6 Atsushi Nukariya. FPGA training course ・ I solved 15 problems which are...
FPGA training course
・ I solved 15 problems which are proposed by Uchida-san.
・ I used above circuit board.
FPGA
Download connector
Power DIP switch
NIM output
NIM inputDAC
ADC
LED
Mode selection
Tool
・ I learned how to use Xilinx ISE Design Suite 11 which is circuit design software, and Veritak which is Verilog HDL simulator.
・ I solved 15 problems using Xilinx ISE Design Suite 11.
Problem
1. Display on LED the value of DIP switch.
2. Make two input XOR (eXclusive OR) without using operator xor.
3. Detect the state that the input value is 5. ( This means DIP switch is 00000101. )
Problem
4. Detect the state that the input value is above 0.
5. Detect the state that the input value is above 1.
6. Make two input MUX (MUltipleXer).
10. Make 4bit circuit of parallel to serial conversion.
Problem
11. Make circuit of sample and hold.
Problem
12. Make 6bit sexagesimal number counter.
13. Make 6bit sexagesimal number counter with enable signal.
Stopwatch –Specification-
・ Display minutes on two LEDs.
・ Display seconds on six LEDs.
・ Start when DIP switch No.1 switch on.
・ Stop when DIP switch No.2 switch on.
Stopwatch –State machine-
Independence
Hold
Clear
Count
DIP switch 1 on
DIP switch 2 on
DIP switch 1 offDIP switch 2 off
DIP switch 1 on
DIP switch 1 offDIP switch 2 off
Stopwatch –Completion(?)-
・ I finished making stopwatch. However it is necessary to output the register used for the state machine somewhere. ( For example, NIM output. )
→ Uchida-san thought that description of state machine is not suitable for Xilinx ISE Design Suite 11.