Status of the EKV3.0 MOS Transistor ModelA. Bazigos -- MOS-AK Workshop, September 22, 2006 20...

MOS AK

Status of the EKV3.0 MOS Transistor Model

Matthias Bucher, Technical University of Crete

e-mail: [email protected]

MOS-AK/ESSDERC/ESSCIRC WorkshopCompact Modelling for Emerging Technologies

Friday, 22 September 2006Montreux Switzerland

Antonios Bazigos,National Technical University of Athens

François Krummenacher,École Polytechnique Fédérale de Lausanne

2A. Bazigos -- MOS-AK Workshop, September 22, 2006MOS AK

Presentation Outline

�About EKV3�Model Code in Verilog-A�Physical Effects & Parameters

� Parameter Extraction Basic Methodology�Modelling Results�Summary


About EKV3

� A Design-Oriented, Charge-Based Model � Moderate and Weak Inversion� Special Attention to Analog/RF IC Design Requirements

� High Frequency Operation, Noise� All Pertinent Effects to 45nm CMOS

� Scaling over Technologies, Geometry, Temperature, Bias� Validated on Various CMOS Technologies.

� TOSHIBA, Infineon, Cypress, Atmel.� Used for Commercial IC Design.


EKV: Charge Based Modelling

Inversion Charge

Drain Current

Transconductances

Transconductance-to-Current Ratio

Capacitances & Charges

Short-Channel Thermal Noise

Induced Gate Noise……

2 2s s d di q q q q= + − −

1

1/ 2 1/ 4m

d sat

g

i i=

+ +

ms s

md d

s dm

g q

g q

q qg

n

∝∝

−∝

1,

O O

L L

D i S i

XXY

Y

x xQ W q dx Q W q dx

L LQ

CV

−∝ ∝

∂= ±∂

∫ ∫

( ); ,i i S s dq q q q= Ψ


EKV3 in Verilog-A

� The Verilog-A Code of EKV3.0� Hierarchical Structure

� 18 files� one main file� many smaller� In Total: 83KB

� Compatible with (at least) ELDO, ADS, SPECTRE, ADMS, …

� Used as the Reference Code for all Model Implementations

� ADMS provides “standard” C-code Various Simulators.

ekv3.va“include statements”

ekv3_extrinsic.va

ekv3_overlap.va

ekv3_gate_current.va

ekv3_noise.va

…


EKV3 and ADMS

� EKV3 Verilog-A Code Tested with ADMS (v2.1)� Current version: ADMS v2.2.4

� Tested with XML Interface for SPICE3� Different XML Interfaces for Different Simulators


EKV3 “Design Kit” in ADS

� Tiburon: A Verilog-A Compiler in ADS� An EKV3 “Design Kit” for ADS has been developed

� Design Kit contains 8 Elements, only MOSFET� QS / NQS� NMOS / PMOS� MODEL-CARD / INSTANCE

� 120nm CMOS Design Kit has been used to Design� Base-Band Elements (OP-AMPs) � LNA


EKV3 in ELDO (C-code)

� In ELDO a Hand-Written C-code Version of the Model exists

� Verilog-A Code: Simpler but less Efficient� Not always Efficiently handled by the Simulators

� Generally “Verilog-A + ADMS” and C-code have the same Functionality


Phenomena covered by EKV3.0 --Associated Parameters 1/2

[Channel Segmentation]NQS

[Appropriate Scaling of RG, RSUBswith W, L and NF]

RF ModelExternal Sub-Circuit

IBA, IBB, IBNImpact Ionization Current

KG, XB, UBGate Current (IGS, IGD, IGB)

LOV, GAMMAOV(NOV), VFBOVBias-Dependent Overlap Capacitances

KP(U0), E0, E1, ETA

ZC, THC

Mobility (Reduction due to Vertical Field Effect) Surface Roughness-, Phonon-, Coulomb Scattering

COX(TOX), PHIF, GAMMA(NSUB), VTO(VFB), GAMMAG(NGATE)

Physical Modelling of Charges Including Accumulation RegionPolysilicon Depletion, Quantum Mechanical Effects

Modelled effect Related Parameters / Comments


Phenomena covered by EKV3.0 --Associated Parameters 2/2

WEDGE, DGAMMAEDGE, DPHIEDGEEdge Conduction

AF, KFNoiseFlicker Noise, Short-Channel Thermal Noise,Induced Gate and Substrate Noise

LETA0Halo/Pocket implant effects

Various ParametersTemperature Effects

Various Parameters (DL, WQLR, … )Geometrical Effects, Width scaling

LETA, {LETA2}, WETASource and Drain Charge Sharing

LR, QLR, NLRReverse Short Channel Effect

WR, QWR, NWRInverse Narrow Width Effect

ETAD, SIGMADDrain Induced Barrier Lowering

UCRIT(VSAT), LAMBDA,

DELTA

Longitudinal Field EffectVelocity Saturation, Channel Length Modulation

TOTAL

Modelled effect Related Parameters / Comments


Basic Parameter Extraction Methodology

CGG vs VG:COX, VTO,

GAMMA, PHIF, GAMMAG

CGG vs VG:COX, VTO,

GAMMA, PHIF, GAMMAG

gm vs VG (lin):DL, RSX

(fixing RSCE for correct VTO)gm vs VG (lin):DL, RSX(fixing RSCE for correct VTO)ID vs VG (lin):LETA, [ETAD]ID vs VG (lin):LETA, [ETAD]

VTO vs L:LR, QLR, NLR

{RSCE},[LETA, LETA2,

ETAD]

VTO vs L:LR, QLR, NLR

{RSCE},[LETA, LETA2,

ETAD]

CGG vs VG:LOV, GAMMAOV,[VFBOV], DLC

CGG vs VG:LOV, GAMMAOV,[VFBOV], DLC

Wide Long CVWide Long CV

Wide Long IVWide Long IV

Wide Short IVWide Short IV Wide All Lengths IV

Wide All Lengths IV Wide Short CV

Wide Short CV

Narrow channel similar procedureNarrow channel

similar procedure

Narrow shortcombined effects

[fine tuning]

Narrow shortcombined effects

[fine tuning]

END

gm vs VG (lin):KP, E0, E1,

[ETA]

gm vs VG (lin):KP, E0, E1,

[ETA]

Width scaling:All lengths w.r.t.

width

Width scaling:All lengths w.r.t.

width

ID vs VG (sat):ETAD, [LETA]

ID vs VG (sat):ETAD, [LETA]

Id, gds vs VD [strong inversion]:

UCRIT,LAMBDA, DELTA

[weak inversion]:ETAD

Id, gds vs VD [strong inversion]:

UCRIT,LAMBDA, DELTA

[weak inversion]:ETAD

Temperature analysis

Temperature analysis


Short-Channel Characteristics

� Correct Weak & Moderate Inversion Behaviour� Smoothness and Correct Asymptotic Behaviour� Correct Weak Inversion Slope and DIBL Modeling

� Transconductance-to-Current Ratio vs. Drain Current (log. axis)

L=70nm VD=1.5V

0.0E+00

1.0E-01

2.0E-01

3.0E-01

4.0E-01

5.0E-01

6.0E-01

7.0E-01

8.0E-01

1.00E-08 1.00E-07 1.00E-06 1.00E-05 1.00E-04 1.00E-03 1.00E-02

ID [A]

GM

*UT

/ID [

-]

measuredEKV3.0

L=70nm VD=1.5V

1.0E-10

1.0E-09

1.0E-08

1.0E-07

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

VG [V]

ID [

A]

measuredEKV3.0

L = 70nm

weak

moderate

strong


Short-Channel Output Characteristics

L=70nm VB=0V

0.0E+00

1.0E-03

2.0E-03

3.0E-03

4.0E-03

5.0E-03

6.0E-03

7.0E-03

8.0E-03

9.0E-03

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

VD [V]

ID [

A]

measuredEKV3.0

L=70nm VB=-1V

0.0E+00

1.0E-03

2.0E-03

3.0E-03

4.0E-03

5.0E-03

6.0E-03

7.0E-03

8.0E-03

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

VD [V]

ID [

A]

measuredEKV3.0

L=70nm VB=0V

1.0E-04

1.0E-03

1.0E-02

1.0E-01

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

VD [V]

gds

[A

/V]

measured

EKV3.0

L=70nm VB=-1V

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

VD [V]

gd

s [A

/V]

measuredEKV3.0

L = 70nm


NQS Model @ RF [Re(Y21), Im(Y21)]

Multifinger Devices @ Various VG Values, Saturation

NMOS Lg=80nm NMOS Lg=2um


Edge Conduction Effect on ID and gm/ID

NMOS 10um/10um

0.0001

0.001

0.01

0.1

1

10

100

-20 0 20 40 60 80 100vgb[-]

id[-

]

NMOS 10um / 80nm VD = 1V

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100

id[-]

gm

/id[-

]

NMOS 10um/10um VD=1V

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0.0001 0.001 0.01 0.1 1 10 100

id[-]

gm

/id[-

]

NMOS 10um / 80nm VD=1V

0.000001

0.00001

0.0001

0.001

0.01

0.1

1

10

100

-20 0 20 40 60 80 100

vgb[-]

id[-

]

L=10um L=80nm


Gate Current & Edge Conduction

� Gate Current is also affected by Edge Conduction� EKV3.0 gives reasonable fits to ID, gm/ID, IG even in

case of presence of Edge Conduction Effect� Edge Conduction affects gm/id dramatically in Weak-

Moderate Inversion

NMOS 10um / 10um VD = 50mV

1.0E-14

1.0E-13

1.0E-12

1.0E-11

1.0E-10

1.0E-9

1.0E-8

1.0E-7

1.0E-6

-0.5 0 0.5 1 1.5 2 2.5

VGB[V]

IG [

A]

NMOS 10um / 80nm VD = 50mV

1.0E-14

1.0E-13

1.0E-12

1.0E-11

1.0E-10

1.0E-9

1.0E-8

-0.5 0 0.5 1 1.5 2 2.5

VGB[V]

IG[A

]

L=10um L=80nm


Temperature Scaling

� ID – VG and ID (gds) - VD vs. Temperature

L = 150nm


EKV3 and Industries

� TOSHIBA Semiconductors� 140nm� 110nm� 80nm

� Infineon Technologies� 120nm� 90nm� 65nm

� Cypress Semiconductors� 150nm

� Atmel Corporation� 350nm� 130nm

� AustriaMicroSystems� 350nm� 180nm

� XFAB� 350nm

� Various Co-Operations� Tektronix


Developments underway (EKV3.1)

� Vertical Non-Uniform Doping.� Accounting for Carrier Heating/Velocity Saturation in

Induced Gate Noise.� A. S. Roy and C. C. Enz, WCM 2006

� Mobility Effect to Improve Flexibility for Short-Channel Back-Bias

� Output Conductance Effects in Long Channel Halo/Pocket Implanted Devices

� Layout Dependent Stress Effects� …� EKV3.1 Release expected: 2007.


Summary

� EKV3.0: a design-oriented, charge-based, compact model for Next Generation CMOS� Moderate and Weak Inversion, Analog/RF IC Design� Validated on Various CMOS Technologies to 65nm.

� Used for Commercial IC Design.� Developed in Verilog-A

� Verilog-A Code is Available to CAD Vendors.� Specific Simulators require Specific XML interface in ADMS� MOS Design Kits developed.

� Implementation ongoing for: � ELDO, Smash, GoldenGate, … � Spectre, HSPICE, …

Thank you very much for your time and attention

Status of the EKV3.0 MOS Transistor ModelA. Bazigos -- MOS-AK Workshop, September 22, 2006 20...

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