Status of OTIS O uter Tracker T ime I nformation S ystem

1Harald Deppe, Martin Feuerstack-Raible, Andre Srowig,

Uwe Stange, Ulrich Trunk, Dirk Wiedner Heidelberg University

Status of OTISOuter Tracker Time Information System

LHCb Week Rio2001, Sept.17 – Sept. 21

OTIS GROUP, Heidelberg University



LHCb at Cern

Cern LHCb



OTIS TDC

Outer Tracker Time Information System

3.250 OTIS-TDCs with 32 channels each

4 OTIS TDCs are connected to one GOL fast serializer one fibre per 128 channels Radiation hard layout 0.25 µm DLL fine time resolution 6 bit Dual Ported Memory with 1.2 Gb/s, 240 bit width low power design Synchronous clock driven readout



LHCb OTIS TDC

BCC

Clock

6464

15

In[0] In[1] In[31]

64 64 64

6 6 6

HR HR HR

D D D

Trigger

Sparsification

Read-out interface Data output

AC1600

240

48

LRB

…

…

…

Derandomizing buffer

Readout buffer

Slow control IF

DACs for ASBblr biasing

Channel mask register

DLLlockLost

DLL

MEMORY

CONTROL

ALGORITHM

Channel mask register



Delay Locked Loop

Test chip for MEMORY and DLL with MUX: OTISMEM1.0,

submitted February 2001

Chip OTISMEM1.0 received and tested:

Preliminary results available

2nd DLL prototype, contains: Delay chain with 32 stages 2 taps each Mean delay per tap 25ns/64 = 390 ps Currently Hit Register

for only one channel

with 64 bit multiplexed to 4 pads



DLL Lock Time

Lock Time is below 1µs

DLL Out

Clock In

Phase Difference

Control Voltage DLL



DLL Lock Range

Lock Range = 29…56MHz at 300K simulated Lock Range 30…50MHz (Within an 10% error) Spec is 30…50MHz at 300K OK !!!

Dynamic Range of Control Voltage 1VVctrl vs Freq

0

200

400

600

800

1000

1200

1400

1600

1800

24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60Freq/MHz

V

ctrl/

mV

Dyn

amic

Ran

ge



DLL Temperature Range

Measurement of Temperature Range Control Voltage inside Dynamic Range

for all tested Temperatures at 40 MHz

Vctrl vs Temp

0

200

400

600

800

1000

1200

1400

1600

1800

0 10 20 30 40 50 60 70 80 90 100T/°C

Tested with cooling spray

Vct

rl/m

V

Dyn

amic

Ran

ge



DLL Differential Non Linearity

Differential Non-Linearity (DNL) preliminary: 0.79bins (~310ps) at 40MHz Influence of MEMORY switching on DLL not tested Influence of test chip specific MUX on DLLGuard Ring

cut DNL #Bin (40MHz, Duty 50:50, Events/MuxAdr =10.000)

-0,5

-0,4

-0,3

-0,2

-0,1

0

0,1

0,2

0,3

0,4

0,5

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63

# TimeBin

Min: -0.33

Max: 0.46

DNL (0-63) ~ 0.79 Bins (~310ps)

DN

L [B

in]



OTIS MEMORY

Implemented on OTIS MEM1.0 Dual Ported Memory 240 bit total Pipeline Width 164 rows long Radiation hard layout Low power design



MEMORY Timing

Symbol Parameter Simulation Test chip Unit

Best Worst Best Worst

tAVRH address valid to read enable high 1.5 3 -0.3 -0.3 ns

tRLAX read enable low to address transition 2.5 5 -0.6 -0.3 ns

tRHRL read enable high to read enable low 4 8 1.6 2.1 ns

tRLRH read enable low to read enable high 8 15 5.9 6.7 ns

tRLDX read enable low to data transition =1 =2 =1.3 =1.6 ns

tRLDV read enable low to data valid =3.5 =7 =4.7 =5.1 ns

tDVWL data valid to write enable low 1.5 3 0.4 0.5 ns

tWLDX write enable low to data transition 1.5 3 1.5 1.6 ns

tAVWL address valid to write enable low 1.5 3 2.7 3.0 ns

tWLAX write enable low to address transition 4.5 9 2.7 3.0 ns

tWHWL write enable high to write enable low 4 7 2.8 3.2 ns

tWLWH write enable low to write enable high 8 16 x <5 ns



OTIS CONTROL ALGORITHM

Implementation of control elements in Verilog exists Simulation of:

Verilog Code exists FPGA Code exists

Tests on FPGA are running

The FPGA is used for verification of

the OTIS CONTROL ALGORITHM.



Implemented Elements

Bunch crossing Counter Pipeline Control Copy to Derandomizing Buffer Derandomizing Buffer Control Readout Control

1, 2, 3 Bunch crossings per Trigger Optional Bunch crossing Reuse

Trigger Counter

Simulation and Synthesis for FPGA and ASIC



Summary

OTISDLL1.0 Lock Range 30...50 Mhz Clock, Hit Signals differential DNL 0.79 Bins @40MHz Problems :

cross talk from MUX Guard Ring cut needed

MEMORY Functional Test successful Timing within specification

CONTROL ALGORITHM Logic synthesizable for FPGA and ASIC Tests on FPGA are in progress



Next steps

DLL: Simultaneous operation of MEMORY and DLL

(Power consumption, cross talk DNL etc.) Guard-Ring cut to reduce noise from MUX

Derandomizing Buffer: Timing (Beetle SR Test chip)

CONTROL ALGORITHM: Ongoing tests with FPGA Design for Test:

Memory Self test

Implementation of external memory access

Fast serial link via GOL-chip



Future Steps

Specification until October 2001 Submission of first complete OTIS

prototype in February 2002

Status of OTIS O uter Tracker T ime I nformation S ystem

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