Status of 65nm foundry access for Aida June 2013 A. Marchioro CERN/PH-ESE.

Status of 65nm foundry accessfor Aida

June 2013A. Marchioro CERN/PH-ESE

Status of 65nm 6/13 2

New Commercial Contract

• Proposal for new foundry contract submitted to CERN FC and approved on March 20– About same value as previous contract

(for both 65nm and new 130nm)– 5 Years– (Current 130nm contract still valid until 2015)

• Contract details (fine pricing, delivery terms, guarantee, shipping costs, applicable law, etc. etc.) finalized with IMEC

• Expecting contract signature by mid-Summer• Export conditions could be similar if not identical to the ones

with previous foundry– i.e. no “free” circulation of some of these chips!!!


Legal aspects

• New foundry has “special” confidentiality culture • Foundry is now willing to adapt NDA conditions

to HEP clients– New procedure requires new NDAs to be issued to all

users by IMEC• This was already done with Cadence to allow

CERN/Cadence/IMEC to work on new design kit• Details for extension to all HEP Institutes being

finalized with IMEC


Technical Aspects (1)• Design Kit

– Porting on Cadence OpenAccess with flow similar to old 130nm done by Cadence (Paris + US)

– First release received from Cadence• Result being qualified and tested at CERN by CERN with demo design

– Includes one flavor of digital cells (to be analyzed and eventually modified) from foundry Library, but no RT IO cells• Not clear if we can have more than one!• Modified library must be returned (and will continue to be owned by the

foundry)

– CERN has investigated usage of library characterization tool (Altos) but results are still controversial (most cells match data from foundry, others seem to be wrong)

– Training courses for new flow to be scheduled asap


Technical support and distributionmodel for new foundry

Foundry

IMEC

CERN InstituteA

UniversityB … Lab

Z

• First training on new flow to be organized at CERN– Later, to be seen


Orders for MPWand Production runs

Foundry

IMEC

CERN

InstituteA

UniversityB … Lab

Z

• Dedicated admin contact person assigned in CERN-ME

• All deliveries to CERN (MPW and productions runs), re-shipped from Geneva


Warning• Normal 65nm MPW runs from the new

foundry allow for all process options and splits at a fixed price.

• Designers tend to like these!

• Some of these options are very expensive in actual productions runs and people are very surprised when the bill is presented.

WAR

NIN

GW

ARNIN

G

WARNING


Technical Aspects: IPs

• Regular foundry SRAM generator are not suitable for radiation environment

• Specifications for Hardened SRAM prepared by CERN• Three companies contacted and qualified for providing

RadTol SRAM generator – Three offers received

• Winners to be announced soon

– First phase of work to start with CERN-WP1 funds by the summer

– Expected first delivery for Q1’14• IPs to be distributed for a fee



• Slow 12-bit, 65nm monitoring ADC:– 4 companies contacted, one selected– Work started with company that provided the

130nm slow ADC cell– Architecture is simple Wilkinson

(identical to old DCU in CMS) with improved offset cancelation scheme

– Project is funded and delivery expected Sep ‘13– Submit proto by Q4 ‘13

• IP available to everybody in community for a small fee



• CMOS IO Pads– Thick-oxide free minimal library with CMOS 1.2V

levels and robust ESD structures compatible with design kit using core only devices

– Technical details specified in a document by CERN– Specialized subcontractor identified • To be executed in 2nd ½ of 2013

– Project paid for by CERN– Available to users in HEP community for small fee



• PLL for generic applications• Specs:– Clock multiplier (40MHz -> 1.6GHz)– Low Power (< 5 mW)– Try SEU robustness through TMR– Offers in hands from three design houses– Typical PLL-IP cost: 35K-60K– Access cost for multi-use to be negotiated and

paid for by end-user



• Bandgap reference cell– This cell eventually necessary for all analog designs– Based on experience gained with multiple BG 130nm

submission• Design to start at CERN in July with EU-Aida funds • Submission in November ‘13– Small funds necessary for proto-chip

• To be included in IP library for a small fee


Other IP blocks necessary• High Speed SLVS cells• Optimized STD cells library for pixels?

– Characterization and library inclusion• I/O Pads optimized for usage with TSVs• I/O Pads optimized for bump-bonding• Specific CAE tools

– working on an early power estimation tool for digital• …• RT to extreme TID and high flux hadrons validation

– Test structures are available– Should this tech not be sufficient for extreme levels, it may require

some hard re-thinking of some current projects …


Design style

• Old foundry accepted many violations (justified through special waivers )to the sacred rule-book

• New foundry will accept NONE!


130 nm second source• Prices from new foundry is lower than current

prices• No sign that old foundry will discontinue

supplying CERN• Design kit to be re-spinned by Cadence Design

Services after work on 65 nm will be completed– Funds are available– Distribution will be free

• Introduction and distribution for users in Q4 ‘13.– Possibly new training courses to be organized


Conclusions

• CERN is committed to continue foundry support to Aida community for new CMOS generation and also for alternative of the current one– 65nm full support model to converge in second

part of ’13• IMEC to become official HEP interface to

foundry

Status of 65nm foundry access for Aida June 2013 A. Marchioro CERN/PH-ESE.

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