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![Page 1: StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to: Describe how.](https://reader035.fdocuments.us/reader035/viewer/2022062314/56649e215503460f94b0dd0a/html5/thumbnails/1.jpg)
StateCAD
FPGA Design Workshop
![Page 2: StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to: Describe how.](https://reader035.fdocuments.us/reader035/viewer/2022062314/56649e215503460f94b0dd0a/html5/thumbnails/2.jpg)
For Academic Use OnlyPresentation Name 2
Objectives
After completing this module, you will be able to:
Describe how to add states and transitions to a state diagram design
List the four wizards available in StateCADAccess the Configuration GUI to change compiler options
![Page 3: StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to: Describe how.](https://reader035.fdocuments.us/reader035/viewer/2022062314/56649e215503460f94b0dd0a/html5/thumbnails/3.jpg)
For Academic Use OnlyPresentation Name 3
Outline
OverviewBeginning a DiagramStates and TransitionsWizardsCompilationSummary
![Page 4: StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to: Describe how.](https://reader035.fdocuments.us/reader035/viewer/2022062314/56649e215503460f94b0dd0a/html5/thumbnails/4.jpg)
For Academic Use OnlyPresentation Name 4
StateCAD
• Translates state diagrams to HDL based designs• Automatically analyzes designs for problems such as
– Stuck-at states– Conflicting state assignments– Indeterminate conditions
• Includes StateBench
![Page 5: StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to: Describe how.](https://reader035.fdocuments.us/reader035/viewer/2022062314/56649e215503460f94b0dd0a/html5/thumbnails/5.jpg)
For Academic Use OnlyPresentation Name 5
StateCAD
Support concurrent state machines
Graphical operators for states
Mealy & Moore outputsResetsCombinatorial and synchronous
logicText comments
![Page 6: StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to: Describe how.](https://reader035.fdocuments.us/reader035/viewer/2022062314/56649e215503460f94b0dd0a/html5/thumbnails/6.jpg)
For Academic Use OnlyPresentation Name 6
FSM Wizard in StateCAD
![Page 7: StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to: Describe how.](https://reader035.fdocuments.us/reader035/viewer/2022062314/56649e215503460f94b0dd0a/html5/thumbnails/7.jpg)
For Academic Use OnlyPresentation Name 7
Logic Wizard in StateCAD
StateCAD Logic Wizard for data flow structures– Shifters, registers,latches,
counters, muxes, etc.Requires object type,
attributes, and signal names
Handles boolean equations within the wizard
![Page 8: StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to: Describe how.](https://reader035.fdocuments.us/reader035/viewer/2022062314/56649e215503460f94b0dd0a/html5/thumbnails/8.jpg)
For Academic Use OnlyPresentation Name 8
Overview
StateCAD diagrams have .dia extensions– File names have an eight character limit
StateCAD output– Language specific files
• VHDL, Verilog, or ABEL• VHDL and Verilog output files can be compiled using
various tools– Exemplar– Synopsys
![Page 9: StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to: Describe how.](https://reader035.fdocuments.us/reader035/viewer/2022062314/56649e215503460f94b0dd0a/html5/thumbnails/9.jpg)
For Academic Use OnlyPresentation Name 9
Outline
OverviewBeginning a DiagramStates and Transitions WizardsCompilationSummary
![Page 10: StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to: Describe how.](https://reader035.fdocuments.us/reader035/viewer/2022062314/56649e215503460f94b0dd0a/html5/thumbnails/10.jpg)
For Academic Use OnlyPresentation Name 10
Beginning a Diagram
• Project New Source• State Diagram• File Name
![Page 11: StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to: Describe how.](https://reader035.fdocuments.us/reader035/viewer/2022062314/56649e215503460f94b0dd0a/html5/thumbnails/11.jpg)
For Academic Use OnlyPresentation Name 11
Outline
OverviewBeginning a DiagramStates and TransitionsWizardsCompilationSummary
![Page 12: StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to: Describe how.](https://reader035.fdocuments.us/reader035/viewer/2022062314/56649e215503460f94b0dd0a/html5/thumbnails/12.jpg)
For Academic Use OnlyPresentation Name 12
Adding States
In the Draw Mode tool bar, use the State Mode command
States are given unique names when they are added or copied– May be used as actual state names– Can be changed or edited
Syntax of states:
NAME_ONLY NAMEOUTPUTS=1;
![Page 13: StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to: Describe how.](https://reader035.fdocuments.us/reader035/viewer/2022062314/56649e215503460f94b0dd0a/html5/thumbnails/13.jpg)
For Academic Use OnlyPresentation Name 13
Outputs
• Output list contains equations– Output equations– State variables
• Outputs support complex data flow logic– Bit or vector equations– Counters– Muxes
• Example:NAME
CNTR <= CNTR + 1;BUSOUT = (sigA OR sigB) AND NOT(sigC OR sigD)
![Page 14: StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to: Describe how.](https://reader035.fdocuments.us/reader035/viewer/2022062314/56649e215503460f94b0dd0a/html5/thumbnails/14.jpg)
For Academic Use OnlyPresentation Name 14
Outputs
Output Wizard is the easiest way to add outputs– In Edit State (double-click
on a state), select the Output Wizard button
![Page 15: StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to: Describe how.](https://reader035.fdocuments.us/reader035/viewer/2022062314/56649e215503460f94b0dd0a/html5/thumbnails/15.jpg)
For Academic Use OnlyPresentation Name 15
Transitions
• Use the Transition button to draw curved and straight transitions:– Straight transitions: Click on one state, then click on another state– Curved transitions:
Click on one state (a small square appears), another small square will follow the cursor (click to place), one more square will appear, place the final square on the state destination
![Page 16: StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to: Describe how.](https://reader035.fdocuments.us/reader035/viewer/2022062314/56649e215503460f94b0dd0a/html5/thumbnails/16.jpg)
For Academic Use OnlyPresentation Name 16
Curved Transitions
• Multiple segment transitions– Enable through
Options menu Graphics
– Deselect “Single Segment Curve”
• Unlimited number of segments• Each segment contains a starting point, two control
points, and an endpoint
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For Academic Use OnlyPresentation Name 17
Transition Conditions
• To add a transition condition, double-click on the transition for the Edit Condition dialog box
• Conditions are Boolean equations– Syntax errors and indeterminate conditions are checked during
compilation
• Conditions may use inputs, outputs, and logic variables– State names and variables from one machine may be used in
the condition of another machine. This allows communication between state machines
![Page 18: StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to: Describe how.](https://reader035.fdocuments.us/reader035/viewer/2022062314/56649e215503460f94b0dd0a/html5/thumbnails/18.jpg)
For Academic Use OnlyPresentation Name 18
Reset
Reset is taken from any state, when its condition is true
One synchronous and one asynchronous reset are allowed per state machine
Reset condition should not contain variables used in any other transition of the state machine– Reset overrides the state transition conditions
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For Academic Use OnlyPresentation Name 19
Reset
Use the Reset Mode command:
Click on an empty region for your start pointClick on the desired reset stateYou will automatically be asked to select the mode
(asynchronous or synchronous)The condition is automatically added (Reset)
![Page 20: StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to: Describe how.](https://reader035.fdocuments.us/reader035/viewer/2022062314/56649e215503460f94b0dd0a/html5/thumbnails/20.jpg)
For Academic Use OnlyPresentation Name 20
Text and Comments
To add text and comments to state diagrams, use the Text Mode:
Enter text here
Add as comments to HDL code
Make attributesvisible
![Page 21: StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to: Describe how.](https://reader035.fdocuments.us/reader035/viewer/2022062314/56649e215503460f94b0dd0a/html5/thumbnails/21.jpg)
For Academic Use OnlyPresentation Name 21
Text and Comments
Test vectors added into the HDL and included files can be referenced by including text in HDL
Language specific logic not supported by StateCAD may be implemented
Caution: When adding comments in HDL, text lines may be broken by StateCAD, and the new line will begin without a comment marker in HDL
![Page 22: StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to: Describe how.](https://reader035.fdocuments.us/reader035/viewer/2022062314/56649e215503460f94b0dd0a/html5/thumbnails/22.jpg)
For Academic Use OnlyPresentation Name 22
Outline
• Overview• Beginning a Diagram• States and Transitions• Wizards• Compilation• Summary
![Page 23: StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to: Describe how.](https://reader035.fdocuments.us/reader035/viewer/2022062314/56649e215503460f94b0dd0a/html5/thumbnails/23.jpg)
For Academic Use OnlyPresentation Name 23
WizardsFSM Wizard or
– Allows you to quickly create basic state machines
Optimization Wizard or– Collects information on design goals and target devices, to provide
optimized results for speed, area, gate count, etc.– Optimizes code for target device AND synthesis tool
Design Wizard– Combines FSM Wizard and Optimization Wizard into one– Only available through the Wizard Toolbar (Window Wizard
Toolbar)
![Page 24: StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to: Describe how.](https://reader035.fdocuments.us/reader035/viewer/2022062314/56649e215503460f94b0dd0a/html5/thumbnails/24.jpg)
For Academic Use OnlyPresentation Name 24
Wizards
• Logic Wizard or– Develops data flow logic– Supports counters, muxes,
shifters, latches, and gates
• Wizard Toolbar
![Page 25: StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to: Describe how.](https://reader035.fdocuments.us/reader035/viewer/2022062314/56649e215503460f94b0dd0a/html5/thumbnails/25.jpg)
For Academic Use OnlyPresentation Name 25
Outline
• Overview• Beginning a Diagram• States and Transitions• Wizards• Compilation• Summary
![Page 26: StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to: Describe how.](https://reader035.fdocuments.us/reader035/viewer/2022062314/56649e215503460f94b0dd0a/html5/thumbnails/26.jpg)
For Academic Use OnlyPresentation Name 26
Compilation
Compilation translates state diagrams into HDL– Automatic error checking,
logic minimization, state assignments
– Performs syntax check, language problems, and design problems
![Page 27: StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to: Describe how.](https://reader035.fdocuments.us/reader035/viewer/2022062314/56649e215503460f94b0dd0a/html5/thumbnails/27.jpg)
For Academic Use OnlyPresentation Name 27
Compiler Configuration Options
• Access Configurations options through the menu bar:– Options Configuration
• Options– Delete unread variables– Retain output
values– Implied else
• Language
![Page 28: StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to: Describe how.](https://reader035.fdocuments.us/reader035/viewer/2022062314/56649e215503460f94b0dd0a/html5/thumbnails/28.jpg)
For Academic Use OnlyPresentation Name 28
Compiler Configuration Options
• Check options– Indeterminate
transitions– Conflicting State
assignments
• State Assignments
![Page 29: StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to: Describe how.](https://reader035.fdocuments.us/reader035/viewer/2022062314/56649e215503460f94b0dd0a/html5/thumbnails/29.jpg)
For Academic Use OnlyPresentation Name 29
Outline
• Overview• Beginning a Diagram• States and Transitions• Wizards• Compilation• Summary
![Page 30: StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to: Describe how.](https://reader035.fdocuments.us/reader035/viewer/2022062314/56649e215503460f94b0dd0a/html5/thumbnails/30.jpg)
For Academic Use OnlyPresentation Name 30
Summary
State diagrams can be translated into VHDL, Verilog, or ABELNumerous toolbars are available to aid in your diagram designStates and state transitions are easily added through buttons
in the Draw Mode ToolbarThe Output Wizard gives access to the Logic Wizard, so you
can easily add output equations or conditions to any state or transition
Designs are compiled and translated with a simple push button
![Page 31: StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to: Describe how.](https://reader035.fdocuments.us/reader035/viewer/2022062314/56649e215503460f94b0dd0a/html5/thumbnails/31.jpg)
For Academic Use OnlyPresentation Name 31
Outline
• Overview• Beginning a Diagram• States and Transitions• Wizards• Compilation• Summary