State Machines

Figure 13-17:

General Model for Mealy Circuit

Using ClockedD Flip-Flops

Figure 13-18: Minimum Clock Period for a Sequential Circuit

Figure 13-19: General Model for Moore Circuit Using Clocked D Flip-Flops

Figure 13-5: Moore Sequential Circuit to be Analyzed

Figure 13-6: Timing Chart for Figure 13-5

Analysis of previous circuit for input sequence X = 01101

0 1 1 0 1

Mealy analysis for input sequence X = 10101

Figure 13-7: Mealy Sequential Circuit to be Analyzed

Figure 13-8: Timing Chart for Circuit of Figure 13-7

Figure 12-17: State Graph and Tablefor Up-Down Counter

CBA C+B+A+ U D

000 001 111 001 010 000 010 011 001 011 100 010 100 101 011 101 110 100 110 111 101 111 000 110

Figure 12-18: Binary Up-Down Counter

Moore

Implement with: 1. D fliflops 2. JK flip flops

Modify to have output = 1 when the state has equal number of 0s or 1s. Output will be 0 otherwise

Mealy

http://automatown.org/automata