State and Finite State Machines - Cornell University · 4‐bit Ripple Carry Adder A 3 B 3 S 3 C 4...

State and Finite State Machines

Hakim WeatherspoonCS 3410, Spring 2013Computer ScienceCornell University

See P&H Appendix C.7. C.8, C.10, C.11

Big Picture: Building a Processor

PC

imm

memory

memory

din dout

addr

target

offset cmpcontrol

=?

new pc

registerfile

inst

extend

+4 +4

A Single cycle processor

alu

• We can generalize 1‐bit Full Adders to 32 bits, 64 bits …

Review: Efficiency and Generality

A0 B0

S0

A1 B1

S1

A2 B2

S2

A3 B3

S3

C0

• We can generalize 1‐bit Full Adders to 32 bits, 64 bits … • How long does it take to compute a result?• Can we store the result?

Review: Efficiency and Generality

S0S1S2S3

overflow

A0

B0

A1

B1

A2

B2

A3

B3

mux mux mux mux

0=add1=sub

Performance

Speed of a circuit is affected by the number of gates in series (on the critical path or the deepest level of logic)

CombinationalLogic

tcombinational

inpu

tsarriv

e

outputs

expe

cted

4‐bit Ripple Carry Adder

A3 B3

S3

C4

A1 B1

S1

A2 B2

S2

A0 B0

C0

S0

C1C2C3

• First full adder, 2 gate delay• Second full adder, 2 gate delay• …

Carry ripples from lsb to msb

Stateful ComponentsUntil now is combinatorial logic

• Output is computed when inputs are present• System has no internal state• Nothing computed in the present can depend on what happened in the past!

Need a way to record dataNeed a way to build stateful circuitsNeed a state‐holding device

Finite State Machines

Inputs Combinationalcircuit

OutputsN M

Goals for TodayState

• How do we store one bit?• Attempts at storing (and changing) one bit

– Set‐Reset Latch– D Latch– D Flip‐Flops– Master‐Slave Flip‐Flops

• Register: storing more than one bit, N‐bitsBasic Building Blocks

• Decoders and EncodersFinite State Machines (FSM)

• How do we design logic circuits with state?• Types of FSMs: Mealy and Moore Machines• Examples: Serial Adder and a Digital Door Lock

GoalHow do we store store one bit?

First Attempt: Unstable Devices

B

A

C

01

First Attempt: Unstable Devices

Does not work!• Unstable• Oscillates wildly!

B

A

C

10

01

Second Attempt: Bistable Devices

In stable state, A = B

How do we change the state?

A B

A B

1

A B

10 0

A Simple Device

• Stable and unstable equilibria?

BR

Third Attempt: Set‐Reset Latch

Q

Q

AS


Set‐Reset (S‐R) LatchStores a value Q and its complement

S R Q Q0 00 11 01 1

S

RQ



S R Q Q0 00 1 ? ?1 01 1

S

RQ

A B OR NOR

0 0 0 1

0 1 1 0

1 0 1 0

1 1 1 0

0

1

0

Q will be 0 if R is 1

1

will be 1

S R Q Q0 00 1 0 11 01 1



S R Q Q0 00 1 0 11 0 ? ?1 1

S

RQ

A B OR NOR

0 0 0 1

0 1 1 0

1 0 1 0

1 1 1 0

1

0

1

Q will be 1

0

will be 0 if S is 1

S R Q Q0 00 1 0 11 0 1 01 1

What are the values for Q and ?a) 0 and 0b) 0 and 1c) 1 and 0d) 1 and 1



S R Q Q0 0 ? ?0 1 0 11 0 1 01 1

S

RQ

A B OR NOR

0 0 0 1

0 1 1 0

1 0 1 0

1 1 1 0

0

0

1

If Q is 1, will stay 1if Q is 0, will stay 0

0

If is 0 will stay 0If is 1 will stay 1

S R Q Q0 0 Q Q0 1 0 11 0 1 01 1

1



S R Q Q0 0 Q Q0 1 0 11 0 1 01 1 ? ?

S

RQ

A B OR NOR

0 0 0 1

0 1 1 0

1 0 1 0

1 1 1 0

1

1

0

Q will be 0 since R is 1

0

will be 0 since S is 1

What happens when S,R changes from 1,1 to 0,0?



S R Q Q0 0 Q Q0 1 0 11 0 1 01 1 ? ?

S

RQ

A B OR NOR

0 0 0 1

0 1 1 0

1 0 1 0

1 1 1 0

10

10

01 01

S R Q Q0 0 Q Q0 1 0 11 0 1 01 1 forbidden

What happens when S,R changes from 1,1 to 0,0?

Q and Q become unstable and will oscillate wildly between values 0,0 to 1,1 to 0,0 to 1,1 …

010010 010101010 0



S

RQ

S

R

Q

S R Q Q0 0 Q Q0 1 0 11 0 1 01 1 forbidden

S R Q Q0 0 Q Q hold

0 1 0 1 reset

1 0 1 0 set

1 1 forbidden

TakeawaySet‐Reset (SR) Latch can store one bit and we can change the value of the stored bit. But, SR Latch has a forbidden state.

Next GoalHow do we avoid the forbidden state of S‐R Latch?

Fourth Attempt: (Unclocked) D Latch

Fill in the truth table?

DS

R

Q

Q

D

D Q

0

1

S

RQ

A B OR NOR

0 0 0 1

0 1 1 0

1 0 1 0

1 1 1 0

Fourth Attempt: (Unclocked) D Latch

DS

R

Q

Q

D

D Q

0 0 1

1 1 0

S

RQ

A B OR NOR

0 0 0 1

0 1 1 0

1 0 1 0

1 1 1 0

Fill in the truth table?

Data (D) Latch• Easier to use than an SR latch• No possibility of entering an undefined state

When D changes, Q changes– … immediately (…after a delay of 2 Ors and 2 NOTs)

Need to control when the output changes


(Unclocked) D Latch can store and change a bit like an SR Latch while avoiding the forbidden state.

Next GoalHow do we coordinate state changes to a D Latch?

ClocksClock helps coordinate state changes

• Usually generated by an oscillating crystal• Fixed period; frequency = 1/period

1

0clockperiod

clockhigh

clocklow

risingedgefalling

edge

Clock DisciplinesLevel sensitive

• State changes when clock is high (or low)

Edge triggered• State changes at clock edge

positive edge‐triggered

negative edge‐triggered

Clock MethodologyClock Methodology•Negative edge, synchronous

– Edge‐Triggered: Signals must be stable near falling clock edge

•Positive edge synchronous

clk

compute save

tsetup thold

compute save compute

tcombinational

Fifth Attempt: D Latch with Clock

S

R

D Q


S

R

D

clk

Q

clk D Q

0 0

0 1

1 0

1 1

Fill in the truth table

clk D Q

0 0

0 1

1 0

1 1


S

R

D

clk

Q

S R Q

0 0 Q hold

0 1 0 1 reset

1 0 1 0 set

1 1 forbidden

clk D Q

0 0 Q

0 1 Q

1 0 0 1

1 1 1 0

Fill in the truth table


S

R

D

clk

Q

clk D Q

0 0 Q

0 1 Q

1 0 0 1

1 1 1 0

clk

DQ

Level Sensitive D LatchClock high:set/reset (according to D)

Clock low:keep state (ignore D)

Sixth Attempt: Edge‐Triggered D Flip‐FlopD Flip‐Flop•Edge‐Triggered•Data captured when clock is high•Output changes only on falling edges

D Q D QL L

clk

D

X

Q

c

X

c

QD

clk 0

0

1

01

Activity#1: Fill in timing graph and values for X and Q

Sixth Attempt: Edge‐Triggered D Flip‐FlopD Flip‐Flop•Edge‐Triggered•Data captured when clock is high•Output changes only on falling edges

D Q D QL L

clk

D

X

Q

c

X

c

QD

clk 10

10

01

1001


(Unclocked) D Latch can store and change a bit like an SR Latch while avoiding a forbidden state.

An Edge‐Triggered D Flip‐Flip (aka Master‐Slave D Flip‐Flip) stores one bit. The bit can be changed in a synchronized fashion on the edge of a clock signal.

Next GoalHow do we store more than one bit, N bits?

RegistersRegister•D flip‐flops in parallel •shared clock•extra clocked inputs:write_enable, reset, …

clk

D0

D3

D1

D2

4 44‐bitreg

clk


(Unclocked) D Latch can store and change a bit like an SR Latch while avoiding a forbidden state.

An Edge‐Triggered D Flip‐Flip (aka Master‐Slave D Flip‐Flip) stores one bit. The bit can be changed in a synchronized fashion on the edge of a clock signal.An N‐bit register stores N‐bits. It is be created with ND‐Flip‐Flops in parallel along with a shared clock.

An Example: What will this circuit do?

4‐bitreg

Clk

Decoder

+1

4

4 4

164

An Example: What will this circuit do?

4‐bitreg

Clk

Run

WE R

Reset

Decoder

A[4] 1 = 0001 =B[4]

S[4]

Cout +1

4

4 4

164

Decoder Example: 7‐Segment LED 7‐Segment LED

• photons emitted when electrons fall into holes

d7 d6 d5 d4

d3 d2 d1 d0

Decoder Example: 7‐Segment LED Decoder

3 inputs • encode 0 – 7 in binary

7 outputs• one for each LED

7LED

decod

e

b2 b1 b0 d6 d5 d4 d3 d2 d1 d0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

7 Segment LED Decoder Implementation

d0d1

d2d3

d4d5

d6

b2 b1 b0 d6 d5 d4 d3 d2 d1 d0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1 1 0 0 0 0 1 1

7 Segment LED Decoder Implementation

d0d1

d2d3

d4d5

d6

b2 b1 b0 d6 d5 d4 d3 d2 d1 d0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

1 1 1 0 1 1 1

1 0 0 0 0 0 1

0 1 1 1 0 1 1

1 1 0 1 0 1 1

1 0 0 1 1 0 1

1 1 0 1 1 1 0

1 1 1 1 1 1 0

1 0 0 0 0 1 1

Basic Building Blocks We have Seen

binaryencoder

2N

N binarydecoder

N

2N

Multip

lexor

N

M

NN

N

N

. . .

0

1

2

2M‐1

Encoders

1

2

3

4

5

6

7

0

encode

r

N

. . .

. . .

Log2(N) outputs wiresN Input wires

e.g. Voting:Can only vote for one out of N candidates, so N inputs.

But can encode vote efficiently with binary encoding.

Example Encoder Truth Table

a

b

1

c

d

2

3

4

o1

A 3-bitencoder

with 4 inputsfor simplicity

a b c d

0 0 0 0

1 0 0 0

0 1 0 0

0 0 1 0

0 0 0 1

o0

o1

o2

Example Encoder Truth Table

a

b

1

c

d

2

3

4

o1

A 3-bitencoder

with 4 inputsfor simplicity

a b c d o2 o1 o0

0 0 0 0 0 0 0

1 0 0 0 0 0 1

0 1 0 0 0 1 0

0 0 1 0 0 1 1

0 0 0 1 1 0 0

o0

o1

o2

• o2 = abcd• o1 = abcd + abcd• o0 = abcd + abcd

Basic Building Blocks Example: Voting

BallotsThe 3410 optical scan

vote readermachine

detect

enc8 3 7

7LED decode

RecapWe can now build interesting devices with sensors

• Using combinatorial logic

We can also store data values (aka Sequential Logic)• In state‐holding elements• Coupled with clocks

AdministriviaMake sure to go to your Lab Section this weekDesign Doc for Lab1 due Monday, Feb 4th Completed Lab1 due in two weeks, Monday, Feb 11thWork alone

Homework1 is outDue in one week, next Wednesday, start earlyHomework Help Session: Thursday and Monday, B14 HLN, 6‐8pmWork alone

BUT, use your resources• Lab Section, Piazza.com, Office Hours, Homework Help Session,• Class notes, book, Sections, CSUGLab

Administrivia

Check online syllabus/schedule • http://www.cs.cornell.edu/Courses/CS3410/2013sp/schedule.htmlSlides and Reading for lecturesOffice HoursHomework and Programming AssignmentsPrelims (in evenings):

• Tuesday, February 26th

• Thursday, March 28th

• Thursday, April 25th

Schedule is subject to change

Collaboration, Late, Re‐grading Policies“Black Board” Collaboration Policy• Can discuss approach together on a “black board”• Leave and write up solution independently• Do not copy solutions

Late Policy• Each person has a total of four “slip days”• Max of two slip days for any individual assignment• Slip days deducted first for any late assignment, cannot selectively apply slip days

• For projects, slip days are deducted from all partners • 25% deducted per day late after slip days are exhausted

Regrade policy• Submit written request to lead TA,

and lead TA will pick a different grader • Submit another written request,

lead TA will regrade directly • Submit yet another written request for professor to regrade.

Goals for TodayState

• How do we store one bit?• Attempts at storing (and changing) one bit

– Set‐Reset Latch– D Latch– D Flip‐Flops– Master‐Slave Flip‐Flops

• Register: storing more than one bit, N‐bitsBasic Building Blocks

• Decoders and EncodersFinite State Machines (FSM)

• How do we design logic circuits with state?• Types of FSMs: Mealy and Moore Machines• Examples: Serial Adder and a Digital Door Lock

Finite State Machines

Next GoalHow do we design logic circuits with state?

Finite State MachinesAn electronic machine which has

• external inputs• externally visible outputs• internal state

Output and next state depend on• inputs• current state

Abstract Model of FSM

Machine isM = ( S, I, O, )

S: Finite set of statesI: Finite set of inputsO: Finite set of outputs: State transition functionNext state depends on present input andpresent state

Automata ModelFinite State Machine

• inputs from external world• outputs to external world• internal state• combinational logic

Next State

Current State

Input

Output

Registers

Comb.Logic

FSM Example

Legend

state

input/output

startstate

A B

C D

down/onup/off down/on

up/off

up/off

up/off

down/offup/off

Input: up or downOutput: on or offStates: A, B, C, or D

FSM Example

Legend

state

input/output

startstate

A B

C D


up/off

up/off

up/off

down/offup/off

Input: = up or = downOutput: = on or = offStates: = A, = B, = C, or = D

FSM Example

Legend

S1S0

i0i1i2…/o0o1o2…

S1S000 01

10 11

1/10/0 1/1

1/0

0/0

1/0

0/00/0

Input: 0=up or 1=downOutput: 1=on or 1=offStates: 00=A, 01=B, 10=C, or 11=D

General Case: Mealy Machine

Outputs and next state depend on bothcurrent state and input

Mealy Machine

Next State

Current State

Input

OutputRe

gistersComb.Logic

Moore Machine

Special Case: Moore Machine

Outputs depend only on current state

Next State

Current State

Input

OutputRe

gisters Comb.Logic

Comb.Logic

Moore Machine FSM Example

Legend

stateout

input

startout

Aoff

Bon

Coff

Doff

downup down

up

up

up

downup


Mealy Machine FSM Example

Legend

state

input/output

startstate

A B

C D


up/off

up/off

up/off

down/offup/off


Activity#2: Create a Logic Circuit for a Serial AdderAdd two infinite input bit streams

• streams are sent with least‐significant‐bit (lsb) first• How many states are needed to represent FSM?• Draw and Fill in FSM diagram

…10110

…01111…00101

Strategy:(1) Draw a state diagram (e.g. Mealy Machine)(2) Write output and next‐state tables(3) Encode states, inputs, and outputs as bits(4) Determine logic equations for next state and outputs

FSM: State Diagram

Two states: S0 (no carry in), S1 (carry in)Inputs: a and bOutput: z

• z is the sum of inputs a, b, and carry‐in (one bit at a time)• A carry‐out is the next carry‐in state.• .

…10110

…01111…00101

a

bz

FSM: State Diagram


• z is the sum of inputs a, b, and carry‐in (one bit at a time)• A carry‐out is the next carry‐in state.• Arcs labeled with input bits a and b, and output z

S0 S1__/_ __/_

__/_

__/_

__/___/_

__/_

__/_

…10110

…01111…00101

a

bz

FSM: State Diagram

S0 S100/0 11/1

01/0

11/0

10/010/1

00/1

01/1


• z is the sum of inputs a, b, and carry‐in (one bit at a time)• A carry‐out is the next carry‐in state.• Arcs labeled with input bits a and b, and output z (Mealy Machine)

…10110

…01111…00101

a

bz

Serial Adder: State Table

a b Current state

z Next state

S0 S100/0 11/1

01/0

11/0

10/010/1

00/1

01/1

(2) Write down all input and state combinations

Serial Adder: State Table

(2) Write down all input and state combinations

a b Current state

z Next state

0 0 S0 0 S00 1 S0 1 S01 0 S0 1 S01 1 S0 0 S10 0 S1 1 S00 1 S1 0 S11 0 S1 0 S11 1 S1 1 S1

S0 S100/0 11/1

01/0

11/0

10/010/1

00/1

01/1

Serial Adder: State Assignment

(3) Encode states, inputs, and outputs as bits

Two states, so 1‐bit is sufficient• A single flip‐flop will encode the state

a b s z s'0 0 0 0 00 1 0 1 01 0 0 1 01 1 0 0 10 0 1 1 00 1 1 0 11 0 1 0 11 1 1 1 1

0 100/0 11/1

01/0

11/0

10/010/1

00/1

01/1

Serial Adder: Circuit

(4) Determine logic equations for next state and outputs

Combinational Logic Equationsz = b + a + s + abss’ = ab + bs + a s + abs

Next State

Current State

Input

Output

Comb.Logica

b

D Q s zs'

s'

Next State

a b s z s'0 0 0 0 00 1 0 1 01 0 0 1 01 1 0 0 10 0 1 1 00 1 1 0 11 0 1 0 11 1 1 1 1

Sequential Logic Circuits

Strategy:(1) Draw a state diagram (e.g. Mealy Machine)(2) Write output and next‐state tables(3) Encode states, inputs, and outputs as bits(4) Determine logic equations for next state and outputs

Next State

Current State

Input

Output

Comb.Logica

b

D Q s zs'

s'

Next State

z = b + a + s + abss’ = ab + bs + a s + abs...

Example #2: Digital Door Lock

Digital Door LockInputs:

• keycodes from keypad• clock

Outputs: • “unlock” signal• display how many keys pressed so far

Door Lock: InputsAssumptions:

• signals are synchronized to clock• Password is B‐A‐B

KAB

K A B Meaning0 0 0 Ø (no key)1 1 0 ‘A’ pressed1 0 1 ‘B’ pressed

Door Lock: OutputsAssumptions:

• High pulse on U unlocks door

UD3D2D1D0

4 LEDdec

8

Strategy:(1) Draw a state diagram (e.g. Moore Machine)(2) Write output and next‐state tables(3) Encode states, inputs, and outputs as bits(4) Determine logic equations for next state and outputs

Door Lock: Simplified State Diagram

Idle

G1

”0”

Ø

G2 G3

B1 B2

”1” ”2” ”3”, U

”1” ”2”

Ø Ø

Ø Ø

“B”

“A” “B”

else

else

any

anyelse else

B3”3”

else

(1) Draw a state diagram (e.g. Moore Machine)


Idle

G1

”0”

Ø

G2 G3

B1 B2

”1” ”2” ”3”, U

”1” ”2”

Ø Ø

Ø Ø

“B”

“A” “B”

else

else

else

anyelse else

(1) Draw a state diagram (e.g. Moore Machine)


Idle

G1

”0”

Ø

G2 G3

B1 B2

”1” ”2” ”3”, U

”1” ”2”

Ø Ø

Ø Ø

“B”

“A” “B”

else

else

else

anyelse else Cur.State Output

(2) Write output and next‐state tables


Idle

G1

”0”

Ø

G2 G3

B1 B2

”1” ”2” ”3”, U

”1” ”2”

Ø Ø

Ø Ø

“B”

“A” “B”

else

else

else

anyelse else Cur.State OutputCur.State Output

Idle “0”G1 “1”G2 “2”G3 “3”, UB1 “1”B2 “2”



Idle

G1

”0”

Ø

G2 G3

B1 B2

”1” ”2” ”3”, U

”1” ”2”

Ø Ø

Ø Ø

“B”

“A” “B”

else

else

else

anyelse else

Cur. State Input Next StateCur. State Input Next State



Idle

G1

”0”

Ø

G2 G3

B1 B2

”1” ”2” ”3”, U

”1” ”2”

Ø Ø

Ø Ø

“B”

“A” “B”

else

else

else

anyelse else

Cur. State Input Next StateCur. State Input Next StateIdle Ø IdleIdle “B” G1Idle “A” B1G1 Ø G1G1 “A” G2G1 “B” B2G2 Ø B2G2 “B” G3G2 “A” IdleG3 any IdleB1 Ø B1B1 K B2B2 Ø B2B2 K Idle


(3) Encode states, inputs, and outputs as bits

State Table EncodingCur. State Output

Idle “0”G1 “1”G2 “2”G3 “3”, UB1 “1”B2 “2”

UD3D2D1D0

4dec

8

D3 D2 D1 D0 U0 0 0 0 00 0 0 1 00 0 1 0 00 0 1 1 10 0 0 1 00 0 1 0 0

KAB

S2 S1 S00 0 00 0 10 1 00 1 11 0 01 0 1

K A B Meaning0 0 0 Ø (no key)1 1 0 ‘A’ pressed1 0 1 ‘B’ pressed

State S2 S1 S0Idle 0 0 0G1 0 0 1G2 0 1 0G3 0 1 1B1 1 0 0B2 1 0 1

Cur. State Input Next StateIdle Ø IdleIdle “B” G1Idle “A” B1G1 Ø G1G1 “A” G2G1 “B” B2G2 Ø B2G2 “B” G3G2 “A” IdleG3 any IdleB1 Ø B1B1 K B2B2 Ø B2B2 K Idle

S2 S1 S0 S’2 S’1 S’00 0 0 0 0 00 0 0 0 0 10 0 0 1 0 00 0 1 0 0 10 0 1 0 1 00 0 1 1 0 10 1 0 0 1 00 1 0 0 1 10 1 0 0 0 00 1 1 0 0 01 0 0 1 0 01 0 0 1 0 11 0 1 1 0 11 0 1 0 0 0

K A B0 0 01 0 11 1 00 0 01 1 01 0 10 0 01 0 11 1 0x x x0 0 01 x x0 0 01 x x

Door Lock: Implementation4

dec

3bitReg

clk

UD3‐0S2‐0

S’2‐0S2‐0

KAB

D3 D2 D1 D0 U0 0 0 0 00 0 0 1 00 0 1 0 00 0 1 1 10 0 0 1 00 0 1 0 0

S2 S1 S00 0 00 0 10 1 00 1 11 0 01 0 1

(4) Determine logic equations for next state and outputs

U = 2S1S0D0 = 2 1S0 + 2S1S0 + S2 1 0D1 = 2S1S0 + 2S1S0 + 2S1S0


dec

3bitReg

clk

UD3‐0S2‐0

S’2‐0S2‐0

KAB

S2 S1 S0 S’2 S’1 S’00 0 0 0 0 00 0 0 0 0 10 0 0 1 0 00 0 1 0 0 10 0 1 0 1 00 0 1 1 0 10 1 0 0 1 00 1 0 0 1 10 1 0 0 0 00 1 1 0 0 01 0 0 1 0 01 0 0 1 0 11 0 1 1 0 11 0 1 0 0 0

K A B0 0 01 0 11 1 00 0 01 1 01 0 10 0 01 0 11 1 0x x x0 0 01 x x0 0 01 x x

S2’ = S2S1S0KAB + S2S1S0KAB + S2S1S2KAB + S2S1S0K + S2 S1S0 KAB


dec

3bitReg

clk

UD3‐0S2‐0

S’2‐0S2‐0

KAB

Strategy:(1) Draw a state diagram (e.g. Moore Machine)(2) Write output and next‐state tables(3) Encode states, inputs, and outputs as bits(4) Determine logic equations for next state and outputs

SummaryWe can now build interesting devices with sensors

• Using combinational logic

We can also store data values• Stateful circuit elements (D Flip Flops, Registers, …)• Clock to synchronize state changes• State Machines or Ad‐Hoc Circuits

State and Finite State Machines - Cornell University · 4‐bit Ripple Carry Adder A 3 B 3 S 3 C 4...

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