Stanford µSequencer

December 2003

Motivation

• Control, initialization, and constant maintenance of Avalon peripherals– Perfectly deterministic

• Microprocessor is larger than necessary for these tasks• Engineering a custom state machine increases

time-to-market• Avalon MicroSequencer provides a solution

– Configurable, programmable state sequencer that fits into the Avalon bus fabric

– Leverages all the benefits of SOPC Builder

Configuration Options

• Size of the Instruction ROM – Words or K words– 36-bit Instruction words– Implemented in

Stratix/Cyclone synchronous RAM blocks

• Optional 32-bit accumulator register– For loop counting,

memory indexing, etc.

Software Build Tab

• Automated generation of memory files for Instruction ROM– .mif (Quartus compilation)– .dat (Verilog simulation)– .hex (VHDL simulation)– Files placed in system

directory

• Software can also be built by an external Perl script.

Sequencer Architecture

OPCODE & DATAROM

IP

DATA_REG

OPCODE

DATA

COND_BIT

ExecutionController

+1

==

&&

||

AvalonMaster

Address WR DataRD DataDATA_REG - a 32-bit wide registerIP - instruction pointerCOND_BIT - condition code bit

(base configuration)

Sequencer Architecture

OPCODE & DATAROM

IP

DATA_REG

OPCODE

DATA

COND_BIT

ExecutionController

+1

==

&&

||

AvalonMaster

Address WR DataRD DataDATA_REG - a 32-bit wide registerIP - instruction pointerCOND_BIT - condition code bitCNT_REG - 32-bit accumulator

CNT_REG

+

(with accumulator register)

Sequencer InstructionsLD(data) - DATA_REG = data

WR(addr) - Avalon Write *(addr) = DATA_REG

RD(addr) - Avalon Read DATA_REG = *(addr)

AND(data) - DATA_REG &= data

OR(data) - DATA_REG |= data

CMP(data) - (DATA_REG == data) ? (COND_BIT = 1) : (COND_BIT = 0)

JMP(true_off, false_off) - ((COND_BIT) ? (IP=true_off) : (IP=false_off))

Note – these instructions are implemented as C macros, so the state machine definition is actually written in C, which means that you can leverage the C language to do very complex things if you are so motivated. Please see the example state machine definitions that are output in the components SDK for examples on how to use these instructions in an actual state machine.

(base configuration)

Additional Instructions

LDC(data) - CNT_REG = data

INC(data) - CNT_REG += data

WRC() - Avalon Write *(CNT_REG) = DATA_REG

RDC() - Avalon Read DATA_REG = *(CNT_REG)

CMPC(data) - (CNT_REG == data) ? (COND_BIT = 1) : (COND_BIT = 0)

CPC() - DATA_REG = CNT_REG

Note – these instructions are implemented as C macros, so the state machine definition is actually written in C, which means that you can leverage the C language to do very complex things if you are so motivated. Please see the example state machine definitions that are output in the components SDK for examples on how to use these instructions in an actual state machine.

(supported when configured with accumulator register)

OPCODE/DATA Word Format

OPCODE DATA

36-bit ROM Word

32-bit DATA4-bit OPCODE

Design FlowSOPC Builder system

configuration/generation

Software Development

Software Compilationin SOPC Builder or using external script

ModelSim Simulation

Quartus Compilation

Quartus Smart Compile will skip the Analyzer and Fitter stages of compilation if only the MIF file has changed since the last full compile! (MIF file must be added to the project for this to work)

Performance• Approximately 130 LE’s

– 270 with accumulator register

• Using physical synthesis options in Quartus, we achieved fmax as high as 235 MHz on a Stratix 1S10 device, -5 speed grade– Configuration with accumulator runs at 200 MHz.

• Executes nearly one instruction per cycle– Three exceptions:

• One cycle delay before executing first instruction• One cycle delay after each jump (NOP inserted by compiler)• Avalon read/write instructions require sequencer to wait for transfer

Installation Package

• InstallShield Package contains everything necessary to begin developing with the Avalon MicroSequencer– SOPC Builder component class, HDL generator, & sample SDK– GCC and associated Cygwin packages (for microcode builder)

are added to the existing SOPC Builder installation of Cygwin– Avalon MicroSequencer Kit

• Preliminary Datasheet

• Four example/demonstration designs

• Tutorial with detailed instructions, summary readme, and starter projects

Note: The installation package should be used with Quartus II 4.0.