Stability Degradation in Bottom-gate Graphene Field-effect Transistors

3
Reliability of bottom-gate graphene field-effect transistors prepared by using inductively coupled plasma-chemical vapor deposition Jung-Kyu Lee, 1 Hyun-Jong Chung, 2 Jinseong Heo, 2 Sunae Seo, 2 Il Hwan Cho, 3 Hyuck-In Kwon, 4 and Jong-Ho Lee 1,a 1 School of EECS and ISRC, Seoul National University, Seoul 151-742, Republic of Korea 2 Semiconductor Devices Laboratory, Samsung Advanced Institute of Technology (SAIT), Yongin, Kyungi 446-712, Republic of Korea 3 Department of Electronics Engineering, Myongji University, Yongin, Kyungki 449-728, Republic of Korea 4 School of Electrical and Electronics Engineering, Chun-Ang University, Seoul 156-756, Republic of Korea Received 28 December 2010; accepted 18 April 2011; published online 12 May 2011 Stability degradation in bottom-gate graphene field-effect transistors prepared by using inductively coupled plasma-chemical vapor deposition method are investigated under bias, temperature and illumination stress. The stretched-exponential time dependence model, which can be derived based on the trapping/detrapping of charges to/from existing traps and continuous redistribution of charges in bulk dielectrics, is well applied in fitting the time dependence of the transfer curve shifts in all stress conditions. The stress wavelength is considered as important factors as well as the bias and temperature stress in the transfer characteristic instabilities of graphene FEFs. © 2011 American Institute of Physics. doi:10.1063/1.3589120 Graphene, ultrathin graphite film, has been considered as most attractive material for future nanoelectronic device ap- plications due to its excellent merits such as very high carrier mobility, 1 ballistic transport, 2 and high thermal conductivity. 3 In the past few years, there have been several approaches to implement graphene channels exfoliation method using scotch tape, 4 growth of graphene on SiC substrate at high temperature of 1450 ° C Ref. 5 and formation of graphene in ultrahigh vacuum environments 6 and some reliability reports. 7,8 However, reliability issues of graphene field-effect transistors FETs prepared by using chemical vapor deposi- tion CVD have not been reported. Especially, the electrical stability of the graphene FETs is critical to apply for sensor application such as gas, 9 pH, 10 and optoelectronic sensor 11 because it can lead to limit of sensing ability. So, it is pre- requisite to investigate the electrical, optical and thermal sta- bility of graphene FETs before sensor applications. In this letter, we study extensively reliability of the bottom-gate graphene FETs fabricated by CVD under prolonged gate bias, temperature, and laser light illumination in the air. Graphene grown by inductively coupled plasma ICP- CVD on Cu film at 650 °C is transferred into this prepat- terned substrate, which has the source and drain electrodes of Au formed on SiO 2 100 nm/Si, and then channel region is defined by using oxygen plasma etching. High doped n-type silicon is used as the back-gate. Mobility ranging from 3000 to 6000 cm 2 / V s at 300 K was extracted through 4-point gate dependent resistivity measurement in high vacuum. 12 All measurements were carried out using an Agilent 4156 C precision semiconductor parameter analyzer. The gate bias was interrupted at fixed times to record the transfer charac- teristics of the graphene FETs at a drain bias of 10 mV by sweeping the gate bias from 10 to 10 V, while the source electrode was grounded. Figure 1a shows that the transfer curves shift by the positive back-gate bias V BG of 10 V in the positive direc- tion, but the shape of the transfer curve is nearly constant. The slope of the curves shows a small variation during the applied bias stresses, which indicates that the shift can be mainly described by the threshold voltage shift V T with- out mobility degradation. Here, V T is a V BG difference be- tween the V BG after the stress and initial V BG at a fixed drain current. Two well-known degradation mechanisms are charge trapping in the gate insulator and the defect creation of new states in the channel or gate insulator. 13 In general, the defect state creation is accompanied by change in sub- threshold slope and mobility while the charge trapping is not. Therefore, the instability of our graphene FETs under gate bias stress might be originated from the trapping of carriers a Author to whom correspondence should be addressed. Electronic mail: [email protected]. -9 -6 -3 0 3 6 9 -0.42 -0.39 -0.36 -0.33 -0.30 -0.27 -0.24 -0.21 Drain current (m A) V BG (V) V D = - 10 mV, @RT stress voltage V ST = 10 V stress time : 0, 10, 100, 1000, 7000 s (a) 10 0 10 1 10 2 10 3 0 1 2 3 4 V ST = -10 V V ST = 10 V stretched-exponential fitting D V T (V) Stress Time (s) constant voltage stress @ RT (b) FIG. 1. Color onlinea I D - V BG curves shift under the constant voltage stress of 10 V. b The time depen- dence of V T under the constant gate biases of 10 and 10 V for 7 10 3 s at room temperature. APPLIED PHYSICS LETTERS 98, 193504 2011 0003-6951/2011/9819/193504/3/$30.00 © 2011 American Institute of Physics 98, 193504-1 Downloaded 18 May 2011 to 115.249.41.221. Redistribution subject to AIP license or copyright; see http://apl.aip.org/about/rights_and_permissions

Transcript of Stability Degradation in Bottom-gate Graphene Field-effect Transistors

Page 1: Stability Degradation in Bottom-gate Graphene Field-effect Transistors

Reliability of bottom-gate graphene field-effect transistors preparedby using inductively coupled plasma-chemical vapor deposition

Jung-Kyu Lee,1 Hyun-Jong Chung,2 Jinseong Heo,2 Sunae Seo,2 Il Hwan Cho,3

Hyuck-In Kwon,4 and Jong-Ho Lee1,a�

1School of EECS and ISRC, Seoul National University, Seoul 151-742, Republic of Korea2Semiconductor Devices Laboratory, Samsung Advanced Institute of Technology (SAIT), Yongin,Kyungi 446-712, Republic of Korea3Department of Electronics Engineering, Myongji University, Yongin, Kyungki 449-728, Republic of Korea4School of Electrical and Electronics Engineering, Chun-Ang University, Seoul 156-756, Republic of Korea

�Received 28 December 2010; accepted 18 April 2011; published online 12 May 2011�

Stability degradation in bottom-gate graphene field-effect transistors prepared by using inductivelycoupled plasma-chemical vapor deposition method are investigated under bias, temperature andillumination stress. The stretched-exponential time dependence model, which can be derived basedon the trapping/detrapping of charges to/from existing traps and continuous redistribution of chargesin bulk dielectrics, is well applied in fitting the time dependence of the transfer curve shifts in allstress conditions. The stress wavelength is considered as important factors as well as the bias andtemperature stress in the transfer characteristic instabilities of graphene FEFs. © 2011 AmericanInstitute of Physics. �doi:10.1063/1.3589120�

Graphene, ultrathin graphite film, has been considered asmost attractive material for future nanoelectronic device ap-plications due to its excellent merits such as very high carriermobility,1 ballistic transport,2 and high thermal conductivity.3

In the past few years, there have been several approaches toimplement graphene channels �exfoliation method usingscotch tape,4 growth of graphene on SiC substrate at hightemperature of 1450 °C �Ref. 5� and formation of graphenein ultrahigh vacuum environments6� and some reliabilityreports.7,8 However, reliability issues of graphene field-effecttransistors �FETs� prepared by using chemical vapor deposi-tion �CVD� have not been reported. Especially, the electricalstability of the graphene FETs is critical to apply for sensorapplication such as gas,9 pH,10 and optoelectronic sensor11

because it can lead to limit of sensing ability. So, it is pre-requisite to investigate the electrical, optical and thermal sta-bility of graphene FETs before sensor applications. In thisletter, we study extensively reliability of the bottom-gategraphene FETs fabricated by CVD under prolonged gatebias, temperature, and laser light illumination in the air.

Graphene grown by inductively coupled plasma �ICP�-CVD on Cu film at 650 °C is transferred into this prepat-terned substrate, which has the source and drain electrodes ofAu formed on SiO2 �100 nm�/Si, and then channel region isdefined by using oxygen plasma etching. High doped n-type

silicon is used as the back-gate. Mobility ranging from 3000to 6000 cm2 /V s at 300 K was extracted through 4-pointgate dependent resistivity measurement in high vacuum.12

All measurements were carried out using an Agilent 4156 Cprecision semiconductor parameter analyzer. The gate biaswas interrupted at fixed times to record the transfer charac-teristics of the graphene FETs at a drain bias of �10 mV bysweeping the gate bias from �10 to 10 V, while the sourceelectrode was grounded.

Figure 1�a� shows that the transfer curves shift by thepositive back-gate bias �VBG� of 10 V in the positive direc-tion, but the shape of the transfer curve is nearly constant.The slope of the curves shows a small variation during theapplied bias stresses, which indicates that the shift can bemainly described by the threshold voltage shift ��VT� with-out mobility degradation. Here, �VT is a VBG difference be-tween the VBG after the stress and initial VBG at a fixed draincurrent. Two well-known degradation mechanisms arecharge trapping in the gate insulator and the defect creationof new states in the channel or gate insulator.13 In general,the defect state creation is accompanied by change in sub-threshold slope and mobility while the charge trapping is not.Therefore, the instability of our graphene FETs under gatebias stress might be originated from the trapping of carriers

a�Author to whom correspondence should be addressed. Electronic mail: [email protected].

-9 -6 -3 0 3 6 9-0.42-0.39-0.36-0.33-0.30-0.27-0.24-0.21

Draincurrent(mA)

VBG (V)

VD = - 10mV,@RTstress voltage VST = 10 Vstress time :0, 10, 100, 1000, 7000 s

(a)100 101 102 1030

1

2

3

4VST = -10 VVST = 10 Vstretched-exponential fitting

DVT(V)

Stress Time (s)

constant voltage stress@RT

(b)

FIG. 1. �Color online� �a� ID−VBG curves shift underthe constant voltage stress of 10 V. �b� The time depen-dence of �VT under the constant gate biases of 10 and�10 V for 7�103 s at room temperature.

APPLIED PHYSICS LETTERS 98, 193504 �2011�

0003-6951/2011/98�19�/193504/3/$30.00 © 2011 American Institute of Physics98, 193504-1

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Page 2: Stability Degradation in Bottom-gate Graphene Field-effect Transistors

in the traps located in the interface or bulk dielectric layers.Figure 1�b� shows the time dependence of �VT under theapplication of constant gate biases of 10 and �10 V for 7�103 s at room temperature. According to the previousstudies, Logarithmic14 and stretched-exponential time depen-dence models15 were derived to quantitatively model the�VT based on the charge trapping mechanism. The differ-ence between them is that the logarithmic time dependencemodel speculated no further redistribution of the chargestrapped at the interface deeper into the bulk dielectric,whereas the stretched-exponential time dependence modelhypothesized the emission of trapped charges toward deepstates in the bulk dielectric for longer stress time �t��� andlarger stress field. Such a trap redistribution in the bulk di-electric is plausible that the amorphous structure of the gatedielectric will lend itself to an appreciable number of band-tail states which can act as transport states for the emittedlower energy trapped state charge.15 Our results show thatthe time dependence of the �VT is in agreement with thestretched-exponential time dependence equation. The equa-tion for the �VT is defined as

�VT = �VT-max�1 − exp�− �t/����� , �1�

where �VT-max is the maximum threshold voltage variation,�=�0 exp�E� /kT� represents the characteristic trapping timeof carriers where the thermal activation energy is given byEa=E�� �in which � is the stretched-exponential exponentand E� is the average effective energy barrier that carriersneed to overcome before they can enter the insulator�, and �0is the thermal prefactor for emission over the barrier. Duringnegative gate bias stress, the holes injected from graphenechannel partially screen the applied electric field so that theeffective applied gate voltage is smaller when injected holesexist at the interface or bulk dielectric layers. When positive

gate bias stress is applied to the gate electrode, the transfercurve moves to the initial one, which is due to the emissionof holes to the graphene channel.

Figure 2 shows that the time evolution of the �VT underdynamic stresses with a duty cycle of 0.5, a period of 2�103 and gate bias of �10 V at room temperature. Duringthe both stress and recovery times, the time dependences ofthe �VT are well described by stretched-exponential timedependence equation. The equation in recovery time are de-fined as15

�VT = �VT0 exp�− �t/���� , �2�

where �VT0 is the �VT at infinite time. This repetitive andreversible VT behavior indicates that the relaxation behavioris associated with the detrapping of the previously trappedcharges. The �VT increases during the stress phase and de-creases during the recovery phase but not fully recovered fora given recovery time of 103 s. Considering that time con-stants extracted from the stretched-exponential fitting duringthe stress phase ��1=1150 s and �3=900 s� are smaller thanthose during the recovery ��2=2100 s and �4=2800 s�, theresults suggest that a part of trapped holes are located in deeptraps of dielectric, and remain relatively stable.

To further investigate the VT shift phenomenon in thegraphene FETs, stress measurements were performed withvarious stress temperatures. Figure 3�a� shows the time de-pendence of �VT under different stress temperatures, whichindicates that the stretched-exponential time dependenceequation is well applied in all stress temperature conditions.The reciprocal temperature dependency of �, obtained fromthe fitting of experimental data with a stretched-exponentialequation, shows that it follows an Arrhenius relationship asshown in Fig. 3�b�. E� and Ea at room temperature �297 K�are determined to be 0.28 eV and 0.13 eV, respectively. Theinset of Fig. 4�b� shows the values of � as a function oftemperature. The temperature dependence of � agrees withthe conventional model of bias stress instability, that is, lin-early increases with temperature by the equation of �=TST /T0−�0, where TST is the stress temperature and T0 isrelated to the energy parameters of the charge trapping pro-cess, although the physical meaning of �0 is not clarified.15

The values of each extracted parameter can be varied withfabrication conditions but the aforementioned observationabout the bias stress and stress temperature dependency ofeach fitting parameter leads us to the conclusion that thestretched-exponential time dependence model can be effec-tively applied to the bias-induced stability analysis ofgraphene FET with a SiO2 gate dielectric.

Additionally, we investigated the degradation effect by aillumination using the red �660 nm�, green �532 nm�, andblue �405 nm� laser sources. The inset of Fig. 4 shows the

0 1000 2000 3000 4000

0

1

2

3

t3 : 900

t4 : 2800t2 : 2100

stress ( VBG = -10 V )recovery ( VBG = 0 V )stretched-exponential fitting

DVT(V)

Time (s)

t1 : 1150

FIG. 2. �Color online� The time dependence of �VT under dynamic stresseswith a duty cycle of 0.5 and a period of 2000 s at room temperature.

102 1030

2

4

6

8

1060 oC40 oC20 oCstretched-exponential fitting

DVT(V)

Stress Time (s)

VST = -10 V

34 35 36 37 38 39 40 41101

102

103

104

t(s)

1/kT (eV-1)

Et = 0.28 eV

290 300 310 320 330 3400.40.50.60.70.8

Exponent(b)

Stress Temperature (K)

FIG. 3. �Color online� �a� The time dependence of �VT

under different stress temperatures. �b� Characteristictrapping time � as a function of reciprocal temperature.The inset shows the values of � as a function oftemperature.

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Page 3: Stability Degradation in Bottom-gate Graphene Field-effect Transistors

�VT of our graphene FET under red, green and blue laserillumination for 3�102 s at room temperature. The largest�VT was observed under the blue light illumination. This isbecause the holes generated in the graphene channel by theoptical illumination can be trapped more easily into deeptraps in dielectric under the blue light having the largest en-ergy. Note that the heating effect from the laser illuminationcan be ignorable because the temperature of a device beingilluminated is a few degrees ��5 °C� at an optical power of10 mW. Figure 4 shows the time dependence of the �VTunder the blue �405 nm� light and a constant voltage stress of�10 V, which indicates that the stability degradation underthe illumination is still primarily due to the charge trappingin the gate insulator. The time dependence of �VT can bewell fitted with the stretched-exponential equation with acharacteristic trapping time � of 270 s and a stretched-exponential exponent � of 0.64. This trapping time is theshorter compared to that under electrical or optical stressonly, because charge trapping process is activated more ef-fectively under both electrical and optical stresses.

In conclusion, the stability degradation characteristics ofp-type graphene FEF prepared by using ICP-CVD were stud-ied under bias, temperature and/or optical stress. From thetransfer curves measured before and after stresses, the chargetrapping model is considered as the main cause of stabilitydegradation in our graphene FET. In all stress conditions, thestretched-exponential equation is well applied in fitting thetime dependence of �VT. The stress wavelength is also con-sidered as an important factor as well as the bias stress in thetransfer characteristic instabilities of graphene FETs.

This work was supported by Basic Science ResearchProgram through the National Research Foundation of Korea�NRF� grant funded by the Korea government �MEST��Grant No. 2010-0001870�.

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101 102 103

0

5

10

15

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25

stretched-exponential fittingmeasurement

DVT(V)

Stress Time (s)

Optical andBias Stress

PST = 12.6mWlST = 405 nmVST = -10 V

400 500 600 7000.1

1

10

DVT(V)

wavelength (nm)

Optical StressTST : 300 s, PST : 10mWVST : VS = VD = VBG = 0 V

FIG. 4. �Color online� The time dependence of the �VT under the blue lightand a constant voltage stress of �10 V. The inset of Fig. 4 shows the �VT

of our graphene FET under red, green and blue laser illumination for3�102 s at room temperature.

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