Stability Analysis and Improvement of the Capacitor ... · Fig. 1 shows the structure of a...

Journal of Power Electronics, Vol. 16, No. 4, pp. 1565-1577, July 2016 1565

http://dx.doi.org/10.6113/JPE.2016.16.4.1565

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718

JPE 16-4-30

Stability Analysis and Improvement of the Capacitor Current Active Damping of the LCL Filters in

Grid-Connected Applications

Jinming Xu†, Shaojun Xie*, and Binfeng Zhang*

†, *College of Automation Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, China

Abstract

For grid-connected LCL-filtered inverters, dual-loop current control with an inner-loop active damping (AD) based on capacitor current feedback is generally used for the sake of current quality. However, existing studies on capacitor current feedback AD with a control delay do not reveal the mathematical relation among the dual-loop stability, capacitor current feedback factor, delay time and LCL parameters. The robustness was not investigated through mathematical derivations. Thus, this paper aims to provide a systematic study of dual-loop current control in a digitally-controlled inverter. At first, the stable region of the inner-loop AD is derived. Then, the dual-loop stability and robustness are analyzed by mathematical derivations when the inner-loop AD is stable and unstable. Robust design principles for the inner-loop AD feedback factor and the outer-loop current controller are derived. Most importantly, ensuring the stability of the inner-loop AD is critical for achieving high robustness against a large grid impedance. Then, several improved approaches are proposed and synthesized. The limitations and benefits of all of the approaches are identified to help engineers apply capacitor current feedback AD in practice. Key words: Active damping, Capacitor current feedback, Control delay, LCL filter, Stability

I. INTRODUCTION

In distributed power generation systems based on renewable energies, a grid-connected inverter is used to inject power into the grid. However, the pulse-width-modulation (PWM) results in a lot of switching harmonics. In order to avoid polluting the ac grid, an inverter should ensure a grid current with a low distortion. Thus, a filter is required. An LCL-type filter is capable of attenuating switching harmonics in the grid current with a lower inductance than an L filter. As a result, it has been widely used to satisfy harmonic limitations. However, due to the inherent resonance of an LCL filter, the inverter has a hard time realizing good stability and a high bandwidth. Studies of inverter-side current or grid current controls have indicated that performance with a single current feedback is related to the ratio of the resonance and control frequencies so that the filter

and controller parameters cooperate properly [1]. However, because of some non-ideal factors like variations of the LCL parameters and grid impedance, an inverter with a single current feedback is difficult to design and tends to perform poorly in the case of wide parameter variations. Using a passive resistor in series with a capacitor is a simple way to improve the inverter performance at the cost of power losses [2]. Alternatively, during the last decade, researchers have tried to use active damping (AD) to improve performance. AD methods include capacitor current feedback [3]-[6], capacitor voltage feedback [7] and [8], grid current feedback [9] and [10] and multi-state feedback [11] and [12]. Among them, capacitor current feedback is broadly discussed.

For capacitor current feedback AD, the proportional feedback of the capacitor current is shown to be capable of damping resonance and improving performance when the control delay is ignored [3]-[6]. A design method based on zero-pole cancellation was proposed in [3], while the parameters are determined by balancing the peak attenuation and phase margin [4]-[6]. However, the control delay in a digital signal processor (DSP) should be considered. In [13], a dual-loop current control with both capacitor current and

Manuscript received Dec. 2, 2015; accepted Apr. 6, 2016 Recommended for publication by Associate Editor Jae-Do Park.

†Corresponding Author: [email protected] Tel: +86 13913391056, Nanjing Univ. of Aeronautics and Astronautics

*College of Automation Engineering, Nanjing University of Aeronautics and Astronautics, China

© 2016 KIPE

1566 Journal of Power Electronics, Vol. 16, No. 4, July 2016

grid current feedbacks was investigated for three different resonance frequencies. It was shown that the proportional feedback of the capacitor current did not stabilize the system at low resonance frequencies. However, the detailed relations between the stability and the resonance frequency were not given. As a result, a guideline for an optimized design was lacking. In [14], the virtual impedance method demonstrated that the proportional feedback of the capacitor current no longer acted like a virtual resistor at high resonance frequencies (above 1/6 of the control frequency, as analyzed in [15]). However, the relationships among the dual-loop stability, the AD and the control delay were not clearly identified. In [16], the stability criterion of the capacitor current feedback AD was derived. However, the dual-loop stability was missing. In [17], the stable region was derived in the case of a one-sample delay. However, the robustness was ignored, and the impact of the AD on the dual-loop stability was simply mentioned with few words. The state-of-art studies show that:

1) Existing studies on capacitor current feedback AD considering a delay did not reveal the mathematical relationships among the capacitor current AD, the dual-loop stability, the delay and the LCL parameters.

2) The robustness was investigated by simply observing the variation trends with respect to the filter parameters through the root locus or bode plots [5], [13], [16], [17]. However, mathematical derivations are lacking.

3) The control delay was considered to be a constant value (i.e., equal to one control period) in the previous studies. However, this assumption is no longer accurate or reasonable due to two facts. a) The conversion time of analog-to-digital sampling was ignored. b) In the past, a DSP was commonly programmed to work at a low control frequency with a delay of one control period because of the limited capability of the DSP. However, with modern techniques, it is no longer a big deal for a DSP to work in a more flexible mode (for instance, with a delay time of less than one control period [14] or a higher control frequency).

Considering that studies on dual-loop control are lacking, it is not surprising that approaches enhancing performance are still lacking or not well documented. The authors of [14] discussed one way of moving the sampling instant toward the reloading instant of the PWM reference in order to extend the frequency range where the AD behaved as a virtual resistor. However, aliasing harmonics as analyzed in [14] and [18] affected the sampling accuracy. In [19], a real-time loading approach is used to reduce the delay. Closed-loop pole maps were given to identify robustness. However, theoretical demonstrations were missing. In addition to the two approaches depending on the DSP working mode, the use of an extra phase compensator seemed to be an alternative choice. In [15], [17], [20] and [21], researchers tried several

Udc

+

-

S1

S2 S3

ug

+

-

current controller& active damping

S1~S4

L1 L2C1

PWM

um

uinv

+

-

iL1 igS4

voltage controllerUref

IrefPLL

sinθ iref

iC1(via iL1-ig)ig

iref

Fig. 1. Grid-connected LCL-filtered inverter.

kinds of compensators such as the proportional plus derivative, as well as high-pass and delay-based filters. All of them feature phase leading and the designs had to make a balance between robustness and noise disturbance.

Under these circumstances, research on the stability and improvement of dual-loop control with capacitor current AD is lacking. Therefore, this paper aims to provide a deep study of such AD. The model of a digital control system is more complex than that of the analog control system in [22]. This study focuses on the dynamics and stability at frequencies below the control frequency. Either the s-domain or z-domain model can be used. Digital PWM is seen as a zero-order hold (ZOH) in the s-domain and z-domain models [1], [9], [14]-[17]. In addition, for an accurate representation of the digital control delay, an exponential function of the delay time should be used in the s-domain model [14], [15], [17]. It is noted that if the dynamics and stability at higher frequencies are concerned, the s-domain model is no longer proper due to the nonlinear dynamics of power switches. In this case the z-domain model should be carefully used. In [23]-[25], researchers have made some contributions to the accuracy of the z-domain model. However, this topic is not the emphasis of this paper.

This paper derives the detailed constraints of the LCL-filter, controller and DSP working mode to ensure good stability and high robustness. Based on theoretical derivations, several suitable approaches are proposed to maintain better stability and performance. A grid-connected LCL-filtered inverter is built to verify the theoretical analysis.

II. SYSTEM DESCRIPTION

Fig. 1 shows the structure of a grid-connected inverter with an LCL filter consisting of an inverter-side inductor L1, a filter capacitor C1 and a grid-side inductor L2, where Udc denotes the DC voltage, uinv denotes the inverter output voltage, iL1 is the inverter-side current, ug is the grid voltage, and ig represents the grid current. In practical applications, the DC side can be connected to an input source (e.g., a PV array or a DC bus) in

Stability Analysis and … 1567

1

1

L s 1

1

C s 2

1

L sPWMk

ADk

( )cG s

Fig. 2. Structure of capacitor current and grid current feedback dual-loop control.

a single-stage system or to a DC-DC converter in a dual-stage system. The current amplitude reference Iref is produced by the DC voltage control, which is used to keep the DC voltage at Uref. A phase-locked loop (PLL) is adopted to obtain the phase information (θ) of ug. Then, Iref is multiplied by sinθ to generate the instantaneous current reference iref. With proper current control, a signal um is generated for the digital PWM. Here, um is called the modulation wave (also called the PWM reference [14]). Fig. 2 gives the current control, where kPWM denotes the transfer function from um to the inverter voltage uinv, and kAD is a proportional factor.

The transfer function from uinv to ig is expressed as:

31 2 1 1 2

1( )

( )g

inv

iuG s

L L C s L L s

(1)

A pair of under-damped poles appears at the resonance frequency ωres. The expression of ωres is:

1 2 1 2 12 ( )res resf L L L L C (2)

III. STABILITY WITH CAPACITOR-CURRENT

FEEDBACK ACTIVE DAMPING

A. Capacitor-Current-Feedback AD without a Delay

The equivalent structure of the inner-loop AD control is shown in Fig. 3, where the transfer function from uinv to iC1 is:

1

2 21

1( )C

inv

iu

res

sG s

L s

(3)

As shown from Fig. 3, the open-loop transfer function is: 1

OL AD PWM( ) ( )C

inv

iuG s k k G s (4)

If the control delay is not considered, kPWM is just a proportional factor (i.e., Udc/Vtri, where Vtri is the amplitude of the triangle carrier [6]). Then, Bode plots of (4) with respect to different values of kAD are shown in Fig. 4. Due to the high peak, two 0dB-crossing points are produced. However, according to the Nyquist stability criterion in the Bode plots (in Appendix A), the AD control works stably because the phase curve does not cross the ±180°-lines between the two 0dB-crossing frequencies. Moreover, as can be seen from Fig. 4 (i.e., the colored points), the phase margins (PMs) at the two 0dB-crossing frequencies are −90° and 90°. That is, the capacitor current AD fails to suppress the resonance peak once another 90° advance or lag is added to the open-loop phase. Unfortunately, the control delay yields a fairly large lag in the phase.

1 ( )C

inv

iuG sPWMk

ADk

Fig. 3. Equivalent structure of capacitor current AD.

Fig. 4. Bode plots of (4) without the control delay.

B. Stable Region of the AD in a Digital Control System

In a digital system, there is always a delay between the signal sampling and the modulation wave reloading. In addition, the PWM inverter can be seen as a zero-order hold model. That is, kPWM in a digital system is:

( 2)PWM PWM PWM

1 s

d d s

sTsT s T T

s

ek k e k e

sT

(5)

where |kPWM| is Udc/Vtri [14], Ts is the control period, and Td is the delay between the sampling of iC1 and the reloading of um. The total control delay is the sum of Td and Ts/2. The control delay makes the phase curve of (4) lower than that shown in Fig. 3. As a result, the PM is decreased and the system stability is endangered. The phase lag caused by (5) at frequency f is:

22 d s

lags s

T T f

T f

(6)

where fs is the control frequency, which is equal to 1/Ts. To evaluate the stability, the 0dB-crossing frequencies

should be calculated first. By letting the magnitude of (4) be equal to 1, the two 0dB-crossing frequencies in rad/s are exactly the solutions of the following equations:

2 2AD PWM

1

2 2AD PWM

1

10

10 0

res res

res res

k kL

k kL

(7)

Then, the two 0dB-crossing frequencies in Hz are:


2 2AD PWM 1 AD PWM 1

1

2 2AD PWM 1 AD PWM 1

2

41

2 2

41

2 2

res

x

res

x

k k L k k Lf

k k L k k Lf

(8)

Accordingly, considering the control delay, the phase of (4) at a higher 0dB-crossing frequency fx1 is:

1OL 1

2( 2 ) 2

2d s x

xs s

T T fG j f

T f

(9)

Then, the PM at fx1 is:

11 OL 1

2PM ( 2 ) 2

2d s x

x xs s

T T fG j f

T f

(10)

Since the open-loop transfer function in (4) does not have a right-half-plane pole, the stability can be guaranteed as long as no positive or negative crossings occur. Therefore, the way to ensure stability is PMx1> 0°, i.e.:

122 0

2d s x

s s

T T f

T f

(11)

As can be seen from (11), the stable region of the capacitor current AD is closely related to the sampling and computation delay time, the control frequency, the resonance frequency and the feedback factor. Note that if (11) is fulfilled, the phase at the lower 0dB-crossing frequency fx2 is much smaller than 180°. Therefore, the PM at fx2 is satisfactory.

As can be seen from (8), if kAD is small, fx1 and fx2 both become approximately equal to fres. It is obtained from (11):

4 2res s

s d s

f T

f T T

(12)

Accordingly, a critical value of the resonance frequency can be obtained:

2res divd sT T

(13)

If (13) is satisfied, it is possible for the capacitor current feedback to work stably with a proper kAD. Especially, for Td=Ts (i.e., a one-sample delay), the critical value of α is exactly 1/6. Meanwhile, for Td=0.5Ts, the critical value of α is exactly 1/4. It is emphasized that (13) is a necessary condition, and that the parameter kAD still has to satisfy (11).

For a known value of ωres, the range of the feedback factor is obtained from (8) and (11):

2 21

AD ADMax

( )div res

div

LK K

(14)

where KAD is equal to kAD|kPWM|, and KADMax is the maximum value of KAD. The calculation steps are given in Appendix B.

Therefore, when the system parameters satisfy (15), the inner AD control is stable. On the other hand, if (15) is not fulfilled, a negative crossing in the open-loop phase appears so that a closed-loop transfer function with an inner AD

TABLE I SYSTEM DEFAULT PARAMETERS

Parameters Symbols Values

Grid voltage Ug 220 V Grid frequency f0 50 Hz DC-link voltage Udc 400 V

Rated power P 5 kW Switching frequency fsw 15 kHz Control frequency fs 15 kHz

Inverter-side inductance L1 0.6 mH Grid-side inductance L2 0.36 mH

Filter capacitance (two sets) C1 7 / 17 μF

0 2 4 6 8 10 12 14 16 18 20-100

-80

-60

-40

-20

0

20

40

kAD

PM

x1 (d

eg)

unstable region

C1=17 μFC1=7 μF

KADMax=7.48

Fig. 5. Plots of PMx1 with respect to different KAD.

control has two unstable poles.

AD ADMax

res div

K K

(15)

To verify the analysis, the system parameters are given in Table I and the delay Td is 0.5Ts. Then, with the use of (13), α and ωdiv are calculated. The ratio α is 0.267 with C1=7μF (ωres>ωdiv), while it is 0.172 with C1=17μF (ωres<ωdiv). The variation trend of PMx1, subjected to different values of KAD, is given in Fig. 5. Therefore, it is unable to maintain stability when ωres is above the critical frequency, as shown by the solid line. On the other hand, the proportional capacitor current feedback is able to work with a proper KAD for ωres<ωdiv. By substituting the LCL parameters and ωdiv into (14), the limit of KAD is then obtained as KAD<7.48. As indicated by the dashed line, a larger KAD also results in instability of the inner AD control.

IV. STABILITY AND ROBUSTNESS WITH

DUAL-LOOP CURRENT CONTROL

A. Impact of Inner-Loop Stability on Dual-Loop Control

In this section, the overall stability including the outer and inner control loops will be analyzed. Fig. 6 shows the equivalent control structure of Fig. 2, where the transfer function from iC1 to ig is expressed as:

1 22 1

1( )g

C

i

iG sL C s

(16)


1 ( )C

inv

iuG sPWMk

ADk

( )cG s1( )g

C

i

iG s

Fig. 6. Equivalent structure of dual-loop current control.

The open-loop transfer function from iref to ig is:

1

1_ OL ( ) ( ) ( ) ( )g gC

ref C

i iii c u iG s G s G s G s (17)

Proportional-resonant and proportional-integral regulators are two commonly used regulators [3], [6]. Given that the effect of the resonant or integral element on the stability margin is small, Gc(s) is usually treated as a proportional regulator (i.e., kp) in the analysis of stability [14], [17]. The specific expression of the open-loop transfer function is:

( 2)P

_ OL ( 2)3 21 2 1 AD 2 1

1 2

d sg

ref d s

s T Tii s T T

K eG s

L L C s K L C s e

L L s

(18)

where KP is equal to kp|kPWM|. Note that Gc(s) and (16) do not have poles with a positive

real part. Thus, if the inner AD is stable, (17) and (18) have no poles on the right half of the s-plane (or outside the unit circuit in the z-plane). Meanwhile, if the inner AD is unstable, (17) and (18) have two poles on the right half of the s-plane. 1) Case I: the Inner AD Control is Stable

As can be seen from the above analysis, (18) has no poles on the right half of the s-plane if the inner-loop AD control is stable. Taking C1=17μF in Table 1 as an example, as shown in Fig. 7(a), the phase curves of the system all cross the –180° line only at the resonance frequency ωres when KAD<KADMax. According to the Nyquist stability criterion in the Bode plot, the design of the outer current controller should ensure that the gain margin GM(ωres) at ωres is larger than 0:

22 1 AD

P_ OL

1 2 AD

1 P

1( ) 20 lg 20 lg

( )20 lg 0

g

ref

resres i

resi

L C KGM

KG j

L L K

L K

(19)

As can be seen from (19), with a decrease of KAD or an increase of KP, the gain margin decreases and the system eventually loses stability. 2) Case II: the Inner AD Control is Unstable

When the AD control is unstable, (18) has two poles on the right half of the complex s-plane. A positive crossing with the –180° line is needed according to the Nyquist stability criterion in the Bode plot. Recalling the stable regions shown in (15), there are two kinds of unstable regions for the inner AD control: 1) ωres≥ωdiv; 2) ωres<ωdiv and KAD> KADMax.

First, when ωres≥ωdiv (taking C1=7μF as an example), the inner AD control is always unstable. As shown in Fig. 7(b), the phase curves of the system always cross the –180°-line at ωdiv and then at ωres. This kind of phase crossing is called the

(a)

Bode Diagram

-50-40-30-20-10

010

Frequency (Hz)

-180

-270

-90

kAD increases

fresfdiv102 103 104

(b)

Fig. 7. Open-loop Bode plots with dual-loop current control for different ωres and kAD, (a) ωres<ωdiv and (b) ωres≥ωdiv. (See Appendix D for more detail)

first crossing situation in this study. A positive crossing with –180° at around ωres needs to be designed to offset the above two poles under this situation. Therefore, the design constraints are:

1 2 AD

1 P

_ OL

2 2AD1 2 1

1

P

( )( ) 20 lg 0

1( ) 20 lg

[- ]

20 lg 0

g

ref

res

div idivi

div div div res

L L KGM

L K

GMG j

KL L C

L

K

(20)

As can be seen from (20), KP should be neither small nor large in the first crossing situation. Otherwise, the overall system is unstable. The lower and upper limits of KP are separately determined by the two inequalities in (20).

Second, for ωres<ωdiv and KAD> KADMax, the inner AD control is always unstable. Taking C1=17μF as an example, as shown in Fig. 7(a), the phase curves of the system always cross the –180°-line at ωres and then again at ωdiv. This is called the second crossing situation in this study. A positive


Fig. 8. Impact of grid voltage harmonics on the grid current with the increase of C1.

crossing with –180° at around ωdiv is needed in order to offset the above two poles under this situation. Therefore, the design constraints are:

( ) 0

( ) 0res

div

GM

GM

(21)

As can be seen from (21), the constraints for the second crossing situation are opposite those of the first crossing one.

B. Robustness Analysis

1) Case I: the Inner AD Control is Stable In a weak grid, the grid impedance Lg makes the real

resonance frequency ωres_Lg smaller than ωres [26]-[29]. The increase of Lg can be seen as an increase of the grid inductance L2. In (19), replace L2 with L2+Lg. It can be seen that GM(ωres_Lg) is a monotonically-increasing function about L2 (or Lg). As a result, GM(ωres_Lg) is always larger than 0 with an increase of Lg because the initial margin is greater than 0 when Lg is 0, i.e., (19). Therefore, when the inner-loop AD control is stable, the dual-loop system exhibits a high robustness when the grid impedance changes. 2) Case II: the Inner AD Control is Unstable

For the first crossing situation, with an increase of L2 (or Lg), ωres_Lg is always larger than ωdiv or it is decreased to less than ωdiv, depending on the LCL parameters. On the one hand, if the minimum value of ωres_Lg is larger than ωdiv, the criterion to ensure stability is GM(ωres_Lg)<0, in the case of the minimum value of ωres_Lg. By replacing L2 with L2+Lg in (20), the value of Kp has to be largely reduced to ensure that GM(ωres_Lg)<0. Thus, the robustness is poor. On the other hand, if the minimum value of ωres_Lg is less than ωdiv, the criterion for robustness is given in (22) because either (19) or (21) has to be fulfilled with the decrease of the real ωres_Lg.

_ _

_ _

( ) 0 ( )

( ) 0 ( )

res Lg res Lg div

res Lg res Lg div

GM

GM

(22)

Given that GM(ωres_Lg) is monotonically increasing and ωres_Lg is decreasing with an increase of Lg, (22) is equivalent to the condition GM(ωdiv)=0. However, the LCL parameters always change in practice. Thus, there is no accurate solution for (22), and the robustness is difficult to guarantee.

For the second crossing situation, ωres_Lg is always less than ωdiv with an increase of L2 (Lg). Thus, GM(ωres_Lg) is always larger than 0, given that (21) is fulfilled in the initial design.

Because KADMax_Lg (i.e., the new upper limit of KAD considering Lg) increases with an increase of Lg, it is worth noticing that the second crossing situation changes to the situation where the inner AD control is stable. At this time, GM(ωdiv) does not need to be considered. Thus, in order to ensure robustness in this case, it is necessary to make sure that GM(ωdiv) is always less than 0 when KAD>KADMax_Lg. Through the detailed derivations in Appendix C, another range of KAD can be obtained:

21 1

ADMax AD1

1div

div

L CK K

C

(23)

C. Discussion

According to the above studies, if the inner AD control is stable, the design of the dual-loop is the simplest and the system exhibits a high robustness. If the inner AD control is unstable, the design constraints are more complex. Only the second crossing situation can conduct a robust design. In addition, for stability purposes, the amplitude curve needs to have multiple crossings with the 0dB-line if the inner AD control is unstable so that the phase margins at all of the 0dB-crossing frequencies are hard to optimize. As a summary of Section IV, ensuring the stability of the inner AD control is meaningful to reduce the difficulty in the dual-loop design, and the dual-loop current control can achieve a high robustness even under the weak grid case without conducting a compromised design.

V. APPROACHES TO IMPROVE INNER-LOOP AD

STABILITY

Because inner-loop AD stability is critical to optimization of the system control design and improvements of the system performance, several approaches are proposed and investigated based on the expressions of ωres, ωdiv and kADMax.

A. Increasing the Control Frequency fs

As can be seen from (13) and (14), ωdiv and kADMax become larger with an increase of fs. As a result, the system parameters make it easy to satisfy the inner AD criterion in (15). However, it is difficult to increase fs a lot because the maximum value of fs is limited by the complexity of the program and the operation capability of the DSP being used.

B. Reducing the Resonance Frequency ωres

The value of kADMax is increased by decreasing ωres. As a result, this approach makes the inner AD stability easier to achieve. However, changing ωres means changing either the inductance or capacitance. At present, the increases in the filter volume, weight and cost with an increase of capacitance is relatively small compared to an increase of inductance. Thus, increasing C1 is a promising way to decrease ωres.

However, increasing C1 affects the rejection of low-order grid current harmonics. To analyze the impact of C1 on


low-order grid current harmonics, the transfer function from ug to ig is expressed as:

( 2)21 1 AD 1 PWM

( 2)3 21 2 1 AD 2 1 PWM

( 2)1 2 PWM

d sg

g d s

d s

s T Tiu s T T

s T Tc

L C s k C s k eG s

L L C s k L C s k e

L L s k e G s

(24) where the grid voltage proportional feedforward is considered. In the low-frequency region, s2 and s3 in the denominator can be ignored compared with the other items. Therefore, the magnitudes of (24) at low frequencies increase with an increase of C1. As shown in Fig. 8, increasing C1 results in the current harmonics caused by ug to exhibit a tendency to amplify. In summary, this approach has some limitations when the grid voltage contains many low-order harmonics.

C. Reducing the AD Feedback Factor kAD

According to (15), reducing kAD is suitable only when ωres<ωdiv. By ensuring that KAD is less than KADMax, the inner-loop AD becomes stable. However, as seen from Fig. 7, reducing kAD is not conducive to suppressing the resonance peak of the LCL filter. As a result, the grid current may contain resonance harmonics even if the system is stable. Another effect of reducing kAD can be seen from (24). With s2 and s3 removed, the magnitudes of (24) at low frequencies decrease with a reduction of kAD.

D. Reducing the Sampling and Computation Delay Td

Another way to increase ωdiv is to reduce Td, and as in the case of increasing fs, KADMax also increases. Reducing Td needs to modify the DSP program. Taking a DSP TMS320F28035 from Texas Instruments as an example, the existing methods are divided into two types. One is the real-time sampling approach, which is carrier out by shifting the sampling instant close to the loading instant of the modulation wave, as shown in Fig. 9(a). The sampling delay can be reduced to the time of the DSP sampling and the calculation of the modulation wave. However, this method is challenged by the sampling aliasing problem [14], [18]. The other method is the real-time loading approach by shifting the loading instant of the modulation wave close to the sampling instant, as shown in Fig. 9(b). Similarly, the sampling delay is reduced to the time of the DSP sampling and the calculation of the modulation wave. However, this method is challenged by the reliability, e.g., the problem of driver shoot-through [19]. The approach in [19], with the use of dual channel sampling, is able to solve the driver shoot-through problem, and the control delay can be considered completely compensated.

E. Adding a Proper Phase Compensator

Since the control delay causes phase lag, adding a phase compensator in the feedback loop is able to improve the inner AD stability. The phase compensator can be a lead or high-pass filter. Fig. 10 gives the improved control, where

(a) (b)

Fig. 9. Two basic approaches to reduce Td, (a) real-time sampling and (b) real-time loading.

1 ( )C

inv

iuG sPWMk

ADk ( )hG s

Fig. 10. Structure of AD control with phase compensator.

Fig. 11. Compensation angle of HPF with different ωh.

Gh(s) is the phase compensator. The equivalent open-loop transfer function is:

1OL AD PWM( ) ( ) ( )C

inv

ih uG s G s k k G s (25)

In order to not amplify high-frequency noises, |Gh(jω)| at frequencies close to and above fres should be 1. The two 0dB-crossing frequencies are approximately equal to those in (8). Accordingly, PMx1 with Gh(s) is improved as:

11 1

2PM 2 ( 2 )

2d s x

x h xs s

T T fG j f

T f

(26)

The second-order high-pass filter (HPF) is expressed as:

2

h 2

( )( )

( ) 2 ( ) 1h

h h

sG s

s s

(27)

where, ωh and ζ are the turn-over frequency and damping factor of the high-pass filter, respectively.

In order to make |Gh(jω)| at frequencies close to and above fres equal 1, ωh should be smaller than ωres. Moreover, considering variations in the filter parameters and grid impedance, the actual resonance frequency is largely reduced. In this case, ωh should ensure that the resonance components of the sampled signal are not filtered out by the high-pass filter because these components are necessary for active


TABLE II FEATURES OF DIFFERENT APPROACHES

No. Approach Features (besides the stability

improvement) A Increasing fs × Higher requirement of DSP operation

capability B Reducing ωres × Need to rearrange either the

inductance or capacitance × Increase volume and weight, cost or

low-order current harmonics C Reducing kAD Higher rejection of low-order current

harmonics × Difficulty in suppression of resonance

peak D Reducing Td Most effective way to solve the

instability × For real-time sampling, aliasing

causes low-order current harmonics × For real-time loading, careful design

of DSP program for reliability Depend on DSP working mode

E Adding Gh(s) Higher rejection of low-order current harmonics with HPF

× Trade-off design between robustness and compensated phase angle

Poor stability margin due to Gh(s) (but a slight decrease of kp solves this without compromising the bandwidth) , as in Section VI-A

damping purposes [9]. Thus, ωh should be lower than the minimal value of ωres if the grid impedance varies widely. At the same time, ωh is also related with the compensation phase angle of (27). As shown in Fig. 11, the phase angle decreases with a decrease of ωh. In addition, if variations of filter parameters make ωres increase, the phase angle at the real ωres is decreased. As a result, the design of ωh needs to balance the robustness and the leading phase angle.

For the design of ζ, if a small value of ζ is used, the gain of (27) around ωh may exceed 1. Consequently, the high pass filter will potentially arouse harmonics in the case of noise disturbances. Thus, ζ should be larger than 0.6.

To obtain new values of ωdiv and KADMax, the compensation effect by adding Gh(s) is approximately seen as the decrease of Td. That is, the new delay time is equal to Td−Td_decreased, where the reduction Td_decreased can be calculated as:

_ 11

1( 2 )

2d decreased h xx

T G j ff

(28)

F. Summary

The features of all of the approaches are synthesized in Table 2. Since the benefits and limitations are clearly known, the use of several approaches together may be a promising option. For instance, the reasonable decrease in both ωres and kAD (i.e., Approaches B & C) can result in a good balance

DC

AC

DC

-link

C

apac

itor

Fig. 12. Photo of inverter prototype.

Fig. 13. Bode plots with typical dual-loop current control for different control delay.

among volume, cost and current harmonics rejection. This combination is not discussed further since it is just a specific choice of parameters. In addition to the above combination, adding an HPF in real-time sampling (i.e., Approaches D & E) is supposed to solve the aliasing of digital sampling without affecting the active damping of the LCL resonance.

VI. VERIFICATIONS

In order to verify the correctness of the analysis and the feasibility of the presented approaches, experiments are done in a single-phase inverter. The system parameters are in Table 1 with C1=7 μF. The power switches are IGBTs K75T60 from Infineon. The digital sampling and control are implemented in a TI TMS320F28035 DSP. During the tests, the DC side is linked to a voltage source set at 400V. The AC side is connected to the commercial 220V/50Hz power grid. IGBTs IKW40N120T2 from INFINEON are used as the power switches. A photo of the inverter prototype is shown in Fig. 12.

A. Design of the Parameters for the Tests Firstly, a design without considering the digital delay is

shown in Fig. 13 (the solid line). In this case a PI controller is used [1]. The design of the active damping factor follows [4] and [5]. The specific design results are that the proportional gain KP is 7.2, the integral time constant Ti of the PI


controller is 0.0006, and the AD factor KAD is 13. From Matlab, PM is 61.2° and GM is 8.71dB.

1ic P

i

T sG s k

T s

(29)

However, when the delay Td is considered (either Ts or 0.5Ts), the inner AD control no longer satisfies (15) so that a system with only inner AD control is unstable. As a result, the phase crosses the -180° line many times when Td is a one-sample delay (Ts, dash-dotted line in Fig. 13) or half of that (0.5Ts, dotted line in Fig. 13). If the design without a delay is still followed, the system cannot work stably because the required –180°-crossing does not exist. As discussed above, for the sake of stability and robustness, it is better to use improved approaches rather than simply adjusting the control parameters. 1) With Approach A: According to (15), the reassignment of the control frequency fs should satisfy:

2 21

ADMax

2

( )13

sdiv s res

d s

div res

div

Tf

T T

LK

(30)

With the use of (30), fs should be higher than 24.4 kHz to ensure that the inner-loop AD control is stable. From the view of signal sampling, fs should be an integer multiple of the switching frequency. Thus, fs has to be 30 kHz. However, in a DSP with the traditional implementation, the program needs to realize the detection and protection of various variables as well as the calculation of the PWM reference in 0.5/fs (16.7μs). In tests, the operating time required for each interrupt is measured to be 16~18μs. Thus, the burden of the DSP is too heavy if fs is increased higher. In addition, other interrupts in the DSP program also need time to run. In summary, for the prototype, Approach A is not applied. 2) With Approach B: Based on the requirement of (30), C1 has to be increased to 100μF. However, an excessive increase in C1 will amplify the effect that low-order harmonics in the grid voltage have on the grid current. For the prototype, Approach B will not be considered. 3) With Approach C: Approach C is not suitable for the case study because ωres is higher than ωdiv. 4) With Approach D: For this approach, the key question is how to determine the value of the delay time. At first, the lower limit of ωdiv is calculated as 3.826×104 rad/s by the bottom inequality in (30). Then, by substituting the lower limit of ωdiv into (13), the upper limit of Td is obtained. In the case of the parameters in Table 1 (C1=7 μF), the upper limit of Td is 0.116Ts. Therefore, the stability of the inner-loop AD control can be realized by using the real-time sampling or loading approach. It should be noted that the aliasing-induced harmonics in the real-time sampling are fairly large with a larger Td [14]. Thus, Td should be as small as possible. For the case study, the time of iC1 sampling and um calculation in the

Fig. 14. Bode plots with different improved approaches.

i g/ A

i g/ A

i g/ A

u g/V

Fig. 15. Simulation waveforms with different Approaches.

TABLE III PARAMETERS REASSIGNED FOR EVERY APPROACH

Approach Reassigned Parameters

A fs=24.4 kHz

B C1=100 μF

C Do not exist

D Td=0.1Ts (real-time sampling); Td≈0(real-time

loading)

E ωh=6000π rad/s, ζ=0.65

DSP is measured to be 4μs which is a little less than 0.1Ts. For a conservative design, Td is 0.1Ts in the test. 5) With Approach E: First, according to (26), to make the inner AD control stable, the basic principle is that the leading phase provided by the high-pass filter should be at least 56°. In case of ζ=0.6, ωh should be above 3000·2π rad/s. By increasing ζ, the phase angle is increased. For the case study, ωh is 6000π rad/s and ζ is 0.65, when |Gh(jωres)| is 66°.

In summary, the reassigned filter and control parameters are shown in Table III. Approaches D and E are further discussed and tested experimentally, while Approaches A and B are simply tested by simulations.

Fig. 14 shows the effects of the improved approaches. The real-time sampling (Td=0.1Ts, PM=34°, GM=5.9dB) and real-time loading (Td≈0, PM=34.7°, GM=6.43dB) approaches


Fig. 16. Experimental waveforms with traditional dual-loop current control.

both solve the instability caused by the typical dual-loop control. The phase curve with Approach D crosses the –180° line only once, and the stability is easy to guarantee. With Approach E, the phase curve also crosses the –180° line only once, but the gain and phase margins are greatly reduced (PM=4.18°, GM=0.96dB). It is noticed that reductions of the stability margins are yielded because the cut-off frequency is needlessly increased. By adjusting Gc(s) to reduce the cut-off frequency, GM and PM are improved while the bandwidth is still the same as that with Approach D.

B. Simulation Results

Approaches A and B are tested by simulations. As shown in Fig. 15, the traditional control results in resonance in the grid current while Approaches A and B both have the capability to stabilize the system.

C. Experimental Results

Fig. 16 shows the results with the traditional dual-loop current control. The inverter cannot work stably, and there are a lot of resonance harmonics in the grid current, which could potentially trigger inverter protection.

Fig. 17 shows experimental waveforms with the improved approaches. It can be seen that the inverter runs stably with the real-time sampling approach. However, the grid current is affected by aliasing due to the discrete sampling. There are some low-frequency harmonics in the grid current. For the real-time loading approach, a better grid current quality is achieved because the signal sampling is located at the beginning of the control period, which is similar to the traditional control. With Approach E, as shown in Fig 17(c), the stability is improved. Note that a small amount of harmonics can be found in the current waveform, especially at the zero-crossing points, because the stability margins are not satisfactory if Gc(s) is unchanged. By slightly reducing the gain of Gc(s), the high-frequency oscillations at the zero-crossing points in Fig. 17(c)) disappear (the waveforms are not shown again).

It should be mentioned that inverter non-ideal factors (dead-time, turn-on-off delay time, conduction voltage drop,

(a)

(b)

(c)

Fig. 17. Experimental waveforms with improved approaches. (a) Approach D real-time sampling. (b) Approach D real-time loading. (c) Approach E.

etc.) are harmful to the grid current quality. On the premise that the current control is stable with a proper stability margin, using some compensation methods can further improve the grid current quality [30]-[32].

VII. CONCLUSIONS

An in-depth study on the stability of capacitor current feedback AD for grid-connected LCL-filtered inverters is done in this paper. Then, stability criterions for the inner-loop AD and the dual-loop current control are given. Moreover, the robust design of the dual-loop current control is discussed


both when the inner-loop AD is stable and when it is not. Analysis shows that ensuring the stability of the inner-loop AD is beneficial for simplifying the difficulty in dual-loop control design and for improving system robustness. Based on the theoretical analysis, several approaches are presented to improve system stability and robustness. Finally, the correctness of the investigations and the effectiveness of the improved approaches are verified in a practical application. Among the improved approaches, the use of a high-pass filter and the approach of reducing the delay are able to optimize the system using the control parameters designed without considering the delay. It is noted that the phase margin with the high-pass filter approach can be further improved by slightly adjusting the current controller without compromising the bandwidth. Given that DSP capability is much better than in the past, the real-time loading approach or the real-time sampling approach with a high-pass filter is a promising way to simplify the parameter design and to improve the performance.

ACKNOWLEDGMENT

This work was supported by National Natural Science Foundation of China (51477077).

APPENDIX

Appendix A Nyquist stability criterion in a Bode diagram: The

open-loop amplitude- and phase-frequency curves are denoted as L(ω) and φ(ω), respectively. The closed-loop stability is achieved if the following criterion is satisfied:

2 0

N N N

Z P N

(A1)

where, P is the number of open-loop poles with a positive real part; N+ and N− separately denote the times that φ(ω) crosses the (2n+1)π line in the upward and downward directions (i.e., positive and negative crossings, respectively) when L(ω)>0, where n equals 0, ±1, ±2,...

Appendix B The derivation of (14) is given in the following. First, (11)

is changed to be:

1

1

4 2s

x sd s

Tf f

T T

(B1)

Then, using fx1 in (8), KAD=kAD|kPWM| and fsTs=1, (B1) is changed to be:

2 2AD 1 AD 1 41 1 1

2 2 4 2res

d s

K L K L

T T

(B2)

The intermediate calculation steps are:

2 2AD 1 AD 1

2 2AD 1 AD 1

2 2 22AD 1 AD 1 AD 1

22AD 1

2 2AD 1

4 1

2

4 2

4 2 4

4 2 4

4 2 4

res

d s

res div

res div div

res div div

div div res

K L K L

T T

K L K L

K L K L K L

K L

K L

(B3)

At last, the active damping factor should satisfy:

2 22 2

11

AD

2 4 ( )

4

div resdiv res

div div

L LK

(B4)

Appendix C

When the grid impedance Lg grows (equivalently seen as an increase of L2), the resonance frequency decreases till it reaches the minimum value, which is shown in (C1). Therefore, KADMax_Lg also has the maximum value KADMax_Lgmax, which is shown in (C2). The amplitude gain GM(ωdiv) of the system at ωdiv can be expressed as (C3).

min1 1

1res L C

(C1)

ADMax1

_

21 1 1

Lgmaxdiv

div

L C

CK

(C2)

21

2 1 AD 11

P

2 1 AD AD 1

P

1[ ( ) ]

( ) 20lg

[ ( ) ]20lg

divdiv div

divdiv

div div Max_Lgmax

LL C K L

CGM

K

L C K K L

K

(C3)

AD

ADMax

12 2

1

_ A

1

D

1

1

1

1

=

div div

d vLgmax i

LL

L C K C

L

CK K

(C4)

When KAD∈(KADMax, KADMax_Lgmax) and the initial design of

GM(ωdiv) is less than 0, KADMax_Lg may increase over KAD with an increase of L2. 1) If KAD<KADMax_Lg, both the inner-loop stability and the dual-loop system stability are ensured since this situation is exactly the same as Case I. 2) If KAD>KADMax_Lg, the dual-loop stability criterion is (21). To ensure GM(ωdiv)<0 when L2 varies, it is necessary to study the property of GM(ωdiv). With the use of the expression of KADMax in (14), L2 for KAD>KADMax_Lg is expressed in (C4). The function in the absolute value sign of (C3) monotonically decreases and obtains its minimum value (i.e., 0) when L2 reaches the maximum in (C4). Thus, GM(ωdiv) monotonically decreases so that GM(ωdiv)<0 is always ensured and (21) is fulfilled when L2 (considering Lg) increases largely.


When KAD>KADMax_Lgmax and the initial value of GM(ωdiv) is less than 0, KADMax_Lg will never be larger than KAD with an increase of L2 (Lg). Therefore, the phase curve of the system is always in the second crossing situation. Obviously, GM(ωdiv) monotonically increases about L2 (Lg) so that GM(ωdiv) eventually exceeds 0 with an increase of L2 (Lg). As a result, the stability of the system cannot be guaranteed for a wide variation of Lg.

Appendix D

The reason for the differences (i.e., the phase shift around fdiv) in Fig. 7, in different KAD and ωres cases is explained.

Using s=jωdiv, (18) is written as:

_ OL

( 2)P

( 2)3 21 2 1 AD 2 1

1 2

g

ref

div d s

div d s

idivi

j T T

j T Tdiv div

div

G j

K e

jL L C K L C e

j L L

(D1)

where:

( 2)

cos ( 2) sin ( 2)

cos( 2) sin( 2)

div d sj T T

div d s div d s

e

T T j T T

j j

(D2)

Then, (D1) changes to be:

_ OL

P3 2

1 2 1 AD 2 1 1 2

P3 2

1 2 1 AD 2 1 1 2

P2 2

1 2 1 AD 1

g

ref

idivi

div div div

div div div

div div div res

G j

jK

jL L C jK L C j L L

K

L L C K L C L L

K

L L C K L

(D3)

According to (D3), the gain is positive in the case of ωres<ωdiv and KAD<KADMax; negative in the case of ωres<ωdiv

and KAD>KADMax; and negative in the case of ωres≥ωdiv. That is, the open-loop gain at ωdiv is a positive factor if the inner AD control is stable, while it is a negative factor if the inner AD control is unstable. Therefore, the phase curves in Fig. 7 cross different lines at fdiv in different cases.

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Jinming Xu was born in Xuzhou, China, in 1987. He received his B.S. degree in Electrical Engineering from the Nanjing University of Aeronautics and Astronautics (NUAA), Nanjing, China, in 2009. From 2009 to 2011, he was a M.S. candidate in Electrical Engineering at NUAA, where he is presently working towards his Ph.D. degree.

His current research interests include grid-connected inverters and control strategies.

Shaojun Xie was born in Hubei, China, in 1968. He received his B.S., M.S., and Ph.D. degrees in Electrical Engineering from the Nanjing University of Aeronautics and Astronautics (NUAA), Nanjing, China, in 1989, 1992, and 1995, respectively. In 1992, he joined the Teaching and Research Division of the Faculty of Electrical

Engineering, NUAA, where he is presently working as a Professor in the College of Automation Engineering. In the past five years, he has authored or coauthored over 100 technical papers published in journals and international conference proceedings. His current research interests include aviation electrical power supplies and power electronic conversions.

Binfeng Zhang was born in China, in 1991. He received his B.S. degree in Electrical Engineering from the Nanjing University of Aeronautics and Astronautics (NUAA), Nanjing, China, in 2013, where he is presently working towards his Ph.D. degree. His current research interests include grid-connected inverters and the application

of wide bandgap devices.

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