SRS News SRU Revision, New Hybrids, DTC, Firmware, …
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Transcript of SRS News SRU Revision, New Hybrids, DTC, Firmware, …
120/02/12
SRS NewsSRU Revision, New Hybrids, DTC, Firmware, …
Sorin Martoiu, CERN PH/DT
SRS News, Sorin Martoiu, CERN 2012, 9th RD51 Collaboratin Meeting
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Outline
SRU revision 2 (PCB produced, assembly) New Hybrids
New APV Hybrids produced (micro HDMI connector) VFAT2 and BEETLE hybrids under design
SRS Firmware Evolution New features for near-future upgrades
New APV firmware options (Zero-suppression code) Design of the DTC link
LVDS channel tests Towards an industrial SRS design
SRS News, Sorin Martoiu, CERN 2012, 9th RD51 Collaboratin Meeting
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SRU rev2
SRU revision 1 features: 4 x SFP+ (GbE, ALICE DDL, ATLAS S-Link, …) SO-DIMM DDR3 (2GB) TTC Remote configuration (BPI Flash)
SRU revision 2 upgrades: 10 GbE PHY 3 x SFP+ (up to 5 Gbps each) Jitter-cleaner PLL for TTCrx clock ( < 50 ps peak-to-peak jitter)
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SRU rev2New 10GbE PHY New PLL
(TTC CLK)
3 x SFP+
10 G
bE
DDR3 SODIMM
Virtex 6FPGA
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New Hybrids
New APV Hybrid
VFAT2 Hybrid
BEETLE Hybrid
New Micro HDMI connector
SRS News, Sorin Martoiu, CERN 2012, 9th RD51 Collaboratin Meeting
• Initial production yield < 90%• Some simple assembly issues and some test samples included in the yield. • Final result may improve
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New Hybrids
New APV Hybrid
VFAT2 Hybrid
BEETLE Hybrid•2 hybrid versions (with or without discharge protection)•Power via detector PCB (option)•Signals via detector PCB (option for the short version only)•One hybrid per HDMI cable
•Work in progress (layout finalization)
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New Hybrids
New APV Hybrid
VFAT2 Hybrid
BEETLE Hybrid•Under design at Weizmann Institute, Israel•Comparator output OR/MUX via radtol CPLD•Master-slave versions for analog readout mode
•Work in progress (layout finalization)
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Firmware Evolution
Test modules Used for QA tests in manufacture process
DTC Link Protocol definition
Synch Module (clock synchronization of multiple FEC cards) On-board clock (free running) DTC clock (SRU clock) Ethernet clock (TX clock of the Network Switch)
Design Partitioning (Xilinx tool migration) Easy integration of new applications/front-ends Partial reconfiguration of the application module (limited support for
Virtex 5 family)
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Firmware Evolution
Ethe
rnet
Cor
eD
TCLi
nk
Clock UnitTest & Init
SC C
ore
Dat
a pa
th
SC BUS
Monitoring System SC
App Slow Control
Readout Control
FE CardInterface
DataProcessor
PacketBuilder
EEPROMoCVoltage
Current
Application Layer (Reconfigurable partition*)
System Layer (Fixed partition)
* Xilinx dynamic reconfiguration support is limited for Virtex 5 FPGAs
On-board clock
DTC clock
Ethernet clock
DAQFE
SRS News, Sorin Martoiu, CERN 2012, 9th RD51 Collaboratin Meeting
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APV Signal Processor
EventBuild- Frame Decode
- Pedestal Corr.- Zero Suppress.
0 - 3 kB/ch
BYPASS
Additional Features:Clock phase calibrationPedestal and noise calibrationDouble input buffer (samples < 15)Common-mode channel (future)
Warnings:•Due to resource limitations the (old) raw ADC mode and Zero-suppression mode cannot be implemented in a single firmware version.•A single channel bypass mode is provided•Common mode rejection not implemented. A common-mode channel output is foreseen for later revision
50kB
50kB
50kB
50kB
Designed by Raffaele Giordano, INFN Napoli
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Clock phase calibration Wrong clock-edge sampling; resync using the on-hybrid PLL25 chip
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APV Frame Decoder
sync pulses headers
Analogue data (128 channel samples)
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APV Zero SuppressionAnalogue data (128 channel samples)
100
-1100
-1000
-900
-800
-700
-600
-500
-400
-300
-200
-100
0
Time110 1 2 3 4 5 6 7 8 9 10
Plot 9
Plot 10
Plot 11
Plot 12
Plot 13
Plot 14
Plot 15
Plot 0
Plot 1
Plot 2
Plot 3
Plot 4
Plot 5
Plot 6
Plot 7
Plot 8
dataout
•Pedestal correction•Zero suppression (integral discrimination)
• Thresholds are automatically calculated from noise data
•User can read or write pedestal and noise data via slow-controls
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DTC Links
Physical Interface•LVDS buffers (< 2 Gbps, no signal conditioning)•CAT 5E/6/7 FTP
SRU 40 x DTC links
•2 x LVDS TX (clock, trigger, control)
•2 x LVDS RX (data, trigger, control)
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DTC LVDS Link Tests 100 MHz DDR PRBS pattern (400Mbps)
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DTC LVDS Tests (Preliminary)Cable
LengthCable Type Max
Speed1
Raw Bandwidth
Data Bandwidth (20% protocol overhead)
2.5 m CAT-5E UTP 700 MHz2 2.80 Gbps 2.24 Gbps
2.5 + 10 m CAT-5E FTP 460 MHz 1.84 Gbps 1.47 Gbps
2.5 + 15 m CAT-6 UTP 300 MHz3 1.20 Gbps 0.96 Gbps
26 m CAT-7 FTP 200 MHz 0.80 Gbps 0.64 Gbps1Only one FEC card tested. Results may be different for a representative population; 2FPGA design limit3Failed at 280 MHz. Safe value 260 MHz (1.04 Gbps; 0.8 Gbps effective)
50 m DTC link not feasible Signal conditioners might be an option Data bandwidth higher than expected at moderate cable length ( > 1 Gbps)
SRS News, Sorin Martoiu, CERN 2012, 9th RD51 Collaboratin Meeting
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DTC Protocol Proposal
Channel interleaving Trigger, busy, … transmitted with high priority and guarantied fixed latency. Data transmitted over regular (low priority) channel.
8b/10b encoding DC balance (improves channel performance) Error detection “Out-of-band” signaling (comma characters – synchronization, framing control, …)⚠ 20% overhead
Versatile Design (Auto-negotiation, full control of slave DTC via SRU)
8b/10b
Framing Control
10b/8b
Frame detection
Latencycorrection
commas commasctrl
High priority ch.Trigger/Busy/…
Low priority ch.Data/Control DTC TX DTC RX
Ch. requestFlow control
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DTC Protocol Proposal
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SRS in Industrial Standard
Discussions with EICSYS GmbH (Hamburg) studying the possibility to develop SRS systems in industrial standards (ATCA, mTCA, ..)• Full industrial certification (CE, mechanical, EMI, …)• Runtime reliability (>99.9% uptime)• System Management
AdvancedTCA
2020/02/12
Thank you!
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Additional Slides
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typedef unsigned char BYTE; // 8-bit wordtypedef unsigned int WORD32; // 32-bit wordtypedef unsigned short int WORD16; // 16-bit wordtypedef signed short int INT16; // 16-bit signed int
struct APV_HEADER{ BYTE APV_ID; // APV Identifier number on the FEC card (0 to 15) BYTE N_CHANNELS; // the number of channels which will be following the header BYTE N_SAMPLES; // the number of samples per channel BYTE ZS_ERROR; // Error code from the Zero Suppression Block, meaning have to be defined WORD16 FLAGS; // bit 0 : ‘0’ – Classic zero suppression, ‘1’ – Zero suppression with peak finding // bits 1 to 15 are still reserved for future use WORD32 RESERVED; // 32 bits reserved for future use};
struct CHAN_INFO{ BYTE RESERVED; // 8-bits reserved for future use BYTE CHAN_ID; // Channel identifier, // APV physical channels are 0 to 127, // 128 could be used for the common mode average // 129 for error codes from the APV (pipeline address(8 bits) & error bit) INT16 CHANDATA[N_SAMPLES]; // 16 bit words, actual data will be 13-bits wide};
SRS ZS Data Format
Author: Raffaele Giordano Ver. 0 25 Jan. 2012
Data types and structures definition
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APV Header
CHAN_INFO
CHAN_INFO
CHAN_INFO
N_CHANNELS CHAN_INFO structures
At each read-out from the ZS buffer for a given APV, the ZSwill answer with this sequence.
1. In classic zero suppression mode, the CHANDATA array contains the actual samples.
2. In peak finding mode, the CHANDATA array has always two elements: CHANDATA[0] = peak value CHANDATA[1] = peak time
Read-out Sequence
Author: Raffaele Giordano Ver. 0 25 Jan. 2012