Spry149c.lte.WhitePaper

8/3/2019 Spry149c.lte.WhitePaper

1/12

Introduction

With the consumer drive or more and more

data, worldwide operators are experiencing

an unprecedented need or wireless band-

width growth. Fortunately, the industry along

with standards bodies such as 3GPP is evolv-

ing support such demand. LTE has emerged as

the technology o choice or operators to meet

this exponential growth. As LTE deployment

becomes a reality, base station manuacturers

are avoring system-on-chip (SoC) architectures

to keep operator network costs low while main-

taining and improving service.

Supporting a successul LTE transition requires

a number o innovations in base station SoC

design. Texas Instruments (TI) has developed a

powerul and innovative multicore SoC architec-

ture called KeyStone that is designed to optimize

WCDMA and LTE perormance while reducing

base station cost and power. For wireless base

station applications, an essential part o KeyStone

is the implementation o confgurable coproces-

sors or the physical layer (PHY) or Layer 1 o the

wireless standards. This paper describes how TIs

TCI6618 wireless system-on chip (SoC), based

on the KeyStone multicore SoC architecture, pro-

vides an optimized PHY LTE solution, streamlines

the development cycle or manuacturers, and

demonstrates the potential or eNodeB solutions

with competitive dierentiation, lower capital ex-

penditure and operating expenses.

TMS320TCI6618 - TIs

high-performance LTEphysical layer solution

The exponential growth in the use o mobile data worldwide has posed signicant challenges

to wireless operators. Fortunately, wireless technology has continued to evolve, and Long

Term Evolution (LTE) has become the worldwide standard o choice to meet the challenges.

The top 25 worldwide wireless operators have chosen to deploy LTE; some o them started

trials in 2010, with multiple market infection point growth expected in 2012. LTE promises

better use o the operators spectrum by improving spectral eciency; this means more bits

per Hertz than previous technologies. Operators must deploy LTE solutions at a rate that

keeps up with the data deluge all while keeping the cost per bit to a minimum, reducing the

carbon ootprint, and providing ease o migration rom 3G to LTE.

The changes required to LTE systems present new challenges or operators, base station

vendors, and their suppliers. Texas Instruments has developed a powerul and innovative new

system-on-a-chip (SoC) architecture designed to reduce costs or LTE products and enable

manuacturers to benet rom cutting-edge base station technology. The KeyStone multicore

SoC architecture builds upon TIs eld-proven multicore DSP platorms and includes an

innovative new foating-point architecture and coprocessors or 4G systems. Adding to the

computational improvements are innovations to the backplanes and internal data movement,

which are critical to achieving ull perormance rom a high-speed 4G SoC. With TIs new

architecture, the industry will advance more rapidly towards deployments that enable the

high-value eatures o 4G systems.

LTE supports fexible channel bandwidths (1.4 20 MHz) as well as requency-division

duplexing (FDD) and time-division duplexing (TDD) to allow fexible deployment around

spectrum ownership. The oundation o the LTE communication protocol stack is the physical

layer (PHY), sometimes reerred to as Layer 1. The PHY layer is the basis o solid base

station-to-mobile device connectivity; without great wireless connectivity, calls drop, down-

loads ail, and videos stall.

The advanced PHYs in the TCI6618 are the industrys gold standard or reliable

perormance, and TIs Layer 1 PHY technology is based on eld-proven, congurable

coprocessors that support all popular wireless standards. This enables the migration rom

3G to 4G on a common platorm, making the transition to 4G appear seamless.

Zhihong LinStrategic marketing manager

Wireless base station inrastructure

Greg WoodApplication manager

Wireless base station inrastructure

W H I T E P A P E R


2/12TMS320TCI6618 - TIs high-performance LTE physical layer solution February 201

2 Texas Instruments

LTE is the latest Third Generation Partnership Project mobile standard. LTE realizes major technology

advances over 3G mobile technologies and oers peak downlink rates o at least 100 Mbps and peak uplink

rates o at least 50 Mbps or the 20-MHz spectrum.

The PHY interaces with Layer 2 (the media access control [MAC] layer) and Layer 3 (the radio resource

control [RRC] layer) and oers data transport services to higher layers. PHY handles channel coding, PHYhybrid automatic repeat request (HARQ) processing, modulation, multi-antenna processing, and mapping o

the signal to the appropriate physical time-requency resources.

LTE downlink PHY processing accepts data and control streams rom the MAC layer in the orm o

transport blocks and begins processing by calculating the cyclic redundancy check (CRC) and attaching it

to the transport block. I the transport block size is larger than the maximum allowable code block size o

6,144 bits, code block segmentation is perormed. A new CRC is calculated and attached to each code

block beore channel encoding. Figure 1 illustrates the major unctional blocks in the LTE downlink.

Antennas Antennas

Resource blockmapping

Resource blockmapping

CRC attach

Code blocksegmentation

Turbo encoding

Rate matching

HARQ combining

Code blockconcatenation

Scrambling

Modulation

Antenna mapping

Transport block (s)Transport block (s)

CRC attach

Code blocksegmentation

Turbo encoding

Rate matching

HARQ combining

Code blockconcatenation

Scrambling

Modulation

Fig. 1 -LTE downlink transport channel processing

LTE radio interface

architecture



Texas Instruments

Turbo encoding provides a high-perormance orward-error-correction scheme or reliable transmission;

rate matching perorms puncturing or repetition to match the rate o the available physical channel resource;

and HARQ provides a robust retransmission scheme when the user ails to receive the correct data. Bit

scrambling is perormed ater code-block concatenation to reduce the length o strings o 0s or 1s in a

transmitted signal to avoid synchronization issues at the receiver beore modulation.

Various modulation schemes (quadrature phase shit keying [QPSK], 16 QAM [quadtrative amplitude mod-

ulation], or 64 QAM) are used or LTE layer mapping, and precoding supports multi-antenna transmission.

Finally, the resource elements o orthogonal requency-division multiplexing (OFDM) symbols are mapped to

each antenna port or air transmission.

LTE leverages many advanced technologies used in 3G HSPA+ (high-speed packet access), like turbo coding,

HARQ, and multi-antenna schemes. LTE oers a solution or 20 MHz o 100 Mbps on the downlink, 50 Mbps

uplink and higher with multi-antenna signal processing schemes. TIs TCI6618 solution supports two sectors

20 MHz, 2x2 multiple input, multiple output (MIMO) solution o 300 Mbps downlink and 150 Mbps on the

uplink, with signal processing overhead or value add and advance algorithms. In addition, LTE uses OFDM

and both downlink and uplink multiple-input/multiple-output (MIMO) technology to provide signicant

perormance improvements over 3G systems.

OFDM transmission LTE uses OFDM or radio transmission, providing a robust transmission mechanism

with protection against degradation rom severe channel conditions, narrow-band co-channel intererence,

and intersymbol intererence and ading. It also delivers high spectral eciency and low sensitivity to time

synchronization errors.

LTE downlink processing uses multicarrier OFDM transmission with a cyclic prex. In the uplink,

wide-band single carrier OFDM transmission with a cyclic prex reduces the variation in the instantaneous

power o the transmitted signal. The ast Fourier transorm (FFT) provides low complexity and ecient

implementation or OFDM modulation and demodulation.

LTE technology

evolution


4/12

TCI6618 theLTE enabler

TMS320TCI6618 - TIs high-performance LTE physical layer solution February 2011

4 Texas Instruments

IDFT

MIMOchannel

estimation

Softslicer

Descramblerchannel

de-interleaver

Rx bit rateprocessing

User 1 data

User 2 data

IDFTSoft

slicer

Descramblerchannel

de-interleaver

Rx bit rateprocessing

UE 1

UE 2

Cyclic prefix

Cyclic prefix

Tx bit rateprocessing

Tx bit rateprocessing

Ref. signal/Data signalseparation

Reference signal processing




Channelinterleaverscrambler

Channelinterleaverscrambler

Modulationmapper

Modulationmapper

DFT

DFT

Resourceelementmapper

Resourceelementmapper

IFFT

IFFT

Cyclicprefix

removalFFT

UL MIMOreceiver

Resourceelement

de-mapper

Cyclicprefix

removalFFT

Resourceelement

de-mapper

Cyclicprefix

removalFFT

Resourceelement

de-mapper

Cyclicprefix

removalFFT

Resourceelement

de-mapper

Fig. 2- LTE MIMO channel model

MIMO technology Smart antenna technology using MIMO antennas is adopted in LTE at both the

transmitter and receiver to improve perormance. MIMO oers signicant increases in data throughput

and coverage without additional bandwidth or transmit power, providing higher spectral eciency and link

reliability against ading. Figure 2 illustrates the LTE 2x4 uplink MIMO channel model and receiver handling.

Multiple antenna uplink MIMO receiver techniques can help increase the signal-to-noise ratio.

Maximum-ratio combining (MRC) is an eective antenna-combining strategy when the receiver is

primarily impaired by noise. In intererence-dominate-channel conditions, a minimum mean square error

(MMSE)-combining technique is a better approach to determine the antenna weighting vector that minimizes

the mean square error. Floating-point implementations o MMSE MIMO equalization can signicantly reduce

computational complexity and provide high perormance, resulting in an ecient LTE MIMO receiver.

The TCI6618 SoC is a member o TIs TMS320C66x DSP multicore generation. Based on TIs new KeyStone

multicore architecture, it is designed or high-perormance wireless inrastructure applications and provides

a perect t or LTE design challenges. Figure 3 illustrates the eatures and processing elements o the device.


5/12

The KeyStone multicore architecture is the rst to provide a high-perormance structure or integrating

reduced instruction set computer (RISC) and DSP cores with application-specic coprocessors and I/O.

KeyStone is the rst multicore architecture that provides adequate internal bandwidth or nonblocking and

zero-delay access to all processing cores, peripherals, coprocessors, and I/O. This is achieved with our

main hardware elements: Multicore Navigator, TeraNet, Multicore Shared Memory Controller, and Hyperlink.

Multicore Navigator is an innovative packet-based manager that controls 8,192 queues. When tasks are

allocated to the queues, Multicore Navigator provides a hardware-accelerated dispatch that directs tasks

to the appropriate hardware available. The packet-based SoC uses the 2-Tbps capacity o the TeraNet

switched central resource to move packets.

The Multicore Shared Memory Controller allows processing cores to access shared memory directly

without drawing rom TeraNets capacity, so packet movement cannot be blocked by memory access.

Hyperlink provides a 50-Gbps chip-level interconnect that allows SoCs to work in tandem. Its low-protocol

overhead and high throughput make Hyperlink an ideal interace or chip-to-chip interconnections. Working

with Multicore Navigator, Hyperlink dispatches tasks to tandem devices transparently and executes tasks as

i they are running on local resources.

TCI6618 key

features for LTE

Multicore Navigator

IPY 4/Y 6fast path

IPsec/SRTP

GTP/SCTP

IEEE 1588

Network coprocessor

RoHC

QoS

Air ciphering

RLC/MAC

Scheduler Fast path

Layer 2 coprocessor

Layer 1 acceleration

PUCCH

Interleaverde-interleaver

Scramblerde-scrambler

Ratematching

Modulator

Uplinkchip rate

Interferencecancellation

Viterbidecoder

Turboencoder

HARQcombining

CRC

Convolutionencode

Ratede-matching

De-modulator

Downlink

chip rate

TFCI CQIdecoder

FFT/DFT

Turbodecoder

TeraNet

Memory system

Multicore shared memorycontroller (MSMC)

2MB shared memory

64-bitDDR3EMIF

System elementsPower

management System monitor

Debug EDMA

Peripherals and I/O

SRIO4x

SGMII2x

UART

Gig Eswitch

SPICPRI/OBSAI

PCIe2x

I2CHyperLink

1 MB L2cache

1 MB L2cache

1 MB L2cache

RSA

C66x DSP

CorePac

CorePac

CorePac

CorePac

1 MB L2 cache

RSA

Fig. 3- TMS320TCI6618 block diagram


Texas Instruments


6/12

C66x cores The TCI6618 has our 1.2-GHz C66x cores that support both xed- and foating-point

arithmetic operations. It oers 153.6 GMACs per second or xed point and 76.8 GFLOPs per second or

foating point at 1.2 GHz. The C66x instruction-set architecture adds 90 new high perormance instructions,

especially foating-point instructions and vector-signal-processing instructions, supporting two-way single

instruction multiple data (SIMD) operation or 16-bit data and our-way SIMD or 8-bit data. The very-long-

instruction word architecture supports eight simultaneous issues and is optimized or complex arithmetic and

matrix processing. Its reduced latency foating-point capability, together with a our times improvement in

MAC perormance, accelerates LTE MIMO equalization and improves most DSP processing required or LTE.

BCP A bit rate coprocessor (BCP) is a multi-standard acceleration engine that ofoads the entire bit rate

processing in the wireless signal chain. The BCP accelerates the ollowing processing unctions:

Modulation

Demodulation

Interleaving

De-interleaving

Turboandconvolutionencoding

In addition to ofoading the DSP cores rom the processing o these unctions, the BCP also enables

advanced receiver algorithms such as turbo intererence cancellation. Turbo intererence cancellation can

increase the SNR by 3 dB, which increases the spectral eciency up to 40 percent, a key perormance

metric or wireless systems. The BCP ofoads approximately 15 GHz o DSP cycles while delivering downlink

throughput o 2.2 Gbps and uplink throughput o 1.1 Gbps.

TCP3d The Turbo-Decoder Coprocessor 3 (TCP3d) is a programmable peripheral or decoding LTE turbocodes in uplink processing. The inputs into the TCP3d are channel-sot decisions or systematic and parity

bits, while the outputs are hard decisions. TCP3d generates the turbo interleaver table, perorms turbo decod

ing, and supports code-block-based CRC calculations. TCP3d is seven times aster than its prior generation

TCP2 with very small driver overhead. The TCI6618 contains three TCP3d coprocessors with a total through-

put o up to 582 Mbps at six iterations.

TCP3e The Turbo-Encoder Coprocessor 3 (TCP3e) is a programmable peripheral or encoding LTE turbo

codes or downlink processing. The inputs into the TCP3e are inormation bits and the outputs are encoded

systematic and parity bits. It supports code-block-based CRC, turbo encoding, and turbo interleaver tablegeneration. TCP3e can ofoad 450-Mbycles per second CPU processing at 150 Mbps downlink throughput.

The TCI6618 has our TCP3e coprocessors with a total throughput up to 2572 Mbps.

FFTC The ast Fourier transorm coprocessor (FFTC) is an accelerator that is loosely coupled with the DSP

cores. It is attached to the TeraNet and uses Multicore Navigator to input and output packets requiring FFT

unctions. FFTC has cyclic prex removal and insertion eatures that can be programmed to ignore or add


6 Texas Instruments

Ratematching

Ratede-matching

CRCattaching

Decodingofcontrolchannelinformation


7/12

samples in the beginning o the packet data; this allows a seamless interace between the antenna interace

and FFTC without requiring sotware to perorm the cyclic prex handling. FFTC can also apply a requency

shit o the input data according to LTE requirements. The ollowing use cases illustrate examples where

FFTC is used in LTE:

Front-endFFTforon-timesymbolprocessing,includingcyclicprexremovalandfrequencyshift

DiscreteFouriertransform(DFT)/inversediscreteFouriertransform(IDFT)forchannelestimation

DFT/IDFTforchannelsounding

DFT/IDFTforfrequencyoffsetcompensationandestimation

IDFTforgeneraluserde-mapping

IFFTfordownlinkandcyclicprexextension

DFTandIDFTforphysicalrandomaccesschannel(PRACH)processing

DFT/IDFTforinterferencerejectioncombiningprocessing

The TCI6618 has three FFTC units with a combined maximum throughput o 1,900 Mcarriers per second.In a LTE system with 20-MHz bandwidth, 2x2 MIMO conguration, this FFTC cluster ofoads more than 1.6

GHz o DSP core processing. In other words, it saves more than one ull DSP core o SoC resources.

RSA The Rake Search Accelerator (RSA) is used or LTE block code decoding. The TCI6618 has two RSAs

tightly coupled on each o two DSP cores. RSA provides hardware acceleration or correlation and search

algorithms, allowing ecient implementation o LTE uplink control inormation (UCI) over physical uplink

shared channel (PUSCH) decoding. Using RSA saves more than 1 GHz o DSP processing or UCI over PUSCH

decoding algorithm.

AIF2 The TCI6618 antenna interace 2 (AIF2) is a proprietary peripheral module that supports transers o

baseband in-phase and quadrature (IQ) data between uplink and downlink baseband DSP cores and high-

speed serial interaces connecting to a digital radio ront end. AIF2 supports LTE requency-division duplexing

(FDD), time-division duplexing (TDD), and both Common Public Radio Interace (CPRI) and Open Base Station

Architecture Initiative (OBSAI) protocols. AIF2 supports six links; each link has a 6-GHz SERDES and 64

maximum antenna carriers per link.

AIF2 has Multicore Navigator built in and a direct connection to FFTC, which provides low latency antenna

trac or LTE systems. AIF2 also has programmable radio timers or rame timing and synchronization to

support multiple standards. It provides 12-Gbps maximum Ingress bandwidth and 12-Gbps maximum Egress

bandwidth.

Network coprocessor The network coprocessor provides Ethernet packet acceleration and security ac-

celeration mainly used in LTE Layer 2 processing. Its built-in CRC engine can be used or LTE PHY transport

block CRC calculation.

Efcient FFTC ront-end data dispatching The KeyStone multicore architecture enables a seamless

interace between AIF2 and FFTC with no intervention required rom sotware running on the DSP core. It also

supports multicore load balancing using the Multicore Navigator inrastructure.


Texas Instruments



8 Texas Instruments

AIF2 and FFTC are optimally designed or LTE OFDM processing. Both continue the Multicore Navigators

packet direct memory access (DMA) engine enabling a DSP core intervention-ree data path between AIF2

and FFTC with direct connection through queues.

Figure 4 illustrates the use o Multicore Navigator to achieve load balancing, scheduling, system

partitioning, and memory usage reduction in LTE uplink symbol processing.

In this example, our antenna streams are ed into FFTC, with the partition and scheduling inormation

programmed into the FFTC input queue descriptors. Each core has three dedicated FFTC output queues

with desired antenna and data symbol inormation reallocated to dispatch to dierent cores on a per-packet

basis using Multicore Navigator.

By using Multicore Navigator queue descriptor header protocol-specic inormation, FFTC output data

is sorted with one queue receiving FFTC output data symbols and one queue receiving the output pilot

symbol. A third queue contains the symbol data that interrupts a core to start data processing. The core

can eciently process the ront-end FFTC data without any data preprocessing overhead. The FFTC provides

load balancing by routing a portion o the data and pilot symbols to each core that will be perorming channe

estimation and equalization.

By using Multicore Navigator queues or FFTC output data, Layer 2 memory space can be saved by

employing multisegment host packet descriptors. Undesired guard tones beore and ater the primary

symbols can be stored in segments o memory that are immediately recycled with each transer. Only the

useul data (primary symbols) are stored in Layer 2 or later processing. This results in a 50 percent

memory-buer reduction or FFTC ront-end processing. Figure 5 illustrates this memory reduction using

Multicore Navigator queue-linked descriptors.

Fig. 4- Load balancing, scheduling and system partitioning using Multicore Navigator

L2Core0

FFT output

Uplink PHY processing

L2Core

1

L2Core2

L2Core3

Queuemanager

Data symbol queue

Pilot symbol queue

Interrupt queue

FFTCAIF


9/12

LTE solutions

with the TCI6618


Texas Instruments

Buffer pointerlocation in L2

Linked buffer descriptorin data symbol queue

Useful data

buffers

. . .

. . .

Guard tonelocation

Left guardtone pointer

Data pointer

Right guardtone pointer

Fig. 5- Memory reduction with Multicore

Navigator packet queue

The TCI6618 platorm development kit (PDK) contains drivers or the BCP, FFTC, TCP3d, TCP3e, Multicore

Navigator, RapidIO, network coprocessor, enhanced direct memory access (EDMA), and chip

support library. It enables an excellent out-o-box user experience and shortens R&D development cycles.

TI also provides LTE PHY sotware, oering building blocks or customer PHY solutions that are highly

optimized or the C66x cores. The BCP ofoads the entire bit rate processing and PUCCH ormat 2, 2a, and

2b decoding in hardware. The LTE library includes sotware or PUSCH symbol, PUCCH ormat 1, 1a, and

1b decoding and PRACH receiver processing, and physical downlink shared channel (PDSCH) symbol rate

processing. Figure 6 shows the complete downlink PDSCH handling using the TI LTE library with TCI6618

accelerators.

Fig. 6- PDSCH processing

Modulationmapper

ScramblingCode block

concatenation

From L2CRC

attachTurbo

encoding

Bit rate processing

Symbol rate processing

FEC blocksegmentation

Ratematching

Primary/secondarysync signalgeneration

Referencesignal generation

Resource mappingpattern generation

Physicalresource mapper Precoding

Layermapping

IFFTAIF

Accelerated by TCI6618 HWLegend

Provided by TCI6618 LTE Lib SW


10/12

The FFTC can also be used or channel estimation to ofoad DSP processing. In LTE, channel estimation is

perormed based on a reerence signal (the ourth symbol in a resource block) embedded in the uplink rame

TIs LTE library sotware provides channel estimation unctions perormed at each data-carrying resource

element in a subrame.

The rst stage o channel estimation can take advantage o FFTC to construct the requency smoothing

estimator. Perorming IDFT translates channel estimates rom the requency domain to the time domain

and uses a rectangular window to cut o the time-domain channel taps to obtain the time-domain channel.

Optionally, a threshold can be used to reduce the noise. Aterwards, perorming a DFT generates the

requency-domain channel estimates. The second stage o the channel estimates can be calculated on a

per-subcarrier basis through linear interpolation/extrapolation o the estimation results rom the rst stage.

Figure 8 shows the PUSCH channel estimation process.


10 Texas Instruments

LTE uplink processing requires signicant CPU cycles or PUSCH channel estimation and equalization.

Depending on the number o antennas, the C66x expanded instruction set architecture and foating-point

arithmetic computations provide as much as a 4x cycle reduction or the MRC equalizer relative to the

C64x+ architecture. With foating-point calculations, more ecient algorithms like block-wise matrix

inversion can be used to achieve the same perormance and with up to 5x cycle reduction than the more

complex xed-point Cholesky decomposition algorithm or the MMSE MIMO equalizer.

The control channel decoding provided by the BCP ofoads a large number o sotware cycles and provides

better perormance than algorithms typically used in sotware. In some cases, this can save up to 1.4 GHz o

DSP processing, equivalent to more than a core o DSP savings. Figure 7 shows PUSCH processing using the

TCI6618 and its highly optimized LTE library sotware.

Fig. 7- PUSCH processing

CPRI

To L2

MRC orMMSE MIMO

equalizerFFT IDFTAIF De-channelization

Channel

estimation

Frequencyoffset

compensation

CRCDe-

segmentationTurbo

decoding

RSAUCI overPUSCH

Control infoover PUSCH

Rate De-matching HARQ

combining

De-interleavingdescrambling

de-concatination

Accelerated by TCI6618 HW acceleratorsLegend Provided by TCI6618 LTE Lib

Bit rate processing

Symbol rate processing


11/12

The FFTC can also be used in PUSCH channel requency oset compensation and estimation, as well as

in various stages o uplink PRACH processing. Two FFTC accelerators in the TCI6618 can greatly ofoad LTE

signal processing rom DSP cores. By leveraging the TI LTE library sotware on C66x DSP cores and ully

utilizing TCI6618 hardware accelerators, LTE PHY processing o the Physical Uplink Shared Channel (PUSCH),

Physical Uplink Control Channel (PUCCH), Physical Downlink Shared Channel (PDSCH), Physical Downlink

Control Channel (PDCCH) and Physical Random Access Channel (PRACH) channels can be integrated into a

single TCI6618 device.

The TCI6618 supports FDD LTE or two sectors o 20 MHz bandwidth, 2x2 MIMO with throughput o 150

Mbps downlink and 75 Mbps uplink using advanced receiver algorithms.

The KeyStone SoC multicore architecture and unmatched TCI6618 system, peripheral and accelerator

bandwidth and throughput bring LTE mobile broadband into aordable reality and enable cost-eective and

best-perormance LTE solutions to the market.

The TCI6618 is a product o continuous innovation built on top o TIs years o wireless base station system

knowledge and eld-proven technology. TIs KeyStone SoC architecture provides highest throughput and

uture-proo architecture or LTE and its continuous technology evolution. Four high perormance DSP cores

with integrated xed- and foating-point capabilities deliver the most powerul cores or LTE PHY processing.

The rich set o hardware accelerators reduces the LTE system latency and rees up CPU resources to achieve

optimal LTE system capacity and competitive dierentiation. The TMS320TCI6618 oers the most robust

hardware platorm combined with a development ecosystem that includes ully-optimized LTE PHY library

sotware. Platorm development sotware accelerates development eorts to enable best-in-class LTE PHY

solutions to customers.

For more inormation visit www.ti.com/tci6618

To equalizerDMRSDFTIDFT

Windowing andnoise floor

removal

Pilotdemodulation

Interpolation

Received demodulation reference signal

Fig. 8 PUSCH channel estimation

Texas Instruments

Conclusion

A042210

Important Notice: The products and services of Texas Instruments Incorporated and its subsidiaries described herein are sold subject to TIs standard terms andconditions of sale. Customers are advised to obtain the most current and complete information about TI products and services before placing orders. TI assumes noliability for applications assistance, customers applications or product designs, software performance, or infringement of patents. The publication of informationregarding any other companys products or services does not constitute TIs approval, warranty or endorsement thereof.

2011 Texas Instruments Incorporated SPRY149C

The platform bar is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.


12/12

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the latest relevant information before placing orders and should verify that such information is current and complete. All products aresold subject to TIs terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TIs standardwarranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products andapplications using TI components. To minimize the risks associated with customer products and applications, customers should provideadequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Informationpublished by TI regarding third-party products or services does not constitute a license from TI to use such products or services or awarranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectualproperty of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompaniedby all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptivebusiness practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additionalrestrictions.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids allexpress and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not

responsible or liable for any such statements.TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonablybe expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governingsuch use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, andacknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their productsand any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may beprovided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products insuch safety-critical applications.

TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products arespecifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet militaryspecifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely atthe Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.

TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products aredesignated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designatedproducts in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products Applications

Audio www.ti.com/audio Communications and Telecom www.ti.com/communications

Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers

Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps

DLP Products www.dlp.com Energy and Lighting www.ti.com/energy

DSP dsp.ti.com Industrial www.ti.com/industrial

Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical

Interface interface.ti.com Security www.ti.com/security

Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense

Power Mgmt power.ti.com Transportation and www.ti.com/automotiveAutomotive

Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video

RFID www.ti-rfid.com Wireless www.ti.com/wireless-apps

RF/IF and ZigBee Solutions www.ti.com/lprf

TI E2E Community Home Page e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright 2011, Texas Instruments Incorporated
http://www.ti.com/audiohttp://www.ti.com/communicationshttp://amplifier.ti.com/http://www.ti.com/computershttp://dataconverter.ti.com/http://www.ti.com/consumer-appshttp://www.dlp.com/http://www.ti.com/energyhttp://dsp.ti.com/http://www.ti.com/industrialhttp://www.ti.com/clockshttp://www.ti.com/medicalhttp://interface.ti.com/http://www.ti.com/securityhttp://logic.ti.com/http://www.ti.com/space-avionics-defensehttp://power.ti.com/http://www.ti.com/automotivehttp://microcontroller.ti.com/http://www.ti.com/videohttp://www.ti-rfid.com/http://www.ti.com/wireless-appshttp://www.ti.com/lprfhttp://e2e.ti.com/http://e2e.ti.com/http://www.ti.com/lprfhttp://www.ti.com/wireless-appshttp://www.ti-rfid.com/http://www.ti.com/videohttp://microcontroller.ti.com/http://www.ti.com/automotivehttp://power.ti.com/http://www.ti.com/space-avionics-defensehttp://logic.ti.com/http://www.ti.com/securityhttp://interface.ti.com/http://www.ti.com/medicalhttp://www.ti.com/clockshttp://www.ti.com/industrialhttp://dsp.ti.com/http://www.ti.com/energyhttp://www.dlp.com/http://www.ti.com/consumer-appshttp://dataconverter.ti.com/http://www.ti.com/computershttp://amplifier.ti.com/http://www.ti.com/communicationshttp://www.ti.com/audio

Spry149c.lte.WhitePaper

Documents

Transcript of Spry149c.lte.WhitePaper