Spring 2010 - Solutions

7/25/2019 Spring 2010 - Solutions

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University of Waterloo

Midterm Examination Solutions

Term: Spring Year: 2010

Student Name

UW Student ID Number

Course Abbreviation and Number ECE 325

Course Title Microprocessor Systems andInterfacing for Mechatronics

Section(s) 001

Sections Combined Course(s)

Section Numbers of Combined Course(s)

Instructor(s) W. Bishop, P.Eng.

Date of Exam Monday, June 14, 2010

Time Period Start Time: 3:15 p.m.End Time: 4:15 p.m.

Duration of Exam 60 minutes

Number of Exam Pages 13(including this cover sheet)

Exam Type Closed Book

Additional Materials Allowed NO ADDITIONAL MATERIALSALLOWED

Marking Scheme (For Examiner Use Only):

Question Mark Weight Question Mark Weight

1a 4 2a 91b 4 2b 8

1c 4 2c 3

1d 4

1e 4

1f 4

Total 44

Copyright c 2010 by W. Bishop, P.Eng. and W. Loucks, P.Eng..

No unauthorized duplication permitted. 1 of 13


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ECE 325, Spring 2010 Midterm Exam Solutions

Instructions:

1. No aids are permitted. No calculators of any type are permitted.

2. Students are not permitted to wear hats of any type during the examination. Stu-dents with special needs are instructed to contact a proctor at the start of theexamination period.

3. Turn off all communication devices prior to the start of the examination and placeon your desk facing down.

4. Place all knapsacks, backpacks, and bags at the front of the examination room orbeneath your table.

5. There are 2 questions with multiple parts.

6. The exam period lasts 60 minutes and there are 44 marks. Some marks are easierto earn than others. Read the paper carefully and use your time wisely.

7. Verify that your name and student ID number is on the cover page and print yourname at the top of each page.

8. Write your answers directly on the question sheets. You may use either pen orpencil to answer questions. Answers that are too light to read or smudged will beassigned a grade of zero.

9. No questions will be answered during the examination. If you feel that a questionrequires clarification, proceed by clearly stating any reasonable assumptions nec-essary to complete the question. If your assumptions are reasonable, they will betaken into account during grading.

10. If you take the examination apart to work on the sheets separately, please call aproctor over 10 minutes prior to the end of the exam to staple the pages.

11. After reading and understanding the instructions, sign your name in the spaceprovided below.

Signature




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Question 1. Short Answer Questions [24 marks total]

Part A) Interrupt Signalling [4 marks]

Figure 1 illustrates a portion of a computer system consisting of a processor (labelledCPU) and three devices (labelled Device 1, Device 2, and Device 3). In this system, a

shared, active-low (passive pullup) interrupt signal (labelled /IRQ) is used by the devicesto communicate a request for immediate service. The/IRQsignal connects to a receiverin the CPU and to an open-collector bus driver in each device. Assume that the CPUalso connects to the three devices using a synchronous system bus (not illustrated).

/IRQ

VCC

CPUDevice 1 Device 2 Device 3

Figure 1: Computer System with a Shared Interrupt Request Signal

Complete Table 1 by indicating the state of the /IRQsignal as a digital logic value (0,1, ?, or Z) received by the processor for each of the scenarios indicated. Note that? denotes a bus conflict state and Z denotes a high impedance state.

Table 1: Interrupt Signals

Interrupt Requested /IRQ

Device 1 Device 2 Device 3 State

No No No 1

Yes No No 0

No Yes No 0

Yes No Yes 0




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Part B) Address Decoding [4 marks]

The data register of a parallel port interface has been memory mapped to memory address0x378 in a small embedded computer system.

You may safely assume the following:

The computer uses a simple synchronous bus with a read not write (R/W) signaland a clock (CLK) signal.

The address bus consists of twelve address lines (A11..A0).

The computer system does not use address aliasing.

The parallel port interface is responsible for fully decoding the address on the buswithout the help of an address decoder.

The data register is clocked on the rising edge of a signal known as REGCLK.

In the space provided below, write the most appropriate Boolean equation for REGCLK(the data registers clock signal).

REGCLK =CLKR/WA11A10A9A8A7A6A5A4A3A2A1A0




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Part C) Synchronous Bus Transfers [4 marks]

Complete Figure 2 shown below by drawing the signal waveforms for a synchronous busread of address 0x2010. Assume that the CPU is the bus master and that the device willrespond to the read request with a data value of 0x0614. Clearly label the address valueand the data value on the appropriate signals. Beside each of the signals in the boxesprovided, clearly indicate whether the signal is driven by the CPU, theDevice,Both, or

Neither.

CLOCK

ADDRESS[15..0]

R/W

DATA[15..0]

DRIVER

NEITHER

CPU

CPU

DEVICE

0x2010

0x0614

Figure 2: Synchronous Bus Read




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Part D) Hamming Coding [4 marks]

Assume that a communication channel uses Hamming Coding to provide single bit errorcorrection for a 4 bit quantity of data. Recall that when Hamming Coding is applied to4 data bits, the bit positions of the resulting code word are those indicated in Table 2shown below.

Table 2: Hamming Code Word Bit Positions

Bit Position Binary Representation Data Bits Check Bits

1 0001 C02 0010 C13 0011 D04 0100 C25 0101 D16 0110 D27 0111 D3

In the space provided below, write the Boolean equations for the three check bits ( C0,C1, and C2).

C0 =D0D1D3C1 =D0D2D3C2 =D1D2D3

If the data bits (D3D2D1D0) received are 0110 and the check bits (C2C1C0) receivedare101, has an error been detected that requires correction? Answer yes or no and brieflyexplain why.

Yes, an error has been detected that requires correction. Using the received data bits, thecheck bits are calculated to be 011. The received check bits do not match the calculatedcheck bits. The syndrome of 110indicates that an error has occured in D2.




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Part E) Serial Data Encoding [4 marks]

Complete Figure 3 shown below by drawing the signal waveforms for the sequence ofbits provided using the data encodings indicated. Assume that immediately prior to thesequence of bits, the signal value is low as illustrated.

On/Off (NRZ)

Return to Zero

Manchester

Differenal

0 1 1 0

Increasing

Time

Serial Data Value

Figure 3: Encodings of Serial Data




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Part F) Asynchronous Data Frames [4 marks]

Figure 4(a) and Figure 4(b) illustrate two possible alternatives for asynchronous dataframes. Frame Alternative 1 uses 1 start bit, no parity bit, and 1 stop bit. Framealternative 2 uses 1 start bit, 1 parity bit, and 2 stop bits.

Start

of

Frame

End

of

Frame

Start Stop0B0 B1 B2 B3 B4 B5 B6 B7

(a) Frame Alternative 1

Start

of

Frame

End

of

Frame

Start Stop0

B0

B1

B2

B3

B4

B5

B6

P Stop1

(b) Frame Alternative 2

Figure 4: Asynchronous Data Frame Alternatives

In the space provided below, briefly discuss the advantages and disadvantages of eachalternative. In your discussion, clearly indicate the overhead (expressed as a fraction oftotal frame data bits) that is associated with each alternative.

Frame Alternative 1 has the lowest overhead ( 210

). This alternative is capable of trans-mitting a full 8 bits of data. It also has the highest throughput of the two alternatives dueto its low overhead. However, this alternative is the least robust of the two alternativesand should be avoided in a noisy environment.

Frame Alternative 2 has the highest overhead ( 411

). This alternative has a parity bit thatallows single bit error detection to be performed. It also has an additional stop bit whichmay help to detect more framing errors. However, this alternative delivers the lowestthroughput of the two alternatives due to its high overhead and should be avoided ifperformance is critical.




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Question 2. Parallel Interfacing [20 marks total]

Consider the parallel interface shown in Figure 5. Table 3 describes these signals. Thetable describes the signals at a high level, in many cases you will be asked to complete thedetail as part of your answer to the questions that follow. Although the figure illustratesa system that has unidirectional data flow, your boss has required you to use an 8-bitparallel port implementing explicit bidirectional control using tri-state drivers and

persistent synchronization for this application.

The following points should be kept in mind while answering this question:

There is only 1 Data address (Data); when written the value is stored in theData register and when read the value currently on the I/O pins are read.

The device and the application and their performance characteristics arenot important to the questions posed and have not been included in thequestion.

Processor System

(All elements except

the parallel interface

and device)

Parallel

InterfaceDevice

SystemB

us

(Synchronousas

discussedin

class)

DataOut: 8 bits of data frominterface to

device

ControlOut: Contol line(s)

interface to

device

ControlIn: Control line(s)

device to

interface

Figure 5: Block Diagram for System Using a Parallel Interface

Signals in Block Diagram Comments

System Bus Uses all of the system bus signals as described inclass. The bus provides a 16 address lines, 8 datalines, one clock line and the R/W line.

DataOut 8 bits of data from the interface to the device.This data uses persistent synchronization (usingControlIn and ControlOut signals as needed).(See Part B of question).

ControlOut The control lines from the interface to the device

ControlIn The control lines from the device to the interface

Table 3: Signal Description for Parallel Interface




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Part A) Connection of the Interface to the System Bus [9 marks]

In the space provided complete the wiring of the data and data direction signals forthe interface. This part of the question does not involve the C ontrolIn or ControlOutsignals; they are considered in other parts of this question.

Specifically your answer must include the following items:

Connection of the appropriate synchronous bus signals with the Register Select unit(including arrowheads to indicate direction of signal flow),

Connection of the appropriate synchronous bus signals to permit the processor totransfer data to the data register, from the I/O pins, and to the data directionregister. Although we have provided the block for the data and DDR registers, youwill have to add the circuitry to permit theData value to be read.

The circuitry necessary for the DDR (Data Direction Register) to provide explicitbidirectional signals for the device (even though the device in this case is only usingthe signals in a unidirectional manner).

ANSWER:

Clock

R/W

/IRQ

Address15..Address0

Data7..Data0

DataDDR

Parallel Interface

(No control or status

signals illustrated or

required in this question)

Register

Select

Device (not shown)

DataOut

/WriteDDR

/WriteData

EnableData

Note: All 8-bits are connected within the

parallel interface, however we interpret

the 8 device signals as in/out

Figure 6: System Bus Connections




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Part B) Persistent Synchronization [8 marks]

In this part of the question you are to provide the circuit to implement the persistenthandshaking between the interface and the device. Note: The DataOut signals aresynchronized using persistent handshaking. You will need to first describe the signaloperation to make the transfer persistent and then provide the circuit for the interface toimplement its part of the exchange.

In the space below describe the operation of the transfer. In addition to the word de-scription of the signalling, your answer is to include both a timing diagram and a circuitdiagram each with signal names. For each of the device synchronization signals indicateif the signal is from the interface to the device ( ControlOut) or device to the interface(ControlIn).

Hint: be sure to consider how any status and control bits may fit into your answer.The status bit associated with this transfer is to be StatusBit0. Be sure to include thewiring, setting and clearing of this status bit. Also specify if you have used implicitclearing or explicit clearing of the status bit.

ANSWER:

In this case there are two signals: DataAvailableproduced by the interface as part of theControlOutbundle andDataAcceptedproduced by the device as part of the C ontrolInbundle. This version of the answer assumes that the DataAvailable signal is set bythe writing of a value into the DataOut Register (/WriteData) and is cleared by theDataAcceptedsignal. In this case there is an implicit assumption that the DataAcceptedsignal is itself cleared (reset) by the falling edge of the DataAvailable signal.

/WriteData

DataAvailable

DataAccepted

Ck

D

Reset

1

/DataOut

DataAvailable

DataAccepted

EnableStatusRegister

Bit 0 of

Data Bus(Status Register0)

to/From Device

Figure 7: Persistent Data (Out) Transfer




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Part C) Program Use of This Interface [3 marks]

Using your device interface, write the pseudo code in the space provided below to syn-chronize and transfer 1 data element (item1) to the device interface. Hint: You mayneed to refer to your synchronization circuit and bus connection circuit from theprevious parts of this question.

Include the following assumptions in your answer:

The parallel interface has just been powered-up prior to the start of your program.

A value of 1 in the least significant bit of the Data Direction Register results in theleast significant input/output line being configured as an output.

ANSWER:

// assume that the addresses: DataIn, DataOut, DataDirectionRegister

// and StatusRegister have been defined

DDR = 0xFF // most significant 4 bits are output.

While (StatusRegister&&0x1 1) ;

DataOut = item1;




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[44 marks grand total]

Copyright c 2010 by W. Bishop, P.Eng. and W. Loucks, P.Eng.. 13 of 13

Spring 2010 - Solutions

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