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SPP FIELDS DFB Quarterly June 2014 Solar Probe Plus FIELDS Instrument Quarterly Digital Fields Board...
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Transcript of SPP FIELDS DFB Quarterly June 2014 Solar Probe Plus FIELDS Instrument Quarterly Digital Fields Board...
1SPP FIELDS DFB Quarterly June 2014
Solar Probe Plus FIELDSInstrument Quarterly
Digital Fields Board
SPP FIELDS DFB Quarterly June 2014
DFB Development Status
• DFB work proceeding well• EM1 tested and characterization in-process• Xilinx FPGA Daughter Board complete and integrated with EM1• EM2 development moving into layout, schematic review held last Friday,
6/13• SIDECAR ASIC screening complete on FM parts, in-process on remaining
EM part• FPGA development continues on remaining modules: Triggers, Burst
Memory, and Spectra/Cross-Spectra EEE Parts approved by PCB, and procurements nearing completion
– All known orders for EM2 and FM complete, with most parts are in house • ASIC CGA attachment PO placed with BAE Systems
– 1st article inspection ~ 5 weeks, Eng & QA on-site inspection – Three mechanical parts for vibe and ‘practice’ for board assembly; and one
part for EM2– After EM2 board assembly and testing, will turn-on attachment of two FM parts
• Closed 7 of 8 Peer Review actions items, – 8th response in review by SPF team; no I-PDR or M-PDR action items assigned
to DFB• Risk mitigation plans are proceeding and trending downward
– ASIC screening confirms parts are viable flight candidates– Board deflection analysis indicates positive margin, vibration testing to
confirm2
SPP FIELDS DFB Quarterly June 2014
DFB Development Road Map
3
Prototype DFB
Xilinx FPGA DB
SIDECAR Evaluation Board
Flight DFB
• EMs and FM DFBs can accommodate all variations of FPGA DB: Xilinx, ProASIC, ProtoRTAX, FM RTAX
FPGA
DB
EM1
EM2-Flatsat
EM2 Schematic Review complete 6/13Notional Layout Shown
SPP FIELDS DFB Quarterly June 2014
DFB EM1
4
• EM1 bench testing complete• FPGA testing and
characterization of DFB (including ASIC) starting
FPGA D
BASIC
• FPGA DB with programmable Xilinx, upward compatible code with ProASIC/RTAX FPGAs
• SIDECAR ASIC in a socket with PCB structural enhancement cap
SPP FIELDS DFB Quarterly June 2014
DFB Test Lab Configurations
6
DFB bench-level testing and characterization set-up• FPGA loads and science
analysis continue for next couple months
• ASIC characterization included
• Thermal testing while EM2 is in layout/fab/assembly
SIDECAR ASIC screening• Both FM and spare selected• Remaining EM part screening
in-process
SIDECAR ASIC Thermal ScreeningEM1 Testing Configuration
7SPP FIELDS DFB Quarterly June 2014
DFB Schedule
• Critical path is thru EMs• Reserve held @
1mnth/year • Schedule threat is CGA
attachment and EM2 assembly
• Work-around is use of EM1 until EM2 is ready
EM1
EM2
SPP FIELDS DFB Quarterly June 2014
Digital Fields BoardBlock Diagram
Generates time domain and spectral domaindata products (DC – 75kHz)
Implementation includes:- Programmable gain states- Burst memory- Flexible configurations- Search coil cal. signal- Low mass, low power ADC
9 inputs:5 E-field antennas4 search coil channels
26 signals digitized @ 150 kS/s
Analog Filters / Gain stages
FPGA processing
SPP FIELDS DFB Quarterly June 2014
ID TITLE P I Crit Impact Trend Retire At
SPF-DFB01 SIDECAR workmanship 2 3
LPM Post PDR characterization testing - Screening complete
SPF-DFB02 PWB Structural Deflection 2 3
LPMSC Post PDR vibration testing, Q3-2014
If the SIDECAR experiences latent failure and/or has reliability issues, then the lack of a complete EIDP and respective workmanship could hinder the debug/troubleshooting, and have the potential to degrade performance and warrant possible redesign which could increase needed mass and power. Risk mitigation plan is to perform characterization and environmental testing on the SIDECARs. These parts have prior electrical burn-in testing hence characterization and environmental tests will demonstrate good rigor to retire the risk. Risk rating: Probability 2, Impact 3; not likely to occur based on successful burn-in testing completed by GSFC/Teledyne; consequences slightly higher based on possibility of reverting to backup plan of discrete ADCs. Proposed/heritage ADCs are not as rad-tolerant, require more board space (mass increases), more power, and/or could drive science return. Newer, more viable, ADCs identified but require radiation testing.
DFB Risk Mitigation Proceeding
If the DFB PWBA experiences too high of structural deflection, then the assembled components may experience package stresses, with respective workmanship and/or reliability issues. The primary concern is the SIDECAR CGAs. This potential could warrant possible redesign of the PWB layout, structural stiffness design, or reduction in DFB capability due to replacing the SIDECAR/other components to stay within mass and power constraints. Analysis and part modeling in process now. Risk mitigation plan is to perform vibration testing to SPF-MEP vibration levels on an EM PWB with representative components and mass models. Analysis and modeling, along with vibration testing, must prove the PWBA design and demonstrate good rigor to retire the riskRisk rating: Probability 2, Impact 3; not likely to occur based on analysis and modeling and good design practices of the PWBA. Consequences now lowered with addition of ASIC Al cap which lowers structural deflection in areas of concern. Analysis complete, vibe test pre-CDR, cap in place on EM1.
11SPP FIELDS DFB Quarterly June 2014
DFB Related Action Items
No Title Detail Status
SCM-15 Calibration Frequencies Cal freq plan agreed to by Fields team Closed
SCM-17 Calibration Signal Cleanliness
Signal range requirements needed to be worked w/I Fields team
SCM team evaluating
DFB-01 Analog Amplitude Near Rails
Consider an indicator flag on SIDECAR if input is near a rail
Closed
DFB-02 System Clk termination Add pull-down resistor on 19.2MHz – in ICD
Closed
DFB-03 Filtering on LF Channels
Consider changing to 2-pole filters on LF channels
Closed
DFB-04 Periodically re-sync SIDECAR
Consider Re-syncing SIDECAR ADC sampling to FPGA
Closed
DFB-05 CCSDS Packet Checksum
Reconsider using checksums on CCSDS packets
Closed
DFB-06 Signal Integrity on FPGA DB
Consider adding more grounding on FPGA DB
Closed
DFB Peer Review held Nov 4-5th, materials available on SPF siteAction Items from this and other Peer reviews included here (SCM Peer Review Sept 4-5, 2013)No DFB actions assigned at I-PDR or M-PDR