Special Issue: Extended Papers Selected from EUROSOI-ULIS 2016

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SOLID-STATEELECTRONICS

An International Journal

Volume 128, February 2017 ISSN 0038-1101

EDITORS:

E. Calleja

Madrid

S. CristoloveanuGrenoble, France

Y. Kuk

Seoul, South Korea

A. Zaslavsky

Providence, RI

Special Issue:Extended papers selected from

EUROSOI-ULIS 2016

Guest Editors

Viktor SverdlovSiegfried Selberherr

ISSN 0038-1101ISSN 0038-1101

Printed in the Netherlands

SPECIAL ISSUE: EXTENDED PAPERS SELECTED FROM EUROSOI-ULIS 2016

Guest Editors

Viktor Sverdlov and Siegfried Selberherr

V. SVERDLOVVERDLOV and S. SELBERHERRELBERHERR: Special Issue of Solid-State Electronics, dedicated to EUROSOI-ULIS2016 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

J. M. C. STORKTORK IEEE Fellow and G. P. HOSEYOSEY: SOI technology for power management in automotive andindustrial applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

B. MOHAMADOHAMAD, C. LEROUXEROUX, D. RIDEAUIDEAU, M. HAONDAOND, G. REIMBOLDEIMBOLD and G. GHIBAUDOHIBAUDO: Reliable gatestack and substrate parameter extraction based on C-V measurements for 14 nm node FDSOI technology 10

M. A. ELMESSARYLMESSARY, D. NAGYAGY, M. ALDEGUNDELDEGUNDE, N. SEOANEEOANE, G. INDALECIONDALECIO, J. LINDBERGINDBERG,

W. DETTMERETTMER, D. PERICERIC, A. J. GARCIA-LOUREIROARCIA-LOUREIRO and K. KALNAALNA: Scaling/LER study of Si GAAnanowire FET using 3D finite element Monte Carlo simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

N. SANOANO: Variability and self-average of impurity-limited resistance in quasi-one dimensional nanowires. . 25

T. A. KARATSORIARATSORI, C. G. THEODOROUHEODOROU, S. HAENDLERAENDLER, C. A. DIMITRIADISIMITRIADIS and G. GHIBAUDOHIBAUDO: Draincurrent local variability from linear to saturation region in 28 nm bulk NMOSFETs . . . . . . . . . . . . . . . . 31

S. STRANGIOTRANGIO, P. PALESTRIALESTRI, M. LANUZZAANUZZA, D. ESSENISSENI, F. CRUPIRUPI and L. SELMIELMI: Benchmarks of a III-VTFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmeticcircuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

P. G. D. AGOPIANGOPIAN, J. A. MARTINOARTINO, A. VANDOORENANDOOREN, R. ROOYACKERSOOYACKERS, E. SIMOENIMOEN, A. THEANHEAN andC. CLAEYSLAEYS: Study of line-TFET analog performance comparing with other TFET and MOSFETarchitectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

C. MEDINA-EDINA-BAILONAILON, C. SAMPEDROAMPEDRO, F. GAMIZAMIZ, A. GODOYODOY and L. DONETTIONETTI: Confinement orientationeffects in S/D tunneling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

[continued on inside back cover

SOLID-STATE ELECTRONICS

Volume 128, February 2017

CONTENTS

Abstracted / Indexed in: Res. Alert, Cam. Sci. Abstr., Chem. Abstr. Serv., Curr. Cont./Phys. chem. & Earth Sci., Curr Cont./Eng. Tech. & Appl. Sci., Curr. Tech. Indx, Eng. Indx, INSPEC Data.,

PASCAL-CNRS Data., Curr. Cont. Sci. Indx, Curr. Cont. SCISEARCH Data., SSSA/CISA/ECA/ISMEC, Mater. Sci. Cit. Indx, Appl. Sci. & Tech. Indx, Wilson Appl. Sci. & Tech. Abstr. Also covered in

the abstract and citation database Scopus�. Full text available on ScienceDirect�.

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CYAN MAGENTA YELLOW BLACK

Amsterdam • Boston • London • New York • Oxford • Paris • Philadelphia • San Diego • St. Louis

Solid-State ElectronicsAn International Journal

Volume 128 (2017)

Founding Editor

W. CRAWFORD DUNLAP

Editors

E. CALLEJA

Madrid

S. CRISTOLOVEANU

Grenoble, France

Y. KUK

Seoul, South Korea

A. ZASLAVSKY

Providence, RI

Amsterdam • Boston • London • New York • Oxford • Paris • Philadelphia • San Diego • St. Louis

Special Issue:

Extended papers selected from EUROSOI-ULIS 2016

Guest EditorsViktor Sverdlov

Siegfried Selberherr

EDITORIAL ADVISORY BOARD

P. AVOURISVOURIS, Yorktown Heights, NY, USAG. BACCARANIACCARANI, Bologna, ItalyL. COLOMBOOLOMBO, Dallas, TX, USAJ. G. FOSSUMOSSUM, Gainesville, FL, USAG. GHIBAUDOHIBAUDO, Grenoble, FranceG. GILDENBLATILDENBLAT, Tempe, AZ, USAS. HALLALL, Liverpool, UKT. HASHIZUMEASHIZUME, Saitama, JapanS. HWANGWANG, Yongin-si, Gyeonggi-do, South KoreaC. JAGADISHAGADISH, Canberra, ACT, AustraliaK. KAKUSHIMAAKUSHIMA, Midori-ku, Yokohama, Japan

S. KELLERELLER, Santa Barbara, CA, USAJ.-HH. LEEEE, Gwanag-Gu, Seoul, South KoreaC. MCCANDREWNDREW, Tempe, AZ, USAC. MCCCONVILLEONVILLE, Coventry, UKS. RINGELINGEL, Columbus, OH, USAJ. SCHMITZCHMITZ, Enschede, NetherlandsA. SEABAUGHEABAUGH, Notre Dame, IN, USAM. S. SHURHUR, Troy, NY, USAA. WAAGAAG, Braunschweig, Germany


FOUNDING EDITOR

DRR W. CRAWFORDRAWFORD DUNLAPUNLAP

EDITORS

E. CALLEJAALLEJA

Dept. of Electronic Engineering (ISOM), ETSI Telecommunication,Universidad Politecnica de Madrid (UPM), 28040 Madrid, Spain

S. CRISTOLOVEANURISTOLOVEANU

Grenoble INP, Ref: LPCS-SSE, 46 av. Felix Viallet,F-38031 Grenoble Cedex 1, France

Y. KUKUK

Dept. of Physics & Astronomy, Seoul National University (SNU),Gwanack-ku Silim-dong, Seoul, South Korea

A. ZASLAVSKYASLAVSKY

Solid State Electronics, Brown University Engineering, 182 Hope Street,Providence, RI 02912, USA

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Volume 128 February 2017

CONTENTS—continued from outside back cover]

C. SCHULTE-CHULTE-BRAUCKSRAUCKS, S. GLASSLASS, E. HOFMANNOFMANN, D. STANGETANGE, N. vONON DENDEN DRIESCHRIESCH, J. M. HARTMANNARTMANN,Z. IKONICKONIC, Q. T. ZHAOHAO, D. BUCAUCA and S. MANTLANTL: Process modules for GeSn nanoelectronics with highSn-contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

B. C. PAZAZ, M. CASSEASSE, S. BARRAUDARRAUD, G. REIMBOLDEIMBOLD, M. VINETINET, O. FAYNOTAYNOT and M. A. PAVANELLOAVANELLO: Studyof silicon n- and p-FET SOI nanowires concerning analog performance down to 100 K. . . . . . . . . . . . . . 60

A. S. N. PEREIRAEREIRA, G. DEDE STREELTREEL, N. PLANESLANES, M. HAONDAOND, R. GIACOMINIIACOMINI, D. FLANDRELANDRE and

V. KILCHYTSKAILCHYTSKA: An in-depth analysis of temperature effect on DIBL in UTBB FD SOI MOSFETs basedon experimental data, numerical simulations and analytical models . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

R. BERTHELONERTHELON, F. ANDRIEUNDRIEU, S. ORTOLLANDRTOLLAND, R. NICOLASICOLAS, T. POIROUXOIROUX, E. BAYLACAYLAC, D. DUTARTREUTARTRE,

E. JOSSEOSSE, A. CLAVERIELAVERIE and M. HAONDAOND: Characterization and modelling of layout effects in SiGe channelpMOSFETs from 14 nm UTBB FDSOI technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

H. J. PARKARK, L. PIRROIRRO, L. CZORNOMAZZORNOMAZ, I. IONICAONICA, M. BAWEDINAWEDIN, V. DJARAJARA, V. DESHPANDEESHPANDE and

S. CRISTOLOVEANURISTOLOVEANU: Back-gated InGaAs-on-insulator lateral N+NN+ MOSFET: Fabrication and typicalconduction mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

V. DESHPANDEESHPANDE, V. DJARAJARA, E. O’’CONNORONNOR, P. HASHEMIASHEMI, K. BALAKRISHNANALAKRISHNAN, D. CAIMIAIMI, M. SOUSAOUSA,

L. CZORNOMAZZORNOMAZ and J. FOMPEYRINEOMPEYRINE: DC and RF characterization of InGaAs replacement metal gate(RMG) nFETs on SiGe-OI FinFETs fabricated by 3D monolithic integration. . . . . . . . . . . . . . . . . . . . . 87

D. TOMASZEWSKIOMASZEWSKI, G. GŁUSZKOUSZKO, L. ŁUKASIAKUKASIAK, K. KUCHARSKIUCHARSKI and J. MALESINSKAALESINSKA: Elimination of thechannel current effect on the characterization of MOSFET threshold voltage using junction capacitancemeasurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

D. BOUDIEROUDIER, B. CRETURETU, E. SIMOENIMOEN, R. CARINARIN, A. VELOSOELOSO, N. COLLAERTOLLAERT and A. THEANHEAN: Lowfrequency noise assessment in n- and p-channel sub-10 nm triple-gate FinFETs: Part I: Theory andmethodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

D. BOUDIEROUDIER, B. CRETURETU, E. SIMOENIMOEN, R. CARINARIN, A. VELOSOELOSO, N. COLLAERTOLLAERT and A. THEANHEAN: Lowfrequency noise assessment in n- and p-channel sub-10 nm triple-gate FinFETs: Part II: Measurements andresults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

C. MARQUEZARQUEZ, N. RODRIGUEZODRIGUEZ, F. GAMIZAMIZ and A. OHATAHATA: Systematic method for electrical characterizationof random telegraph noise in MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

B. KAZEMIAZEMI ESFEHSFEH, S. MAKOVEJEVAKOVEJEV, D. BASSOASSO, E. DESBONNETSESBONNETS, V. KILCHYTSKAILCHYTSKA, D. FLANDRELANDRE and

J.-P. RASKINASKIN: RF SOI CMOS technology on 1st and 2nd generation trap-rich high resistivity SOI wafers . 121

C. JUNGEMANNUNGEMANN, T. LINNINN, K. BITTNERITTNER and H.-G. BRACHTENDORFRACHTENDORF: Numerical investigation of plasmaeffects in silicon MOSFETs for THz-wave detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

V. SIMONKAIMONKA, G. NAWRATILAWRATIL, A. HOSSINGEROSSINGER, J. WEINBUBEINBUB and S. SELBERHERRELBERHERR: Anisotropic interpolationmethod of silicon carbide oxidation growth rates for three-dimensional simulation. . . . . . . . . . . . . . . . . . 135

P. MANSTETTENANSTETTEN, L. FILIPOVICILIPOVIC, A. HOSSINGEROSSINGER, J. WEINBUBEINBUB and S. SELBERHERRELBERHERR: Framework to modelneutral particle flux in convex high aspect ratio structures using one-dimensional radiosity . . . . . . . . . . . . 141

T. BALDAUFALDAUF, A. HEINZIGEINZIG, J. TROMMERROMMER, T. MIKOLAJICKIKOLAJICK and W. M. WEBEREBER: Tuning the tunnelingprobability by mechanical stress in Schottky barrier based reconfigurable nanowire transistors . . . . . . . . . 148

[continued on last page

Solid-State Electronics 128 (2017) 1–2

Contents lists available at ScienceDirect

Solid-State Electronics

journal homepage: www.elsevier .com/locate /sse

Editorial

Special Issue of Solid-State Electronics, dedicated to EUROSOI-ULIS 2016

http://dx.doi.org/10.1016/j.sse.2016.10.0150038-1101/� 2016 Elsevier Ltd. All rights reserved.

The current special issue of Solid-State Electronics includes 29extended papers presented at the 2016 Second Joint InternationalEUROSOI Workshop and International Conference on UltimateIntegration on Silicon (EUROSOI-ULIS 2016) held in Wien, Austria,on January 25–27, 2016. The papers entering to the special issuehave been selected by the EUROSOI-ULIS 2016 Technical ProgramCommittee based on the excellence of abstracts submitted and pre-sentations delivered at the conference. In order to comply with thehigh standards of Solid-State Electronics the manuscripts wentthrough the standard reviewing procedure.

The papers cover the vast variety of topics including fabrication,characterization and modeling of the cutting-edge fully depletedSOI, FinFET and nanowire-based devices, tunnel FETs, and novelemerging devices for memory and logic applications.

The invited paper by H. Stork and G. Hossey from ON Semicon-ductor introduces an exciting field of commercial SOI technologyand provides an extensive review of its use for power managementin automotive and industrial applications.

The problem of an accurate extraction of the effective oxidethickness and the work function in extremely scaled 14 nm fullydepleted SOI devices is addressed in the paper by B. Mohamadet al.

Simulation study of silicon ultra-scaled gate all around nano-wire FETs including the line-edge roughness by 3D Finite ElementMonte Carlo Simulations is performed by M. Elmessary et al.

Another aspect of variability due to electron scattering on ran-domly positioned impurities and the problem of self-averaging ofimpurity-limited resistance in quasi-one dimensional nanowiresis addressed in the paper by N. Sano.

Drain current variability in 28 nm n-MOSFETs in both linear andsaturation regimes is studied in details by T. Karatsori et al.

Continuing the line of extremely scaled devices, the computa-tional benchmarking of III–V semiconductors tunnel FETs againstthe 10 nm CMOS FinFET technology is performed by S. Strangioet al. at an example of basic arithmetic circuits.

An extensive comparison of the analog performance of fabri-cated line tunnel FETs with respect to other tunnel FET- and MOS-FET-based architectures is reported in the paper by P. Agopian et al.

Confinement orientation effects on source to drain tunnelingare addressed by C. Medina-Bailon et al.

Process modules for GeSn nanoelectronics with high Sn-concen-tration reported by C. Schulte-Braucks et al. provide a base for fur-ther optimization of GeSn FETs and novel tunnel FET devices.

An experimental evaluation of the analog performance of n- andp-type SOI nanowire FETs in a broad temperature range from roomtemperature down to 100 K is performed by B. Paz et al.

The influence of temperature on drain-induced barrier loweringin ultra-thin box and body fully depleted SOI MOSFETs is analyzedby A. Pereira et al. based on extensive experimental data, numeri-cal simulations, and analytical modeling.

Continuing the line of exploiting materials with improvedtransport characteristics for the next generation transistors, theinfluence of layout effects including mechanical stress in 14 nmUTBB FDSOI SiGe channel p-MOSFETs is investigated and charac-terized both experimentally and by modeling in the paper by R.Berthelon et al.

Fabrication process and conduction mechanisms in back-gatedInGaAs-on-insulator lateral N+NN+ junctionless MOSFETs arereported by H.J. Park et al.

DC and first RF characterization of InGaAs replacement metalgate n-FETs on SiGe-on-insulator FinFETs fabricated by 3D mono-lithic integration is presented by V. Deshpande et al.

A new MOSFET threshold voltage characterization method sug-gested by D. Tomaszewski et al. allows elimination of the channelcurrent effects by using junction capacitance measurements.

D. Boudier et al. describe how low frequency noise measure-ments can provide an essential information on the quality of thegate oxide and the silicon film of tri-gate SOI FinFETs and thuscan be used as a non-destructive characterization tool at sub-10 nm technology nodes.

A systematic method for electrical characterization of randomtelegraph noise in MOSFETs is presented by C. Marquez et al. aim-ing to facilitate massive on-wafer characterization of noise MOS-FET characteristics.

In the work by B. Kazemi Esfeh et al. it is shown that a trap-richlayer in trap-rich high resistivity SOI wafers with thinner BOX doesnot alter RF characteristics of the MOSFET transistors while itallows for improved thermal properties thus making the technol-ogy viable for SoC applications.

The paper by C. Jungemann et al. continues along the line of fre-quency-dependent phenomena in MOSFETs and provides an effi-cient numerical simulation tool capturing plasma oscillationeffects in silicon MOSFETs used for THz detection.

Efficient approaches for accurate high-performance TCAD simu-lations are reported by the CDL Laboratory for high-performanceTCAD at TU Wien: V. Simonka et al. describe the anisotropic inter-polation method of SiC oxidation growth rates for three-dimen-sional simulation, while P. Manstetten et al. present acomputationally efficient framework to evaluate the neutral fluxin high aspect ratio structures during three-dimensional plasmaetching simulations.

http://crossmark.crossref.org/dialog/?doi=10.1016/j.sse.2016.10.015&domain=pdf

http://dx.doi.org/10.1016/j.sse.2016.10.015


http://www.sciencedirect.com/science/journal/00381101

http://www.elsevier.com/locate/sse

2 Editorial / Solid-State Electronics 128 (2017) 1–2

T. Baldauf et al. address by simulations the effect of mechanicalstress on tunneling and the transfer characteristics in two indepen-dently gated Schottky junctions of Schottky barrier-based reconfig-urable nanowire transistors.

Continuing the reconfigurable FETs topic, C. Navarro et al. high-light the main advantages, limitations, and ways to improve theperformance by employing TCAD for careful optimization andbenchmarking reconfigurable field effect transistors.

Concerning new applications and devices employing advancedFD-SOI technology, a novel scalable three-dimensional single-pho-ton avalanche diode pixel with high fill factor is proposed andextensively studied by simulations in the work of M. Vignetti et al.

A novel electrostatic discharge protection based on reconfig-urable ultra-thin film gated diode merged NMOS is proposed andfabricated with 28 nm UTBB FD-SOI high-k metal gate technologyin the work by S. Athanasiou et al.

Another new sharp-switching band-modulation back-gateddevice fabricated in advanced FD-SOI technology is presented byH. El Dirani et al.

Finally, recent developments in promising devices and conceptsbeyond SOI MOSFETs for future non-volatile memory and logicapplications are given in the paper by A. Grossi et al., where elec-trical characterization and modeling of one-transistor/one-resistorresistive random access memory arrays with amorphous and poly-crystalline HfO2 as an active medium is presented.

A substantial reduction of the switching current in spin-transfertorque due to inverse magnetostriction induced switching barrier

lowering is predicted by Y. Takamura et al. A magnetic randomaccess memory cell based on the magnetic tunnel junction sur-rounded by a piezoelectric gate operates at low voltages, whichpromises a large reduction of the write energy without degradationof the thermal stability.

We would like to express our gratitude and thank all theauthors for accepting the invitation and preparing the excellentquality manuscripts within a tight time frame. We would also liketo acknowledge all the reviewers for their time spent to providehighly professional comments to the authors, which indisputablyhelped boosting the overall paper quality to meet the highest pub-lication standards adopted by Solid-State Electronics. Our specialthank is dedicated to the Solid-State Electronics Editor Sorin Cris-toloveanu for his constant encouragements, support, and help.

Guest EditorViktor Sverdlov

Guest EditorSiegfried Selberherr

Institute for Microelectronics, TU Wien, Vienna, AustriaE-mail addresses: [email protected] (V. Sverdlov),

[email protected] (S. Selberher

Available online 18 October 2016

mailto:[email protected]






SOI technology for power management in automotive and industrialapplications


⇑ Corresponding author.E-mail address: [email protected] (G.P. Hosey).

Johannes M.C. Stork IEEE Fellow, George P. Hosey ⇑ON Semiconductor, Phoenix, AZ, USA

a r t i c l e i n f o

Article history:Available online 15 October 2016

The review of this paper was arranged byViktor Sverdlov

Keywords:Semiconductor on InsulatorSOIPower managementAutomotive electronicsIndustrial electronics

a b s t r a c t

Semiconductor on Insulator (SOI) technology offers an assortment of opportunities for chip manufactur-ers in the Power Management market. Recent advances in the automotive and industrial markets, alongwith emerging features, the increasing use of sensors, and the ever-expanding ‘‘Internet of Things” (IoT)are providing for continued growth in these markets while also driving more complex solutions. Thepotential benefits of SOI include the ability to place both high-voltage and low-voltage devices on a singlechip, saving space and cost, simplifying designs and models, and improving performance, thereby cuttingdevelopment costs and improving time to market. SOI also offers novel new approaches to long-standingtechnologies.

� 2016 Elsevier Ltd. All rights reserved.

1. Introduction

Today’s modern cars contain an enormous amount of electricalwiring and electronic circuits used for a variety of applications, andthe trend is for even greater integration and complexity. Likewise,the industrial segment continues to grow and expand with the‘‘Internet of Things”. With each new advance and each new oppor-tunity come new challenges. In power management, these chal-lenges include the ability to fabricate high-voltage powerelectronics and the low-voltage MOS dev ices required to controlthem without the additional space and cost of multi-chip and co-packaged solutions. Semiconductor-on-Insulator technology offersthe advantage of integrating both high-voltage devices and low-voltage circuitry on the same chip [1]. The monolithic integrationof vertical power devices together with control circuits increasesthe functionality and minimizes the size of the chips [2]. SOI alsooffers improved performance as a result of lower parasitic leakageand capacitance, leading to improved model accuracy and fewerdevelopment iterations, resulting in reduced development costsand quicker time to market, as well as improved reliability. In addi-tion, SOI provides new ways to improve older technologies andopens paths to novel process integrations.

2. Automotive and industrial applications

The automotive segment has enjoyed one of the fastest growthrates of any large segment in the worldwide chip market, averag-ing 8% annual growth between 2002 and 2012. The average auto-mobile currently has around $350 in semiconductor content witheven higher dollar content found in hybrid and luxury vehicles[3]. The vast majority of this content is in microcontroller units,analog, and power. (Fig. 1 shows a breakdown of the semiconduc-tor content in various automobile families by family and by semi-conductor type.)

Key trends in automotive semiconductors include:

� Fuel Economy & Emissions Reduction� Active Safety & Autonomous Driving (autonomous cruise con-trol, collision warning/avoidance)

� Vehicle Electrification (Hybrids, plug-ins, electric cars)� Connectivity (Bluetooth, in-car WiFi)� Light Emitting Diode (LED) Lighting

ON Semiconductor offers a vast array of solutions in these areas,including

� Power Management, Igniters, Application-Specific IntegratedCircuits (ASICs), Application-Specific Standard Products (ASSPs)

� Image Sensors, Communications, Sensor Interface







Fig. 1. Automobile semiconductor content [3].

Fig. 2. Size comparison of a bulk NLDMOS device inserted into an SOI shell to the same device once fully optimized for an SOI platform.

Fig. 3. Area savings for optimized NLDMOS and PLDMOS devices in SOI platformscompared to bulk platforms, by device size (current capability).

4 J.M.C. Stork, G.P. Hosey / Solid-State Electronics 128 (2017) 3–9

� Insulated Gate Bipolar Transistors (IGBTs), High Efficiency FETs,Power Integrated Modules (PIMs), Gate Drivers, IntelligentPower Modules (IPMs)

� Wireless Charging Circuits, In-Vehicle Networking� LED Drivers, Motor Control, MOSFETs� Smart Passive Sensors, Protection

The industrial segment also offers incredible growth opportuni-ties in the coming years courtesy of trends in

� The ‘‘Internet of Things” – Home security, smart homes, smartoffice buildings, building security and surveillance

� High-efficiency power supplies and motors� The seemingly ubiquitous sensors we encounter every day.

for which ON offers solutions that include

� Power modules (IPMs, PIMs)� Smart Passive Sensors, Image sensors, ISPs, DSPs� Wired/wireless communications, motor drivers, and LED drivers� As well as a host of comprehensive power managementsolutions.

3. Automotive BCD process integration

Bipolar-CMOS-DMOS (BCD) is a key technology in power inte-grated circuits, and thus, has become a key technology in automo-tive power applications. The marriage of BCD with SOI wafertechnology allows the same chip to carry both low-voltage controlcircuitry and high-voltage DMOS power devices. Devices with rat-ings exceeding 35 V are common in 12 V automotive systems,while 120 V rated devices are seen in the emerging 42 V batterysystems as designers and manufacturers look for robust ‘‘load

dump” capability. Even higher voltages, 500 V or more, arerequired for some applications, such as ignition IGBTs [1]. As auto-motive manufacturers continue to seek the simplest, lowest-costsolutions, SOI technologies, with the ability to house control anddriver circuits in a single chip will become more and more a tech-nology of choice.

SOI offers additional benefits as well. Wafer costs for SOI sub-strates are considerably higher than those for traditional bulk sili-con wafers, however, when the layout and integration are fully-optimized, SOI offers chip size (silicon area) savings, as shown inFig. 2, and mask count savings as well.

As shown in Fig. 3, effective savings of 10–30%, depending onthe SOI wafer fabrication techniques employed, are achieved whenSOI-based processing is used in place of HV-bulk-Si technology.

Fig. 4. Parasitic junctions in a typical bulk DMOS device.

Fig. 5. (a and b) Parasitic junctions in a typical SOI DMOS device and cross-section.

J.M.C. Stork, G.P. Hosey / Solid-State Electronics 128 (2017) 3–9 5


SOI technology also brings improved IC performance throughreductions in parasitic leakage currents and parasitic capacitances.Every set of PNP or NPN junctions creates a parasitic transistorwith some inherent gain and an associated, resulting, leakage cur-rent. Typical parasitics for a bulk device are shown in Fig. 4.

The same is, of course, also true for devices in SOI technologyplatforms, however, the sheer number of such parasitic junctionsis greatly reduced by the SOI integration. Fig. 5 shows the parasiticjunctions for the same device when fabricated in an SOI platform.

It is also worth noting that, for each of these parasitic junctions,not only is a parasitic transistor created, but a parasitic junctioncapacitance as well.

While any one of these parasitic junctions might not greatlyimpact device or circuit performance, taken together, they cangreatly affect the results, so the more parasitic junctions are pre-sent, the greater the risk.

Parasitics lead to greater model complexity as modeling teamswork to identify and characterize each and every parasitic path.With this increased complexity comes greater inherent inaccuracyof the models. Inaccuracies in the models, in turn, result in addi-

Fig. 6. Temperature rise and decay in SOI and bulk-Si LDMOS transistors followingan application of 90 W/mm2, 1 ms power pulse [5].

0

50

100

150

200

250

300

Tem

p

Time (s)

Temp Response by BOX

Fig. 7. Modeling results for temperature response o

tional design/development cycles which prolong development,increase development costs, and delay release to market.

Conversely, SOI technology offers simpler, more accurate mod-els, leading to fewer design cycles, shorter development times,reduced development cost, and quicker time to market (andprofitability).

SOI is not, of course, without its integration challenges as well.One of the primary challenges in using SOI is the accumulation anddissipation of heat within the chip and especially the powerdevices. As semiconductor devices shrink, heat dissipationbecomes ever more challenging. While the task is already difficultin bulk silicon devices, it takes on even greater difficulty in asilicon-on-insulator (SOI) device. In bulk silicon, the heat can travelthrough the silicon to the package lead frame. In SOI devices, how-ever, the buried oxide and oxide trenches surrounding the deviceact as heat insulation, trapping the generated heat within the SOItub. The thermal resistance of SOI devices has been seen to be asmuch as an order of magnitude higher than that for bulk silicondevices [4].

Fig. 6 shows a comparison of SOI vs bulk silicon temperatureresponse. It is seen that there is a significant difference in self-heating between SOI and bulk silicon, and that this difference isgreatest for short power transients because the initial temperaturerise in the SOI devices is more rapid than that for the bulk devices[5].

Fig. 7 shows a modeled temperature response for BOX thick-nesses ranging from 0.5 lm top 1.5 lm. As would be expected,the self-heating for the devices increases with the thickness ofthe BOX layer as the thicker BOX increases the thermal resistanceof the device.

4. Motor control using IGBT’s

SOI technology offers tremendous opportunities for device per-formance in Insulated Gate Bipolar Transistors (IGBTs) as well.

IGBTs have enjoyed popularity for automotive ignition applica-tions because they combine the fast-switching capability of a MOS-FET with the low conductions losses (high efficiency) of a bipolarjunction transistor (BJT).

0

50

100

150

200

250

300

350

Curr

ent (

mA)

Thickness

BOX 0.5

BOX 1

BOX 1.5

Current

f SOI object with various BOX thicknesses [6].

Fig. 8. The IGBT triangle.

Fig. 9. Switching loss/conduction loss trade-off.

Fig. 10. Cross-section of N-channel trench IGBT with drift region labeled.


Until recently, automotive systems other than the ignition mod-ule had no need for the high voltage performance of IGBTs, but newdevelopments in both conventional and hybrid autos are changingthat. High-Intensity Discharge (HID) headlamps and super-accurate direct fuel-injection systems have become common in

today’s cars and commercial vehicles, such as buses and trucks.Their associated electrical drives and controls operate at voltagesabove 100 V. In addition, hybrid/electric vehicles (HEVs), whichrequire efficient power control at voltages close to 1000 V, willdrive demands for new types of automotive IGBTs [7].

IGBT design and performance are a study in trade-offs. Fig. 8shows what is called the ‘‘IGBT Triangle”. The points of the triangleare the three key aspects of IGBT performance – Switching Losses(efficiency), Conduction Loss (Vce), and Ruggedness (energyabsorption ability as displayed in short circuit and UIS testing).

Efforts to improve one aspect of performance (one point of thetriangle) diminish one or both of the other aspects. Fig. 9 illustratesan example of such a trade-off. As shown, increasing the dopantconcentration results in reduced conduction loss, but it alsoincreases switching loss. Conversely, decreasing the dopant con-centration improves switching loss while bringing about anunwanted increase in Vce.

Decreasing the thickness of the ‘‘drift” region, however, offersthe opportunity to reduce both the switching loss and conductanceloss. The drift region (visible in Fig. 10) is an epitaxy layer throughwhich minority carriers must travel when the device is in opera-tion. The drift region is typically quite thick and very lightly-doped relative to other regions of the device, so it is not surprisingthat this region of silicon contributes significantly to the ‘‘on” resis-tance of the device, and thus the conduction loss (also known asVceon using the bipolar nomenclature, or Vdson using the MOSnomenclature).

Process options for fabricating these thinner drift regionsinclude the use of glass carrier wafers and the use of SOI siliconcarrier wafers. The silicon wafer carrier method is illustrated inFig. 11.

While both the glass carrier method and the SOI wafer carriermethod will work to achieve the desired thinning of the driftregion, the glass carrier process encounters two serious challenges

� The glue attaching the glass carrier to the silicon limits thebackside processing temperature to less than 300 �C.

� The glass and the silicon have different thermal expansion coef-ficients, resulting in wafer bow and/or warp issues, or othermanufacturing issues such as equipment handling.

The SOI wafer carrier method overcomes both of these chal-lenges as the BOX does not limit processing temperature like gluedoes, and both the device and carrier wafers are silicon, so the coef-ficients of thermal expansion are perfectly matched.

5. Image sensors

Image sensors are a rapidly-growing segment of the automotiveelectronics market. As today’s (and tomorrow’s) cars become moreand more sophisticated and incorporate collision avoidance andautonomous driving, the need for image sensors will continue toexpand. Today’s cars have the potential for 20 or more sensorsper vehicle for back-up cameras, blind spot detection, collisionwarning, and numerous other applications as displayed in Fig. 12.

Like any emerging market, automotive image sensors presentboth challenges and opportunities. The rapid adoption of LED light-ing in both vehicles and traffic signs has made the problem of LEDflicker in video viewing and machine vision a high priority forautomotive OEMs.

ON Semiconductor has positioned itself as a leader in LEDFlicker Mitigation (LFM) technology with the release of AR0231AT,a CMOS image sensor that eliminates high frequency LED flickerfrom traffic signs and vehicle LED lighting and allows Traffic SignReading algorithms to operate in all light conditions. AR0231AT

Fig. 11. SOI silicon wafer carrier IGBT process flow.

Fig. 13. Stacked wafer configuration.

Fig. 12. Automobile imaging sensor opportunities.


uses the latest 3.0 lm Back Side Illuminated (BSI) pixel with ONSemiconductor’s DR-PixTM technology.

BSI technology also offers higher quantum efficiency (QE) andreduced cross-talk.

Stacked wafer technology is another image sensor technologyopportunity. In a stacked wafer process, one wafer contains thepixels while the other contains the mixed signal devices. The ‘‘sen-sor” wafer is then bonded to the ‘‘ASIC” wafer as shown in Fig. 13.This approach allows for individual optimization of each wafer forboth cost and performance. Fig. 14 shows the resulting cross-section of Pixel and ASIC wafers connected using through-siliconvias (TSV).

6. Conclusions

The market for power management ICs and Discretes continuesto grow at a steady pace thanks to new automotive technologies,the proliferation of ever-more sensor applications, and the ‘‘Inter-net of Things.” SOI technologies offer numerous cost, performance,and integration improvement opportunities. Using SOI integration,chip manufacturers are able to shrink parts, offer both low andhigh voltage devices in a single chip, improve IGBT performancewithout suffering the trade-offs seen in bulk technologies, and cre-ate novel sensor technologies. SOI technologies also offer the

chance to reduce parasitics, leading to improved performanceand more accurate models, which in turn, lead to reduced develop-ment costs and faster times to market.

Fig. 14. Stacked wafer cross-section.


Acknowledgements

The authors extend their thanks to Technische Universitat Wien(TUWien), the hosting institute for EUROSOI-ULIS 2016, as well asthe Conference’s Chairmen, Dr. Viktor Sverdlov and Dr. SiegfriedSelberherr.

The authors also thank our many colleagues at ON Semiconduc-tor whose projects and products are represented in the informationpresented here.

References

[1] Olsson J. High voltage SOI devices for automotive applications. Science andTechnology of Semiconductor-on-Insulator Structures and Devices Operating ina Harsh Environment. Netherlands: Springer; 2006. p. 155–66.

[2] Heinle U, Pinardi K, Olsson J. Vertical high voltage devices on thick SOI withback-end trench formation. In: Solid State Device Research Conf.. p. 295–8.

[3] S. Bernstein, Auto Semiconductors Report, September 2012.[4] Pop E et al. Energy dissipation and transport in nanoscale devices. Nano Res.

2010;3(3):147–69.[5] Arnold E, Pein H, Herko SP. Comparison of self-heating effects in bulk-silicon

and SOI high-voltage devices. In: Int. Electron Devices Meeting, San Francisco,CA. p. 813–6.

[6] G.P. Hosey, Modeling heat dissipation in an SOI device – finite element analysisat semiconductor die level, in: Joint Int. EUROSOI Workshop and Int. Conf. onUltimate Integration on Silicon, Vienna, 2016, pp. 206–209.

[7] H. Hauenstein, High-Voltage IGBTs Move into Automotive Apps, ElectronicDesign, October 2010.

http://refhub.elsevier.com/S0038-1101(16)30200-3/h0005














Reliable gate stack and substrate parameter extraction based on C-Vmeasurements for 14 nm node FDSOI technology


⇑ Corresponding author at: CEA-Leti, MINATEC Campus, 38054 Grenoble Cedex 9,France.

E-mail address: [email protected] (B. Mohamad).

B. Mohamad a,b,⇑, C. Leroux a, D. Rideau c, M. Haond c, G. Reimbold a, G. Ghibaudo b

aCEA-Leti, MINATEC Campus, 38054 Grenoble Cedex 9, FrancebUniv. Grenoble Alpes, IMEP-LAHC, MINATEC/INPG, CS 50257, 38016 Grenoble, Francec STMicroelectronics, BP 16, 38920, France

a r t i c l e i n f o a b s t r a c t



Keywords:Effective work functionEquivalent oxide thicknessChannel thicknessBuried oxide thicknessFully depleted silicon on insulator

Effective work function and equivalent oxide thickness are fundamental parameters for technology opti-mization. In this work, a comprehensive study is done on a large set of FDSOI devices. The extraction ofthe gate stack parameters is carried out by fitting experimental CV characteristics to quantum simulation,based on self-consistent solution of one dimensional Poisson and Schrodinger equations. A reliablemethodology for gate stack parameters is proposed and validated. This study identifies the process mod-ules that impact directly the effective work function from those that only affect the device threshold volt-age, due to the device architecture. Moreover, the relative impacts of various process modules on channelthickness and gate oxide thickness are evidenced.


1. Introduction

The effective Work function (WFeff) and the Equivalent Oxidethickness (EOT) are key parameters for FDSOI device characteriza-tion. WFeff and EOT are the values of Work Function and Thicknessthat an ideal Metal/SiO2 gate stack should have to account for themeasurements. They directly influence Capacitance Equivalentthickness (CET), Threshold voltage (VT) and therefore on-current.Both are strongly related to the process: dielectric thickness, metalgate work function and dielectric interface dipole [1]. Formermethodologies [2,3] for automatic and statistical extraction ofWFeff and EOT were fitted for bulk but are no longer sufficient forFDSOI technology. Capacitance–Voltage extraction of the flat bandvoltage (VFB) in the accumulation region has traditionally been themethod for the WFeff extraction for the bulk technology. Theabsence of CV signal in the accumulation and flat band regionscompared to standard bulk capacitance pushes us to look for alter-native solution for WFeff and EOT extraction. Indeed the inversionregion (VT) still available in FDSOI can be exploited to extract theWFeff and EOT. The extraction difficulties are due to the complexityof the FDSOI structure (Fig. 1) and the strong influence on VT of sev-eral technological parameters such as: channel thickness tsi, buried

oxide (BOX) thickness tbox and well doping level of substrate NWell

at BOX backside. We will present a comprehensive study onnumerous devices combining the process modules on metal gate,dielectric, channel material (Si & SiGe) and well implantation type(P & N doped). Reliable parameter extraction is presented by com-parison between quantum simulations and experimental CV char-acteristics allowing the identification of the process modules thatreally influence EOT and WFeff.

2. Process technology and experimental results

Fig. 1 shows two standard FDSOI MOS devices (P (a) & N (b)MOS) that feature a gate stack characterized by a metal bilayer(Poly and TiN) on the top of oxide bilayer (High-k dielectric HfON& SiON). To get such devices, the process starts from an ultra-thinsilicon body over a buried oxide. The strained Si0.75Ge0.25 channel(cSiGe) is selectively processed in PMOS areas by epitaxy growthprocess followed by a Ge condensation, before shallow trench iso-lation (STI) regions are patterned and the back side wells areimplanted. The channel thickness is around 6–8 nm of Si or Si0.75-Ge0.25 over a 20 nm BOX with a P or N-Well with a 1018 cm�3 dop-ing level at its backside. Two different interlayer (SiON) dielectrics,can be deposited corresponding to two different final oxide thick-nesses: EOT = 1 nm for GO1 and EOT = 3 nm for GO2. The bilayerhigh-k HfON/SiON is deposited by Atomic Layer Deposition, MetalOrganic Vapor deposition and decoupled plasma nitridation. To







Source

NWell

Gate

N+Channel SiGeGe

BOX

STI

STI

P+P+GO1 or GO2

PGateDrain Body

(a) Standard PMOS (b) Standard NMOS

Source

PWell

Gate

P+Channel Sii

BOXST

I

STI

N+N+GO1 or GO2NGate

Drain Body

Fig. 1. Standard (a) PMOS and (b) NMOS FDSOI devices: both feature a gate stack TiN + Poly on a bilayer oxide HfON + SiON but (a) with SiGe channel and N-Well substrateand (b) with Si channel and P-Well substrate. The interlayer (SiON) dielectrics, is deposited in order to have two different final oxide thicknesses: EOT = 1 nm for GO1 andEOT = 3 nm for GO2.

Table 1Set of different FDSOI devices featured by combining different process modules on metal gate, dielectric, channel (Si & SiGe) and well (P & N doped). The 4th and 5th columnsreport on the DVT shift evidenced in Figs. 2 and 3.

Device Device definition (GO1 & GO2) GO1 GO2

Channel Metal Well DVt [mV] DVt [mV]

NMOS Si N P Ref. Ref.Si N N 45 115Si P P 90 45

PMOS SiGe P N Ref. Ref.SiGe N P 60 90SiGe N N 100 45Si P N 320 250Si N N � 295

0.0

0.5

1.0

1.5

2.0

2.5 Standard PMOS NGate + PWell NGate Si channel

Cgc

[10-2

F/m

2 ]

Vg [V]-1.0 -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 1.0

Standard NMOS NWell PGate

90mV45mV60mV

320mV100mV

Fig. 2. Gate-to-channel capacitance at back bias VB = 0 V for PMOS and NMOS FDSOI GO1 with VT shift to reference architecture.

B. Mohamad et al. / Solid-State Electronics 128 (2017) 10–16 11

obtain N and P gate types, before the final metal gate, a sacrificialgate is deposited, specifically to each N or P gate type. Sacrificialgate includes specific additives which are diffused by thermalannealing in order to adjust dipole at oxide bilayer inner interface[1,4]. The final metal gate bilayer (TiN + Poly) is the same for all thedevices (N and P-MOS) and it is deposited right after the sacrificialgate etching. After final gate deposition, the Source-Drain implan-tations (specific to each FDSOI MOS type) are carried out, followed

by final annealing. From these standard FDSOI MOS, a wide set ofdevices has been obtained by combining the process modules onmetal gate, dielectric, channel and well type (Table 1).

In order to carry out the parameter extraction of WFeff and EOT,two types of measurements have been performed on this set ofdevices: the gate-to-channel capacitance (Cgc) and the back-gate-to-channel capacitance (Cbc) [5]. For Cgc measurements, the smallAC signal is applied on the Gate and the induced capacitive current

0.0

0.2

0.4

0.6

0.8

1.0

Standard PMOS NGate + PWell Ngate Si channel NGate + Si channel

Cgc

[10-2

F/m

2 ]

Vg [V]-1. 5 -1. 2 -0. 9 -0. 6 -0. 3 0.0 0.3 0.6 0.9 1.2 1.5

Standard NMOS NWell Pgate

45mV

250mV

90mV45mV115mV

Fig. 3. Gate-to-channel capacitance at back bias VB = 0 V for PMOS and NMOS FDSOI GO2 with VT shift to the reference architecture.

Oxide

Source

P/N-Well

Gate

P/N+ChannelSi /SiGe

BOX

STI

STI

N/P+N/P+

N/P-GateDrain Body

z

x

N/P-Gate ChannelSi /SiGe BOX P/N-Well

Quantum Classical

Oxide

Classical

z

xQuantumClassical

(a)

(b)

Fig. 4. 1-D (a) Cross section of typical FDSOI transistor designed and measured in this study. (b) 1-D structure simulated to account of the transistor electrostatics (yellowline). (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)

12 B. Mohamad et al. / Solid-State Electronics 128 (2017) 10–16

is measured on Source and Drain. For Cbc measurements, the smallAC signal is applied on the back side contact and the inducedcapacitive current is still measured on Source and Drain. In boththe experimental configurations Source and Drain are grounded.These measurements have been performed for all the devices andtheir relative gate-to-channel capacitances, corrected by subtract-ing their parasitic capacitances, are reported in Fig. 2 for GO1devices and Fig. 3 for GO2 devices. As summarized in Table 1, wehave the opportunity to test various devices, N-MOS and P-MOS,on which we can get various channel materials, Gate type and Welltype for ground plane. A reference can be identified for each MOSstructure. N-MOS has a N-Gate and P ground plane with a Si chan-nel whereas P-MOS has P-Gate and N ground plane with a SiGe

channel. Arrows in Figs. 2 and 3 identifies the VT shift from refer-ence when we modify some process module of the gate stack. VT

shifts are reported in Table 1 and we will try in following part toaccount for such DVT variations.

3. Simulation and extraction

The extraction of gate stack parameters (EOT and WFeff) forthese devices (Table 1) is obtained by fitting Quantum Simulationto experimental capacitance-voltage characteristics (CV). Indeed,for a specific gate stack (WFeff, EOT, tsi, tbox, NWell), we can simulatethe channel charge of the MOS device and compare it to experi-

0.0

0.2

0.4

0.6

0.8

1.0

WFeff

=4.695eVEOT=3.13nmt

si=7.9nm

tbox

=20nmN

d well=1018cm-3

Vg [V]

Cgc

[10

-2F/

m2 ]

Standard PMOS GO2

WFeff

=4.705eVEOT=3.13nmt

si=7nm

tbox

=20nmN

d well=1018cm-3

-1.0 -0.5 -1.0 -0.5 -1.0 -0.5

WFeff

=4.680eVEOT=3.13nmt

si=7nm

tbox

=17nmN

d well=1018cm-3

Fig. 5. Standard PMOS GO2 gate-to-channel capacitance compared with simulation (UTOXPP) with different channel and BOX thicknesses (each fit leads to a certain WFeffand EOT extraction).

N-Well

N+

BOX

STI

STI

P+P+

GateOxide

SA

-8 -7 -6 -5 -4 -3 -2 -1 00.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

GO2

GO1

UTOXPPtsi=7.9nm

tbox

=20nm

UTOXPPtsi=7nm

tbox

=20nm

C bc [1

0-3F/

m2]

Vb [V]

Channel SiGe

Fig. 6. Experimental standard PMOS GO1 & GO2 back-gate-to-channel capacitance compared to simulation (UTOXPP) leading to tbox extraction.


mental measurements. We can consider that WFeff and EOT arecorrectly identified if we account for the various dependences ofthe experimental capacitances with Gate and Body biases. Thesesimulations are based on the self-consistent solutions of the Pois-son and Schrodinger equations (PS), carried out by NUMERICADSimulator (UTOXPP [6]).

In order to accurately calculate the charge distribution in thechannel and substrate of the FDSOI stack (Fig. 4), paraboliceffective-mass approximation (EMA) of the valence andconduction band are taken into account. As shown in Fig. 4, thePS simulations are carried out in z-direction, orthogonal to thechannel-oxide interface (Fig. 4a yellow line). With the purpose ofincluding electron and hole wave function penetration, the PS for-malism is not just solved in the channel and substrate (Well) butalso in complementary regions as the front oxide (EOT) and backoxide (BOX) (Fig. 4b). To calibrate the EMA simulation parameters,a more complex and accurate 6-K�P band self-consistent simulation

has been performed, leading to corrected in-plane effectivemasses:i.e. for the heavy hole valence band (mDOS-HH xy) of 2.5m0 for Si and1.5m0 for SiGe channel [3], with m0 as the electron mass.

The calculated density of charge q(z, Vg, Vb) from the PS equa-tion can be used to compute the channel charge as

QchðVg;VbÞ ¼Z zf

zsqðz;Vg;VbÞdz ð1Þ

From such channel charge, we can calculate the gate-to-channelcapacitance, defined by

Cgc ¼ dQchðVg;VbÞdVg

ð2Þ

and the back-gate-to-channel capacitance by

Cbc ¼ dQchðVg;VbÞdVb

ð3Þ

Cgc

[10-2

F/m

2 ]

Vb=0V,-1V...-7V

Standard PMOS GO2

UTOXPPt

si=7.9nm

WFeff

=4.695eV

Vg [V]

-1.5 -1.0 -0.5 0.0 0.5 1.0-1.5 -1.0 -0.5 0.0 0.5 1.00.0

0.2

0.4

0.6

0.8

1.0

Vb=0V,-1V...-7V

UTOXPPt

si=7nm

WFeff

=4.705eV

Fig. 7. Standard PMOS GO2 gate-to-channel capacitance vs simulation (UTOXPP) with two different channel thicknesses (7.9 nm tsi is mandatory for fitting all CVs).

0.0

0.2

0.4

0.6

0.8

1.0

1.2

Vb=7V,6V...0V

tsi=6.8nm

tbox

=20nmN

a well=1018cm-3

NMOS GO2

UTOXPPWF

eff=4.55eV

EOT=2.85nm

Cgc

[10

-2F/

m2 ]

-1.0 -0.5 0.0 0.5 1.0 -1.0 -0.5 0.0 0.5 1.0

Vb=7V,6V...0V

tsi=6.8nm

tbox

=20nmN

d well=1018cm-3

NMOS GO2 NWell

UTOXPPWF

eff=4.555eV

EOT=2.85nm

Vg [V]

Fig. 8. Fitting between simulations and experiments for two MOS devices having two different well types at back side of buried oxide.


These simulated capacitances will be compared with the exper-imental CV curves in order to extract the FDSOI stack parameters.To evaluate the quality of parameter extraction, various hypothe-ses on physical parameters (tbox, tsi) have been compared for asame experimental device (Standard PMOS GO2). A good fit ofCgc(Vg) can be obtained for the three different set of parameters(Fig. 5) leading to three different values for EOT and WFeff. Thesevalues are given with a precision of 0.01 nm and 3–4 meV.Whereas, EOT is found to be independent of tbox and tsi values(with precision below 0.01 nm), a 25 meV WFeff uncertainty isfound. Such a result confirms the importance of a previousextraction on tbox and tsi in order to accurately extract WFeff. Toextract tbox, we have recently proposed a new CV measurement,the Cbc earlier mentioned, with back side wafer contact as Gate[5]. Fig. 6 shows back-gate-to-channel capacitance experimentalconfiguration and measurements results.

The corresponding CV curves for GO1 and GO2 (Fig. 6) showscharacteristics similar to the standard gate-to-channel capacitancebut at a significantly lower level. Adjustment with quantum simu-

lation makes possible a reliable extraction of the box thickness,independently of tsi and EOT [5]. A 20 nm box thickness is neces-sary in order to fit Cbc capacitances for both the standard PMOS(GO1 and GO2). Concerning tsi, it can be obtained by comparisonbetween simulations and experiments on a large set of CV charac-teristics for which back biases vary from 0 V to large values leadingto back interface inversion (Fig. 7). We can notice that there is onlyone channel thickness that takes into account the real capacitancedeformation for strong back interface inversion. tbox and tsi areexpected to shift VT, WFeff could also vary with channel material(Si versus SiGe) but it is obviously independent of the Source andDrain or Well type. Indeed, during the device fabrication, theimplantation of the Source-Drain as well as the back substrate wellare carried out without any influence on the MOS stack. A reliableparameter extraction must verify the independence of WFeff andEOT with variations on types of Source and Drain or Well implan-tation. This feature has been confirmed on three different MOSdevices, corresponding to two different well types (Fig. 8) andtwo different MOS types (Fig. 9). Moreover Fig. 9 validates the good

-1.5 -1.0 -0.5 0.0 0.5 1.00.0

0.2

0.4

0.6

0.8

1.0

1.2

NMOSPMOS

tsi=6.8nmtbox=20nmNd well=1018cm-3

WFeff=4.555eVEOT=2.85nm

Cgc

[10-2

F/m

2 ]

Vg [V]

Fig. 9. Fitting between simulation and experimental data for two different MOSdevices having a same gate stack and two different source and drain implantations(GO2 NMOS with N-Well & GO2 PMOS with N-Well and N-Gate metal and Sichannel).


choice of mDOS-HH of 2.5m0 for Si channel [3]. Indeed, only a goodvalue of mass, related to electrons (conduction band) and holes(valence band), can reproduce both capacitances with a sameWFeffand EOT.

4. Results

In Fig. 10, are shown the WFeff and EOT extracted for the fifteendifferent tested MOS devices (Table 1). The agreement reportedabove on WFeff & EOT for three different MOS structures (Figs. 8and 9) is identified in Fig. 10 with a blue arrow. Among the fifteendifferent devices, other configurations correspond to same gatestack and channel material but different Source and Drain or backside well types. They all lead to a good agreement which areidentified with green arrows in Fig. 10.

4.50

4.55

4.60

4.65

4.70

4.75

4.80

4.85

0.7 0.8 0.9 1.0 1.1

Si SiGe

GO1

WF ef

f [eV

]

EOT WFeff

WFeff

(N P)=100mV(Si SiGe)=145mV

Fig. 10. WFeff versus EOT for different PMOS and NMOS FDSOI structures. Impact of Ge

We report in Fig. 11 the dependence of tsi with EOT. It appearsto depend only on channel and oxide type. Indeed, it is equal to6.1 nm for Si and 7 nm for SiGe for all GO1 devices and 6.8 nmfor Si and 7.9 nm for SiGe for all GO2 devices. SiGe channel is foundto be 1 nm thicker than Si channel and, in both cases, GO2 processleads to less channel consumption.

tbox is reported in Fig. 12 and it is found at the same 20 nm valuefor all the different MOS devices, a value corresponding to the tar-get of the SOI substrate. EOT is reported in Figs. 10–12. It dependsprimarily on oxide type (GO1 and GO2) but also on channel mate-rial. As already evidenced in previous studies [7], the gate oxideformation leads to a slight interlayer regrowth in case of SiGe sub-strate. We notice here an interlayer regrowth around 0.12 nm forGO1 and 0.3 nm for GO2.

WFeff appears to depend on gate type, channel material andoxide (GO1 and GO2). Considering first GO1, we notice an averageshift of 100 mV from N to P metal gate. It is the expected effect ofAl dipole created at HfON/SiON interface by the sacrificial gate pro-cess [1]. With SiGe channel, WFeff report an additional shift of145 mV. In Fig. 2 we can notice that VT shift with SiGe channelreaches 320 mV. It is partially explained by the shift of valenceband for SiGe semiconductor, but an additional WFeff shift of145 mV is required to account for the whole VT shift. It has beenattributed to an interface dipole at SiGe/SiON interface [7]. ForGO2, both dipoles at HfON/SiON and SiGe/SiON device interfacesdecreases of 45 and 95 mV, respectively.

5. Conclusion

Robust EOT and WFeff extractions on FDSOI devices have beenproposed through a methodology based on comparison betweenexperimental CV characteristics and Poisson-Schrodinger simula-tions. To be reliable, it requires a first identification of buried oxidethickness (tbox) and channel thickness (tsi). It has been validated ona large set of MOS devices. Such analysis evidences the relativeimpact of process modules on tsi, EOT and WFeff. Channel thicknessand equivalent oxide thickness appear to depend on the channelmaterial and the gate oxide interlayer process. Whereas effective

2.7 2.8 2.9 3.0 3.1 3.2 3.3

[nm]

Si

SiGe

GO2

WFeff

WFeff

(N P)=45mV(Si SiGe)=95mV

and sacrificial metal gate and coherence of WFeff and EOT extractions are shown.

6.0

6.3

6.6

6.9

7.2

7.5

7.8

8.1

0.7 0.8 0.9 1.0 1.1 2.7 2.8 2.9 3.0 3.1 3.2 3.3

tSi

tSi

(Si SiGe)=1.1nm for GO2(Si SiGe)=1nm for GO1

SiGe

Si

GO1

t Si [n

m]

EOT [nm]

SiGe

Si

GO2

Fig. 11. tsi versus EOT for different PMOS and NMOS FDSOI structures. Impact of Ge and coherence of tsi and EOT extractions are shown.

18.0

18.5

19.0

19.5

20.0

20.5

21.0

21.5

22.0

0.7 0.8 0.9 1.0 1.1 2.7 2.8 2.9 3.0 3.1 3.2 3.3

GO1

Si SiSiGe SiGe

EOT [nm]

t BO

X [n

m]

GO2

Fig. 12. tbox versus EOT for different PMOS and NMOS FDSOI structures. Impact of Ge and coherence of tbox and EOT extractions are shown.


work function is a combined effect of interlayer, channel interlayerand sacrificial gate type.

Acknowledgements

The authors would like to thank MINOS Laboratory of FrenchANR and WAYTOGO FAST ECSEL Project for their support for thiswork.

References

[1] Suarez-Segovia C, Leroux C, Caubet P, Domengie F, Reimbol G, Romano G, et al.Effective work function modulation by sacrificial gate aluminum diffusion onHfON-based 14 nm NMOS devices. Microelectr Eng 2015;147:113–6.

[2] Leroux C, Baudot S, Charbonnier M, Van Der Geest A, Caubet P, Toffoli A, et al.Investigating doping effects on high-k metal gate stack for effective workfunction engineering. Microelectr Eng 2007;84:2408–11.

[3] Soussou A, Leroux C, Rideau D, Toffoli A, Romano G, Tavernier C, et al.Parameters extraction in SiGe/Si pMOSFETs using split CV technique. In: Proc ofULIS conf, Cork (Ireland). p. 41–4.

[4] Suarez-Segovia Carlos, Leroux C, Domengie F, Dabertrand K, Joseph V, RomanoG, et al. Effective work function engineering by sacrificial lanthanum diffusionon HfON-based 14 nm NFET devices. In: 45th European Solid State DeviceResearch Conference (ESSDERC), 14–18 September 2015. p. 246–9.

[5] Mohamad B, Ghibaudo G, Leroux C, Josse E, Reimbold G. Full front and back splitC-V characterization of CMOS devices from 14 nm node FDSOI technology. In:Proc of S3S conf, Rohnert Park (USA). Section 9a.4.

[6] Garetto D, Rideau D, Tavernier C, Leblebiciand Y, Schmid A, Jaouen H. Advancedphysics for simulation of ultrascaled devices with UTOXPP Solver. In: Proc ofNTSI-nanotech 2011, Boston (USA). p. 607–10.

[7] Soussou A, Leroux C, Rideau D, Toffoli A, Romano G, Saxod O, et al.Understanding Ge impact on VT and VFB in Si1 � xGex/Si pMOSFETs.Microelectr Eng 2013;109:282–4.

































Scaling/LER study of Si GAA nanowire FET using 3D finite element MonteCarlo simulations


⇑ Corresponding author at: ESDC, College of Engineering, Swansea University,Swansea SA1 8EN, Wales, United Kingdom.

E-mail address: [email protected] (M.A. Elmessary).

Muhammad A. Elmessary a,c,⇑, Daniel Nagy a, Manuel Aldegunde d, Natalia Seoane e, Guillermo Indalecio e,Jari Lindberg f, Wulf Dettmer b, Djordje Peric b, Antonio J. García-Loureiro e, Karol Kalna a

a ESDC, College of Engineering, Swansea University, Swansea SA1 8EN, Wales, United Kingdomb ZCCE, College of Engineering, Swansea University, Swansea SA1 8EN, Wales, United KingdomcDept of Mathematics & Engineering Physics, Faculty of Engineering, Mansoura University, Mansoura 35516, EgyptdWCPM, School of Engineering, University of Warwick, Coventry CV4 7AL, England, United KingdomeCITIUS, Universidade de Santiago de Compostela, 15782 Santiago de Compostela, Galicia, SpainfVarian Medical Systems Finland, Helsinki, Finland




Keywords:Schrödinger quantum correctionsMonte Carlo simulationsGAA nanowire FETLERVariability

a b s t r a c t

3D Finite Element (FE) Monte Carlo (MC) simulation toolbox incorporating 2D Schrödinger equationquantum corrections is employed to simulate ID-VG characteristics of a 22 nm gate length gate-all-around (GAA) Si nanowire (NW) FET demonstrating an excellent agreement against experimental dataat both low and high drain biases. We then scale the Si GAA NW according to the ITRS specificationsto a gate length of 10 nm predicting that the NW FET will deliver the required on-current of above1 mA/lm and a superior electrostatic integrity with a nearly ideal sub-threshold slope of 68 mV/decand a DIBL of 39 mV/V. In addition, we use a calibrated 3D FE quantum corrected drift-diffusion (DD)toolbox to investigate the effects of NW line-edge roughness (LER) induced variability on the sub-threshold characteristics (threshold voltage (VT), OFF-current (IOFF), sub-threshold slope (SS) and drain-induced-barrier-lowering (DIBL)) for the 22 nm and 10 nm gate length GAA NW FETs at low and highdrain biases. We simulate variability with two LER correlation lengths (CL = 20 nm and 10 nm) and threeroot mean square values (RMS = 0:6; 0:7 and 0:85 nm).


1. Introduction

Gate-All-Around (GAA) nanowire (NW) FETs are considered tobe excellent candidates for future CMOS integration for sub-10 nm digital technology to continue transistor downscaling [1].The GAA NW FETs have superior electrostatics and immunity toshort channel effects while still delivering a large on-current [2–4]. However, to have a full realistic assessment of these potentialcandidates, we must take into account the exact device geometryand also determine how different sources of device variabilitycan affect device characteristics and reliability. Variability of tran-sistor characteristics is induced by material properties and by fab-rication processes and can affect their performance in circuits. Oneof such sources is line-edge roughness (LER) which has a majorimpact on variability in NW/FinFETs [3,5–7].

In this work, we report on performance, scaling and variabilityof nanoscale GAA Si NW FETs. We use an in-house 3D Finite Ele-ment (FE) Monte Carlo (MC) simulation toolbox which includesnewly integrated calibration-free 2D FE anisotropic Schrödingerequation based quantum corrections (SEQC) [8] along the devicechannel. More details on the 3D FE MC toolbox are in Refs. [8–11]. Here, we start by comparing results from our 3D FE SEQCMC toolbox against experimental data of a 22 nm gate lengthGAA Si NW FET [2] with a h110i channel orientation. We then sim-ulate the h100i channel orientation for the same NW for compar-ison. Next, we scale the NW to a gate length of 10 nm according tothe International Technology Roadmap for Semiconductors (ITRS)specifications [12] and simulate the h100i and h110i channel ori-entations with the 3D FE SEQC MC. Finally, we use our 3D quantumcorrected FE drift-diffusion (DD) simulation toolbox to study theLER-induced variability on the sub-threshold characteristics(threshold voltage (VT), OFF-current (IOFF), sub-threshold slope(SS) and drain-induced-barrier-lowering (DIBL)) at both low andhigh drain biases for the 22 nm and the 10 nm gate length GAANW FETs. We simulate the variability with LER correlation lengths







18 M.A. Elmessary et al. / Solid-State Electronics 128 (2017) 17–24

(CL) of 20 nm and 10 nm and three root mean square values (RMS)of 0:6; 0:7 and 0:85 nm chosen to represent the RMS observed inexperiments [2,3].

-30 -20 -10 0 10 20 30

Distance along x-axis [nm]

0

1×1019

2×1019

3×1019

4×1019

5×1019D

opin

g C

once

ntra

tion

[cm

-3]

22 nm

Gate

X X

Sour

ce v

olum

e

Dra

in v

olum

e

2. 3D Monte Carlo simulations

The 3D FE method incorporated into 3D SEQC MC toolbox iscapable of accurately describing the complex 3D geometry of thenanoscale devices. The accurate description of the simulationdomain in nanoscale semiconductor devices is essential in deter-mining quantum transport at highly non-equilibrium conditions.In our case, we chose a semi-classical transport technique, a 3Densemble MC [8–11], with calibration-free quantum confinementcorrections, the SEQC. Our in-house 3D FE MC simulation toolboxemploys fully anisotropic 2D FE Schrödinger equation based quan-tum corrections (QC) [8] which depends on valley orientation andconsiders longitudinal and transverse electron effective masses.The MC transport engine considers an analytical anisotropic non-parabolic bandstructure model with the same longitudinal andtransverse masses and the following scattering processes: theacoustic phonon scattering, non-polar optical phonon scattering(g; f -processes) [13], ionised impurity scattering using the third-body exclusion model by Ridley [14] with a static screening modelself-consistently calculating Fermi energy and electron tempera-ture [15], and the interface roughness scattering using Ando’smodel [16]. This combination has been shown to be a very goodcompromise between the precision and the speed for accuratephysical simulations of carrier transport in nanodevices whichare strongly quantum confined systems at highly non-equilibrium transport conditions [9–11].

We start by comparing results from our 3D SEQC MC toolboxagainst experimental data of a 22 nm gate length GAA Si NW [2]with a h110i channel orientation. The NW has elliptical cross-section (Fig. 1) with a shorter diameter of 11:3 nm and a longerdiameter of 14:22 nm; with an effective diameter (elliptical cir-cumference/p) DNW = 12:8 nm and EOT = 1:5 nm which can beaccurately described by the FE method.

The 3D FE quantum corrected (QC) drift-diffusion (DD) simula-tions using density gradient (DG) [17] were used to reverse engi-neer a doping profile in the sub-threshold region at VD = 0.05 V

Fig. 1. Schematic of the 22 nm gate length n-channel Si GAA nanowire, showingLER and examples of 2D slices used for Schrödinger solver.

and VD = 1.0 V by changing the Gaussian-like doping profile (a dop-ing maximum and a spread X which determine the abruptness ofthe doping profile) as shown in Fig. 2. The effective masses in theDG approach were used as calibration parameters. Fig. 3 showsexamples of this reverse engineering process for the sub-threshold region which achieved excellent agreement with a max-imum doping of 5� 1019 cm�3, a work function of 4:512 eV, and aS/D size of 30:8 nm. We then use the 3D FE SEQC MC toolbox tosimulate the ID-VG characteristics of the 22 nm gate GAA Si NWat low and high drain biases achieving an excellent agreement withthe experimental data [2] as can be seen in Fig. 4. The current isnormalised by nanowire perimeter (elliptical circumfer-ence = 40:21 nm). Note here that the resulted drain current from3D SEQC MC simulations gives the agreement with experimentwithout any need for additional lumping of external resistancefrom the experiment. This is because the S/D resistance is accu-rately reproduced in physically based 3D ensemble MC techniquethanks to the size of the S/D access regions included into simula-tion domain.

Fig. 5 compares the average electron velocity at VG = 0.8 V andVD = 1.0 V for the 22 nm gate length GAA NW along the h100iand the h110i channel orientations, along with the average veloc-

Fig. 2. Cross-section of Gaussian-like doping profile along the transport x-directionin the 22 nm gate length GAA NW FET.

-0.1 0 0.1 0.2 0.3 0.4

Gate Voltage [V]

1×10-10

1×10-9

1×10-8

1×10-7

1×10-6

1×10-5

1×10-4

1×10-3

Dra

in C

urre

nt [

A/µ

m]

DD VD

=0.05 V, X/2, S/D size=30.8 nmDD V

D=1.0 V, X/2, S/D size=30.8 nm

DD VD

=0.05 V, X, S/D size=22 nmDD V

D=1.0 V, X, S/D size=22 nm

-0.1 0 0.1 0.2 0.3 0.41×10

-10

1×10-9

1×10-8

1×10-7

1×10-6

1×10-5

1×10-4

1×10-3 IBM V

D=0.05 V

IBM VD

=1.0 VMC V

D=0.05 V, X/2, S/D size=30.8 nm

MC VD

=1.0 V, X/2, S/D size=30.8 nm

ND

= 5e19 cm-3

Fig. 3. Devising doping profile for the 22 nm GAA NW FET at VD = 0.05 V andVD = 1.0 V via DD simulations by changing the size of the S/D region and the dopingspread X (open red triangles and orange squares). Final MC simulations (green opencircles and stars) are compared to experimental data (black full circles and stars).(For interpretation of the references to color in this figure legend, the reader isreferred to the web version of this article.)

0 0.2 0.4 0.6 0.8 11×10

-9

1×10-8

1×10-7

1×10-6

1×10-5

1×10-4

1×10-3

Dra

in C

urre

nt [

A/µ

m]

MC <100> VD

=0.05 VMC <100> V

D=1.0 V

0 0.2 0.4 0.6 0.8 1Gate Voltage [V]

0.0

5.0×10-4

1.0×10-3

1.5×10-3

2.0×10-3

MC <110> VD

=0.05 VMC <110> V

D=1.0 V

IBM <110> VD

=1.0 VIBM <110> V

D=0.05 V

22nm NW <110> / <100>

Fig. 4. ID-VG characteristics for the 22 nm GAA nanowire from the 3D FE MC withanisotropic Schrödinger quantum corrections, in the h110i (circles) and h100i(stars) channel orientations, compared against experimental data in the h110i(triangles) orientation [2].

Distance along x-axis [nm]

0.0

1.0×105

2.0×105

3.0×105

Ave

rage

Vel

ocity

[m

/s]

total

-30 -20 -10 0 10 20 -20 -10 0 10 20 30

Δ1Δ2Δ3

22 nm NW <100>

Sour

ce

Dra

in

Gate

Dra

in

Sour

ce

22 nm NW <110>

Gate

Fig. 5. Average electron velocity at VD = 1.0 V and VG = 0.8 V along the 22 nm gatelength GAA NW (3D MC) along the h100i and h110i channel orientations. The zerois set in the middle of the channel.

Fig. 6. Eigenmodes (jwðy; zÞj2) corresponding to the lowest energy eigenvalue of thethree D valleys, in the middle of the h110i channel for the 22 nm (top, at VD = 1:0 V)and 10 nm (bottom, at VD = 0:7 V) Si GAA NW at VG = 0:8 V.

0 0.2 0.4 0.6 0.8 1Gate Voltage [V]

1×10-10

1×10-9

1×10-8

1×10-7

1×10-6

1×10-5

1×10-4

1×10-3

Dra

in C

urre

nt [

A/µ

m]

VD

=0.05 V <100>V

D=0.05 V <110>

VD

=0.7 V <100>V

D=0.7 V <110>

0.0

5.0×10-4

1.0×10-3

1.5×10-3

2.0×10-3

10 nm NW

Fig. 7. ID-VG characteristics for the scaled 10 nm gate length GAA NW FET predictedby the 3D FE SEQC MC along the h100i and h110i channel orientations.

M.A. Elmessary et al. / Solid-State Electronics 128 (2017) 17–24 19

ity in the three silicon valleys D1, D2 and D3. We see that the elec-tron velocity exhibits a typical behaviour along the channel. Thetotal average velocity in the h100i orientation is higher than theone in the h110i orientation due to a higher electron mobility inthe h100i crystallographic orientation in Si. The source injectselectrons at relatively large injection velocity of about3:0� 104 m/s where they are quickly accelerated along the gatereaching their maximum velocity of 2:0=1:75� 105 m/s, respec-tively, on the drain side of the gate. Then electrons decelerate intoa heavily doped drain due to enhanced optical phonon emissionassisted by ionised impurity scattering [18].

In the h100i orientation channel, the D1 velocity is the smallestbecause it has the heaviest mass in the transport direction. The D2and D3 velocities are equal in the h100i channel device becausethey have the same effective transport masses. On the other hand,in the h110i channel, the D3 velocity is the largest because it hasthe lightest effective transport mass. The D1 and D2 velocitiesare equal because they have equal effective transport masses.

We then scale the Si GAA NW according to the ITRS specifica-tion [12] to a gate length of 10 nm and an EOT of 0:8 nm. Fig. 6

compares the eigenmodes (jwðy; zÞj2) corresponding to the lowestenergy eigenvalue, in the h110i channel orientation, of the threeD valleys in the middle of the channel for the 22/10 nm gate lengthGAA NW, respectively, at VD = 1.0/0.7 V and VG = 0.8 V (note that D1and D2 have the same effective mass tensor in the h110i channel

orientation, so they will have the same wavefunction). The asym-metry seen in the eigenmode of the D3 valley in the 22 nm gateNW FET (top–left) is the result of drain induced change into poten-tial in the channel at a large applied drain bias of 1:0 V. This effectwill not occur in the 10 nm gate device because this transistor,with a much stronger quantum confinement, has a much bettercontrol of the transport so that the drain induced change intopotential is negligible.

Fig. 7 shows ID-VG characteristics (the current is normalised bynanowire perimeter (elliptical circumference = 20:29 nm)) for thescaled 10 nm gate length NW FET at VD = 0.05 V and VD = 0.7 Valong the h100i and the h110i channel orientations obtained fromthe 3D FE SEQC MC. Table 1 compares device operating character-istics with gate lengths of 22 nm and 10 nm predicting that thescaling to the 10 nm gate will ensure superior electrostatic integ-

Table 1VT and sub-threshold slope (SS) at VD ¼ 0:05 V (LOW) and 1:0=0:7 V (HIGH) from theDD, DIBL from the DD and from the MC, and drive currents (IMC) at VG = 1:0 Vcomparing 22 and 10 nm GAA FETs.

Method Gate length [nm] 22 10

MC VT [V] 0.3 0.35DD SSLOW [mV/dec] 74 67DD SSHIGH [mV/dec] 76 68MC DIBLh100i [mV/V] 81 66MC DIBLh110i [mV/V] 64 39MC Ih100i [lA/lm] 1222 1320MC Ih110i [lA/lm] 1000 1100


rity of a nearly ideal sub-threshold slope of 68 mV/dec and a DIBLof 39 mV/V and satisfactory on-current (the on-current increase is� 8=10% for the h100i/h110i channel orientation with respect tothe 22 nm NW).

The threshold voltage (VT) is 0:3=0:35 V for the 22=10 nm gatelength NW FET. The scaled GAA NW has a better sub-thresholdslope (SS) at both low and high drain biases and a better drain-induced-barrier-lowering (DIBL) along the h100i and the h110ichannel orientations. Due to the fact that electrons have a highermobility in the h100i crystallographic orientation, both devicesdeliver a higher current for the h100i channel orientation thanfor the h110i channel at both low and high drain biases. For the22 nm and the 10 nm GAA NW FETs, the drain current in theh100i channel device is larger than in that with the h110i channelby � 30=20% at a low/high drain bias.

0.6 0.7 0.8

10

20

30

40

50

σVT [

mV

]

CL=20 nm , VD,low

CL=20 nm , VD,high

CL=10 nm , VD,low

CL=10 nm , VD,high

0.6 0.7 0.8

RMS [nm]

10

20

30

40

50

σVT [

mV

]

CL=20 nm , VD,low

CL=20 nm , VD,high

CL=10 nm , VD,low

CL=10 nm , VD,high

22nm NW 10nm NW

(a)

0.6 0.7 0.8

0.2

0.4

0.6

0.8

σlog

10(I

off[A

])

CL=20 nm , VD,low

CL=20 nm , VD,high

CL=10 nm , VD,low

CL=10 nm , VD,high

0.6 0.7 0.8

RMS [nm]

0.2

0.4

0.6

0.8

CL=20 nm , VD,low

CL=20 nm , VD,high

CL=10 nm , VD,low

CL=10 nm , VD,high

22nm NW 10nm NW

(c)

Fig. 8. Comparison of the VT, SS, log10(IOFF) and DIBL variability versus the RMS height duthe drain bias, and the correlation length (CL). VD,low = 0.05 V and VD,high = 1.0 V for the 22NW.

3. Line-edge roughness (LER)

Downscaling transistors to the nano regime increases the unde-sirable performance mismatch in identically designed transistors[19]. The line-edge roughness (LER) is considered as one of themajor sources of device variability [20] which may lead to seriousdevice parameter fluctuations and limit the performance in theVLSI circuit applications. Therefore, studying the LER variability,especially in GAA NWs which have all the channel interfacesaffected by the LER, is essential for predicting device behaviourin digital circuits. Here, we study the effect of uncorrelated LER(where we apply different LER profile at each side of the device,thus changing the width of the device across its length) using Four-ier synthesis with Gaussian autocorrelation [21] implemented asdescribed in Refs. [20,22]. The LER is characterised by a correlationlength (CL = K), and a root mean square value (RMS = D). The sim-ulation method is based on the inverse discrete transformation andthe application of a Gaussian filter over a list of random phases.The correlation length will be accounted for by the width of theGaussian filter, and the amplitude will set the root mean square(RMS) value. To model the Fourier spectra, we use the followingautocorrelation function:

SGðkÞ ¼ffiffiffiffi

pp

D2Keð�k2K2=4Þ;

The simulations of variability for the 22 nm and the 10 nm gatelength NW FETs are carried out using the 3D density gradient(DG) quantum corrected FE DD with a LER correlation length (CL)

0.6 0.7 0.8

1.5

2

2.5

3

σSS

[mV

/dec

]

CL=20 nm , VD,low

CL=20 nm , VD,high

CL=10 nm , VD,low

CL=10 nm , VD,high

0.6 0.7 0.8

RMS [nm]

1

1.5

2

2.5

3

CL=20 nm , VD,low

CL=20 nm , VD,high

CL=10 nm , VD,low

CL=10 nm , VD,high

22nm NW 10nm NW

(b)

0.6 0.7 0.8

5

10

15

20

CL=20 nm CL=10 nm

0.6 0.7 0.8

RMS [nm]

5

10

15

20

σDIB

L [

mV

/V]

CL=20 nm CL=10 nm

22nm NW 10nm NW

(d)

e to LER for the studied 22 nm and 10 nm gate length GAA NW FETs as a function ofnm gate length NW, and VD,low = 0.05 V and VD,high = 0.7 V for the 10 nm gate length

0.2 0.25 0.3 0.35

VT [V]

40

50

60

70

80

90

DIB

L [

mV

/V]

VT,low

VT,high

CC=-0.931

22 nm NW, CL=20 nm, RMS=0.85 nm

CC=-0.977

(a)

0.2 0.25 0.3 0.35

VT [V]

40

50

60

70

80

90

DIB

L [

mV

/V]

VT,low

VT,high

CC=-0.807


CC=-0.938

(b)

0.2 0.25 0.3 0.35

VT [V]

40

50

60

70

80

90

DIB

L [

mV

/V]

VT,low

VT,high

CC=-0.912


CC=-0.972

(c)

0.2 0.25 0.3 0.35

VT [V]

40

50

60

70

80

90

DIB

L [

mV

/V]

VT,low

VT,high

CC=-0.828


CC=-0.944

(d)

Fig. 9. Scatter plots showing the DIBL variation as a function of the VT, at both low and high drain biases, due LER variations (CL = 20=10 nm and RMS = 0:6=0:85 nm) for the22 nm gate GAA NW FET. VD,low = 0.05 V and VD,high = 1.0 V. Correlation coefficients (CC) are also calculated.


of 20 nm and 10 nm and three root mean square values(RMS = 0:6; 0:7 and 0:85 nm) chosen to represent the RMS valuesobserved in experiments [2,3].

After we have calibrated DD-DG simulations to the results from3D FE SEQC MC simulations, we analyse the LER-induced variabil-ity affecting the sub-threshold region of the device comparing fourfigures of merit: threshold voltage (VT), OFF-current (IOFF), sub-threshold slope (SS), drain-induced-barrier-lowering (DIBL).Ensembles of 300 devices have been used to investigate the LER-induced variability in the sub-threshold regions. We extract thethreshold voltage using the fixed current approach and the OFF-current is extracted at VG = 0 V. Fig. 8 shows a comparison of theVT, SS, log10(IOFF) and DIBL variability due to the LER for the stud-ied 22 nm and 10 nm gate length GAA NWs as a function of thedrain bias, the correlation length, and the RMS height. In the pres-ence of LER, the observed variations for the four figures of merit aresmaller in the 22 nm gate length GAA NW at low and high drainbiases than the ones observed in the 10 nm gate length GAA NW.As expected, the standard deviations for the four figures of meritare increasing with the increase of the RMS value. Note here thatthe standard deviations for the four figures of merit are stronglyaffected by the drain bias and the correlation length values in bothNWs. The standard deviations for the four figures of merit areincreasing with the increase of the correlation length value, andalso with the increase on the drain bias.

Fig. 9 shows the DIBL variability as a function of VT at low andhigh drain biases due to LER with CL = (20 and 10 nm) andRMS = (0:6 and 0:85 nm) for the 22 nm gate length NW. In all cases,the DIBL shows strong negative correlations with VT,low (correlation

coefficient (CC) ranges from �0:807 to �0:931) and shows evenstronger correlations with VT,high (CC ranges from �0:938 to�0:977). The larger the CC value, the less sensitive the variabilityis to a change in the drain bias. The Q-Q plot (not shown here) indi-cates near-to-Gaussian behaviour especially at a high drain bias.

Fig. 10 shows the DIBL variability as a function of VT at low andhigh drain biases due to LER with CL = (20 and 10 nm) and RMS =(0:6 and 0:85 nm) for the 10 nm gate length NW FETs. In all cases,the DIBL shows larger strong negative correlations with VT,high (CCranges from �0:969 to �0:988) than with VT,low (CC ranges from�0:945 to �0:979). We can see that, for the 10 nm gate lengthNW, the CC values are larger than those for the 22 nm gate lengthNW. The Q-Q plot indicate more Gaussian behaviour as expected ina larger device but the DIBL for some specific 10 nm gate lengthdevices can overtake the DIBL in the 22 nm one.

Fig. 11 shows the scatter plots of the threshold voltages at ahigh drain bias (VT,high) against the threshold voltages at a low drainbias (VT,low) for the 22 nm gate length Si GAA NWwith CL = (20 and10 nm) and RMS = (0:6 and 0:85 nm). The threshold voltage at lowand high drain biases are strongly correlated so we have used thesame ranges for both the horizontal and vertical axis to showclearly the different behaviours. We can see that the thresholdvoltages with CL = 20 nm have a larger CC value that those forthe CL = 10 nm which means the device variability is less sensitiveto the change at the drain bias. In addition, the threshold voltagesat a low drain bias (VT,low = 0.05 V) is more spread in the case ofCL = 20 nm. Fig. 12 shows the OFF-current (IOFF,high) versus thethreshold voltages (VT,high) at VD = 1.0 V for the 22 nm GAA NWwith CL = (20 and 10 nm) and RMS = (0:6 and 0:85 nm). The log

0.2 0.25 0.3 0.35 0.4 0.45

VT [V]

40

50

60

70

80

90

100

110

DIB

L [

mV

/V]

VT,low

VT,high

CC=-0.974


CC=-0.984

(a)

0.2 0.25 0.3 0.35 0.4 0.45V

T [V]

40

50

60

70

80

90

100

110

DIB

L [

mV

/V]

VT,low

VT,high

CC=-0.945


CC=-0.969

(b)

0.2 0.25 0.3 0.35 0.4 0.45

VT [V]

40

50

60

70

80

90

100

110

DIB

L [

mV

/V]

VT,low

VT,high

CC=-0.979


CC=-0.988

(c)

0.2 0.25 0.3 0.35 0.4 0.45

VT [V]

40

50

60

70

80

90

100

110

DIB

L [

mV

/V]

VT,low

VT,high

CC=-0.951


CC=-0.973

(d)

Fig. 10. Scatter plots showing the DIBL variation as a function of the VT, at both low and high drain biases, due LER variations (CL = 20=10 nm and RMS = 0:6=0:85 nm) for the10 nm GAA NW. VD,low = 0.05 V and VD,high = 0.7 V. Correlation coefficients (CC) are indicated as well.

0.28 0.29 0.3 0.31 0.32 0.33V

T,low [V]

0.2

0.22

0.24

0.26

0.28

VT

,hig

h [V

]

22nm NW

CL=20 nm, RMS=0.85 nm

CC=0.979

(a)

0.28 0.29 0.3 0.31 0.32 0.33V

T,low [V]

0.2

0.22

0.24

0.26

0.28

VT

,hig

h [V

]

22nm NW

CL=10 m, RMS=0.85 nm

CC=0.961

(b)

0.28 0.29 0.3 0.31 0.32 0.33V

T,low [V]

0.2

0.22

0.24

0.26

0.28

VT

,hig

h [V

]

22nm NW


CC=0.982

(c)

0.28 0.29 0.3 0.31 0.32 0.33V

T,low [V]

0.2

0.22

0.24

0.26

0.28

VT

,hig

h [V

]

22nm NW


CC=0.966

(d)

Fig. 11. Scatter plot showing the distribution of the threshold voltages at high drain bias (VT,high) against the threshold voltages at low drain bias (VT,low) for the 22 nm GAANW with LER (CL = 20;10 nm and RMS = 0:6;0:85 nm) with respective correlation coefficients (CC).


0.2 0.22 0.24 0.26 0.28

VT,high

[V]

-15

-14.5

-14

-13.5

-13

log 10

(Iof

f,hi

gh [

A/µ

m]) 22nm NW


CC=-0.9956

(a)

0.2 0.22 0.24 0.26 0.28

VT,high

[V]

-15

-14.5

-14

-13.5

-13

log 10

(Iof

f,hi

gh [

A/µ

m])

22nm NW

CC=-0.984


(b)

0.2 0.22 0.24 0.26 0.28

VT,high

[V]

-15

-14.5

-14

-13.5

-13

log 10

(Iof

f,hi

gh [

A/µ

m]) 22nm NW


CC=-0.9952

(c)

0.2 0.22 0.24 0.26 0.28

VT,high

[V]

-15

-14.5

-14

-13.5

-13

log 10

(Iof

f,hi

gh [

A/µ

m])

22nm NW


CC=-0.988

(d)

Fig. 12. log10(IOFF,high) vs. VT,high at VD = 1.0 V for the 22 nm GAA NW FET with the LER (CL = 20;10 nm and RMS = 0:6;0:85 nm).


of the OFF-current exhibits the typical linear dependence on thedecreasing VT,high suggesting near-to-Gaussian behaviour asexpected. Again, we can see that the variability with CL = 20 nmhave a larger CC value than those for the CL = 10 nm, a characteris-tic of a lower variability in the SS.

4. Conclusion

We have employed our 3D SEQC FE MC simulation toolbox toobtain the ID-VG characteristics of a 22 nm gate length GAA SiNW FET. The simulation toolbox accurately describes the nanoscalegeometry of multi-scale transistors using the FE method, andemploys a completely parameter-free model of carrier transportwhich uses fully anisotropic transport model together with fullyanisotropic quantum corrections which dependent on the valleyorientation (longitudinal and transverse electron effective massesorientation along the device channel). The ID-VG characteristics atlow and high drain biases obtained from the 3D MC toolboxdemonstrated exceptional agreement with the experimental data[2] without any additional post-processing of lumping access resis-tance. We have then scaled the GAA Si NW FET to the 10 nm gatelength and predicted that the scaled device will deliver an on-current of 1320=1100 lA/lm for the h100i/h110i channel withsuperior electrostatic integrity of a nearly ideal sub-thresholdslope of 68 mV/dec and a DIBL of 39 mV/V. Finally, we have studiedthe effects of LER-induced variability on the sub-threshold charac-teristics (VT, IOFF, SS and DIBL) for both the 22 nm and the 10 nmgate length GAA NWs. Our simulations indicate that the 22 nmgate length NW is less sensitive to variability than the 10 nmone. We have found that the LER induced variability of the thresh-old voltage in the 22 nm gate length GAA NW FETs exhibits rVT ofabout 9:5—19:2 mV and rlog10ðIOFFÞ of about 0:16—0:33 A at high

drain bias. The LER induced variability for the 10 nm GAA NW FETsis much larger. The variability of the threshold voltage, rVT , isabout 19:5—42 mV and, the variability of the OFF-current,rlog10ðIOFFÞ, is about 0:35—0:76 A at a high drain bias. The 22 nmgate length GAA NW shows smaller variations for the four figuresof merit at low and high drain biases than the ones observed in the10 nm gate length GAA NW (see Fig. 8) as expected but theincrease in the device variability is relatively small when compar-ing correlation coefficients (CC) [6,7]. This demonstrates that theGAA NW FETs are strong candidates for future generation of digitaltransistors delivering large on-current required in a circuit designaccompanied by a well controlled device variability.

References

[1] Ferain I et al. Multigate transistors as the future of classical metal-oxide-semiconductor field-effect transistors. Nature 2011;479:310–6.

[2] Bangsaruntip S et al. Density scaling with gate-all-around silicon nanowireMOSFETs for the 10 nm node and beyond. IEDM Tech Dig 2013:526–9.

[3] Bangsaruntip S et al. High performance and highly uniform gate-all-aroundsilicon nanowire MOSFETs with wire size dependent scaling. IEDM Tech Dig2009:297–300.

[4] Suk SD et al. Investigation of nanowire size dependency on TSNWFET. IEDMTech Dig 2007:1129–31.

[5] Linton T et al. Determination of the line edge roughness specification for 34 nmdevices. IEDM Tech Dig 2002:303–6.

[6] Seoane N, Indalecio G, Aldegunde M, Nagy D, Elmessary MA, García-LoureiroAJ, et al. Comparison of fin-edge roughness and metal grain work functionvariability in InGaAs and Si FinFETs. IEEE Trans Electron Dev 2016;63(3):1209–16.

[7] Kim SD, Wada H, Woo Jason CS. TCAD-based statistical analysis and modelingof gate line-edge roughness effect on nanoscale MOS transistor performanceand scaling. IEEE Trans Semicond Manuf 2004;17(2):192–200.

[8] Elmessary MA, Nagy D, Aldegunde M, Lindberg J, Dettmer WG, Períc D, et al.Anisotropic quantum corrections for 3-D finite-element Monte Carlosimulations of nanoscale multigate transistors. IEEE Trans Electron Dev2016;63(3):933–9.
























[9] Lindberg J, Aldegunde M, Nagy D, Dettmer WG, Kalna K, García-Loureiro AJ,et al. Quantum corrections based on the 2D Schrödinger equation for 3D finiteelement Monte Carlo simulations of Nanoscaled FinFETs. IEEE Trans ElectronDev 2014;61(2):423–9.

[10] Aldegunde M, García-Loureiro AJ, Kalna K. 3D finite element Monte Carlosimulations of multigate nanoscale transistors. IEEE Trans Electron Dev2013;60(5):1561–7.

[11] Nagy D, Elmessary MA, Aldegunde M, Valin R, Martinez A, Lindberg J, et al. 3Dfinite element Monte Carlo simulations of scaled Si SOI FinFET with differentcross-sections. IEEE Trans Nanotechnol 2015;14(1):93–100.

[12] ITRS(2012). International technology roadmap for semiconductors [Online].Available: <http://www.itrs.net/Links/2012ITRS/Home2012.htm>.

[13] Jacoboni C, Lugli P. The Monte Carlo method for semiconductor devicesimulation. Wien-New York: Springer-Verlag; 1989.

[14] Ridley BK. Reconciliation of the Conwell-Weisskopf and Brooks-Herringformulae for charged-impurity scattering in semiconductors: third-bodyinterference. J Phys C: Solid State Phys 1977;10(10):1589–93.

[15] Islam A, Kalna K. Monte Carlo simulations of mobility in doped GaAs usingself-consistent Fermi-Dirac statistics. Semicond Sci Technol 2011;26(5):055007. 9pp.

[16] Ferry DK. Semiconductor transport. Taylor & Francis; 2000.[17] Garcia-Loureiro AJ et al. Implementation of the density gradient quantum

corrections for 3D simulations of multigate nanoscaled transistors. IEEE TransComput-Aided Des Integr Circ Syst 2011;30(6):841–51.

[18] Islam A, Benbakhti B, Kalna K. Monte Carlo study of ultimate channel scaling inSi and In0.3Ga0.7As bulk MOSFETs. IEEE Trans Nanotechnol 2011;10(6):1424–32.

[19] Ban Yongchan, Sundareswaran Savithri, Pan David Z. Electrical impact of line-edge roughness on sub-45 nm node standard cells. J Microlithogr MicrofabrMicrosyst (JM3) 2010;9(4):041206.

[20] Seoane N et al. Random dopant, line-edge roughness, and gate workfunctionvariability in a nano InGaAs FinFET. IEEE Trans Electron Dev 2014;61(2):466–72.

[21] Asenov A, Kaya S, Brown AR. Intrinsic parameter fluctuations indecananometer MOSFETs introduced by gate line edge roughness. IEEE TransElectron Dev 2003;50(5):1254–9.

[22] Indalecio G, Aldegunde M, Seoane N, Kalna K, García-Loureiro AJ. Statisticalstudy of the influence of LER and MGG in SOI MOSFET. Semicond Sci Technol2014:045005.











http://www.itrs.net/Links/2012ITRS/Home2012.htm



































Variability and self-average of impurity-limited resistance in quasi-onedimensional nanowires


E-mail address: [email protected]

Nobuyuki SanoInstitute of Applied Physics, University of Tsukuba, Tsukuba, Ibaraki 305-8573, Japan




Keywords:NanowireImpurity scatteringVariabilityPhase interferenceSelf-average

a b s t r a c t

The impurity-limited resistance in quasi-one dimensional (quasi-1D) nanowires is studied under theframework of the Lippmann–Schwinger scattering theory. The resistance of cylindrical nanowires is cal-culated theoretically under various spatial configurations of localized impurities with a simplified short-range scattering potential. Then, the relationship between the phase interference and the variability inthe impurity-limited resistances is clarified. We show that there are two different and independentmechanisms leading to the variability in impurity-limited resistances; incoherent and phase-coherentrandomization processes. The latter is closely related to the so-called ‘‘self-average” and its physical ori-gin under nanowire structures is clarified. We point out that the ensemble average also comes into play inthe cases of long channel nanowires, which leads to the self-average resistance of multiple impurities.


1. Introduction

Si nanowires have been receiving great attention in the past fewdecades because of their possible application of future electronicand photonic devices [1,2]. However, because of their small struc-tures in size, the device performance often fluctuates over greatranges, depending on the configuration of localized impurities inthe substrate [3,4]. So far, theoretical studies on such variabilityobserved in mobility or resistance of nanowires are limited withlarge-scale numerical simulations [5–10]. It has been demon-strated that the transport properties indeed fluctuate in shortchannel nanowires. Clearly, the phase interference would be ofcrucial importance in understanding the physics behind thevariability.

It should be noted that the phase interference also plays a dom-inant role in self-averaging the transport properties such as resis-tance in long channel devices, in which many impurities aredistributed uniformly in the substrate. Many different configura-tions of impurities in the substrate allows us to use the space-average impurity scattering rates in calculating the mobility etc,although the precise impurity configuration is different for eachdevice. This is often referred to as ‘‘self-average” and the phaseinterference is deeply involved in its averaging mechanism [11].Despite its importance, however, almost no attention has beenpaid so far on the interference effects among multiple impuritieson transport properties under nanowire structures.

In the present paper, we study the interference effects associ-ated with localized impurities on impurity-limited resistances inthe quasi-1D nanowires. This is carried out based on the theoryemployed recently by the present author [12] and we clarify howand why the phase interference leads to the variability in theimpurity-limited resistance. Then, the physical origin of ‘‘self-average” emerged under the fully coherent circumstances isclarified.

2. Theoretical foundations

2.1. Impurity-limited resistance

We consider a cylindrical nanowire with the radius of rs ¼ 2 nmand the impurity density in the substrate is assumed to be uniform(nimp ¼ 2� 1019 cm�3), i.e., localized impurities are distributed uni-formly in the channel region. The channel length L of the wirechanges in accordance with the number of impurities doped inthe channel region, namely, L ¼ 4 nm for one impurity, 8 nm fortwo impurities, etc. In addition, the extreme quantum limit, inwhich only the lowest subband is involved in electron transport,is assumed in which the phase interference is most effective.

Theoretical expressions of the impurity-limited resistance dueto localized impurities in the nanowires are derived from the Lan-dauer formula under the linear response regime. The conductance Gof the doped channel region is calculated from the transmissioncoefficient TAðEÞ of the in-coming electrons in the lowest subbandA with total energy E from the reservoirs (source and drain):







Fig. 1. Schematic drawings of the nanowire with two impurities doped in thechannel and the corresponding potential profile under the applied gate voltage. Thedoped impurities are assumed to be donors so that the interaction is attractive.Under the framework of the scattering theory, the whole potential modulation istreated as a single scattering potential. The whole scattering potential consists ofthe long- and short-range potential modulation and the impurity-limited resistanceresults from the short-range screened scattering potential.

26 N. Sano / Solid-State Electronics 128 (2017) 25–30

G ¼ e2

p�h

Z 1

�1dETAðEÞ � @f FD Eð Þ

@E

� �

; ð1Þ

where f FDðEÞ is the Fermi–Dirac distribution in the reservoirs.It should be noted that the total resistance Rtot given by the

inverse of G is comprised of two contributions; the contact resis-tance and the channel resistance [12]. The former results fromthe difference in the number of modes between the lead and thereservoirs, whereas the latter is due to the scattering potential byionized impurities, phonons, surface roughness, and the long-range potential modulation. This long-range potential modulationis, furthermore, separated into the long-range part of the scatteringCoulomb potential of ionized impurities/carriers and the electro-static potential induced by the applied gate voltage,1 as schemati-cally drawn in Fig. 1. It should be noted that, in general, this long-range potential modulation is nearly irrelevant to the channel resis-tance and simply attributed to the carrier density modulation in thechannel [12]. As the channel length shrinks, direct tunneling fromthe source to the channel and/or the drain regions comes into playand, then, the finite resistance due to the long-range potential mod-ulation shows up.

In the present study, the separation between the long- andshort-range parts of the scattering potential is always possiblesince the short-range part is defined as the singular part of thescattering potential and approximated by the delta-functionpotential. The rest of the potential should be regarded as thelong-range part and attribute to the potential modulation throughthe Poisson equation, rather than the scattering potential. How-ever, such separation for the realistic Coulomb potential might looknontrivial under nanostructures as the spatial distance betweenthe impurities could be so small. This is, however, equivalent toasking whether or not the higher-order corrections associated withthe interaction strength of impurity scattering is significant. In thiscase, the multiple impurities should be treated as a coherent singlescattering center and the separation of the long- and short-rangeparts is made possible via Fourier transform of the potential.

In order to extract the impurity-limited resistance from thetotal resistance, we intentionally eliminate phonon scatteringand consider only impurity scattering throughout this study.

1 The work-function difference between the substrate and the gate also contributesto this long-range potential modulation.

Furthermore, the resistance caused by the long-range potentialmodulation mentioned above is ignored by assuming that thechannel potential is flat along the wire axis. This could be achievedby properly imposing the gate voltage. This also implies that weignore the direct tunneling from the source to the channel and/orthe drain regions. As a consequence, the impurity-limited resis-tance is obtained by simply subtracting the contact (quantum)resistance from the total resistance, Rs ¼ Rtot � R0, and, thus, givenby

Rs ¼ p�he2

RAðEÞh i1� RAðEÞh i ¼ R0 RAðEÞh i þ RAðEÞh ið Þ2 þ � � �

n o

ð2Þ

with

RAðEÞh i ¼Z 1

�1dERAðEÞ � @f FD Eð Þ

@E

� �

: ð3Þ

Here, the contact (quantum) resistance is given by R0 ¼ p�h=e2 andRAðEÞ (¼ 1� TAðEÞ) is the reflection coefficient of the in-comingelectrons with total energy E in the lowest subband A. We alsoassume that the chemical potential in the reservoirs is well abovethe bottom of the lowest subband in the channel. If Rs is truncatedby the first term in the last expression of Eq. (2), the resultingexpression corresponds to the usual Born approximation providedthat the reflection probability RAðEÞh i is also approximated by thelowest order with respect to the interaction strength.

2.2. Transmission and reflection coefficients

The transmission and the reflection coefficients, TAðEÞ and RAðEÞ,are calculated from the asymptotic forms of the scattered wavefunction by solving the Lippmann–Schwinger (LS) equation givenby

wþðEÞ�

�

� ¼ /ðEÞj i þ Gþ0 Eð ÞV wþðEÞ�

�

�

; ð4Þwhere wþðEÞ�

�

�

is the scattered state vector with total energy

E; /ðEÞj i is the unperturbed state vector, V is the scattering potential

operator, and Gþ0 Eð Þ is the unperturbed (retarded) Green operator

[12–15]. The unperturbed state vector /ðEÞj i is the eigenstate of

the unperturbed Hamiltonian bH0, which is expressed by

bH0 ¼ � �h2

2mr2 þ UcylðRÞ ð5Þ

under the effective mass approximation for the cylindrical wire.Here, m is the electron effective mass and UcylðRÞ is the single-particle potential energy which confines the electrons inside thecylindrical wire. Assuming that the electrons are confined by theinfinite potential barrier, the unperturbed eigenfunction in the low-est subband A is simply given by

/A Rð Þ ¼ 1ffiffiffi

Lp eikznA rð Þ ¼ 1

ffiffiffi

Lp eikz

1ffiffiffiffi

pp

rsJ1 x01ð Þ J0 x01rrs

� �

; ð6Þ

where R ¼ r; zð Þ ¼ r;u; zð Þ in the cylindrical coordinates, L is thewire (channel) length, nA rð Þ is the subband wavefunction, J0ðxÞ isthe 0-th order Bessel function, and x01 is the first root of J0ðxÞ ¼ 0.The total electron energy E in the lowest subband is then givenby

E ¼ ek þ e01 ¼ �h2k2

2mþ �h2

2mx01rs

� �2

: ð7Þ

As for the scattering potential due to localized impurities, weemploy the short-range d-function potential defined by

V Rð Þ ¼X

Nimp

r¼1

vcaSð Þdð3Þ R � R0rð Þ; ð8Þ

Fig. 2. Impurity-limited resistances of two impurities for 1000 different configu-rations as a function of the impurity separation D along the wire axis for (a)T ¼ 300 K and (b) 30 K. The solid symbols in (a) represent the results from the NEGFsimulations for acceptor impurities. The horizontal dashed lines show 2Rsingle

s , withRsingles being the single-impurity resistance averaged over the impurity

configurations.

N. Sano / Solid-State Electronics 128 (2017) 25–30 27

where Nimp is the number of impurities in the channel, vc is the scat-tering potential energy, a (¼ 0:5 nm) is the characteristic lengthalong the axis direction over which the scattering potential is effec-tive, and S (¼ pr2s ) is the cross-sectional area of the wire.R0r ¼ r0r; z0rð Þ is the position of the r-th impurity(r ¼ 1;2; . . . ;Nimp). As already discussed in our previous paper[12], the expression employed here for the impurity scatteringpotential oversimplifies the reality: The present model representsonly the singular part of the Coulomb potential due to ionizedimpurities and corresponds to the cases of extremely strong screen-ing. Since the long-range part of the potential always smoothens thefluctuations in the transport characteristics, the present scatteringpotential somewhat exaggerates the phase interference effectsamong the localized impurities. Nevertheless, as we shall show inFig. 2, in which the present analyses are compared with more elab-orate NEGF simulations, the present model does represent properlythe essential features associated with the phase interference amongmultiple localized impurities.

Thanks to the simple form of the impurity scattering potential,the exact transmission and reflection coefficients could be analyt-ically derived from the LS equation and given, respectively, by

TAðEÞ ¼ 1þ I�ðEÞj j2 ð9Þand

RAðEÞ ¼ IþðEÞ�

�

�

�

2; ð10Þ

where I�ðEÞ is expressed as

I�ðEÞ¼ e�ikz01 e�ikz02 � � � e�ikz0Nimp

� �

�iCðEÞ� � 1

1þ iRðEÞ

!

eikz01

eikz02

..

.

eikz0Nimp

0

B

B

B

B

@

1

C

C

C

C

A

ð11Þby employing the matrix representation with respect to impurity

site indices. The matrix elements of CðEÞ and RðEÞ are then definedby

ðCðEÞÞrs ¼ma

�h2kvcS nA r0rð Þj j2 � crðEÞdr;s ð12Þ

and

ðRðEÞÞrs ¼ eik z0r�z0sj jcsðEÞ ¼ eikDrscsðEÞ; ð13Þwhere Drs ¼ z0r � z0sj j and nA r0rð Þ is the subband wavefunction of ther-th impurity site. It should be noted that crðEÞ is a dimensionlessreal number and represents the strength of the coupling betweenelectron and impurity.

As a concrete example, the exact expression of the reflectioncoefficient RAðEÞ of two localized impurities is given by

RA Eð Þ ¼ KðEÞ1þKðEÞ ð14Þ

with

KðEÞ ¼ c21 þ c22 þ 2c21c22

þ 2c1c2 1� c1c2ð Þ cos 2kDð Þ þ c1 þ c2ð Þ sin 2kDð Þf g; ð15Þ

where D ¼ D12 ¼ z01 � z02j j and D is the separation between the twoimpurities along the wire axis direction. Notice that Eq. (14) isbounded above and its supremum is unity, as it should be.

3. Results and discussion

3.1. Variability and phase interference

We first show the impurity-limited resistance Rs of two local-ized impurities for 1000 different configurations inside the channelas a function of the impurity separation D for T ¼ 300 and 30 K inFig. 2. The scattering potential energy is set at vc ¼ 183 meV, cor-responding to the screening length of ksc ¼ 2 nm [12]. For compar-ison, similar results frommore elaborate NEGF simulations [16] arealso shown with solid symbols in Fig. 2(a).

In the NEGF simulations, we have carried out the simulationsfor more than 500 different impurity configurations. Since it isnot possible to carry out the simulations coupled self-consistently with the Poisson equation so many times, the impu-rity scattering potential has been approximated with the Yukawapotential with the image charges associated with the interfacewith the gate. This approximation is not crucial because our mainconcern is to find out how the difference in shape of the scatteringpotential, namely a finite extension of the scattering potential inreal space, affects the variability associated with the phase inter-ference. In addition, the device structure employed in the NEGFsimulations is a square nanowire with the side length of 3.5 nm.The difference in shape is again insignificant because the cross-sectional area is very similar in both cases.

The fluctuations associated with the subband wavefunction(and the screened Coulomb potential) are greatly suppressed, com-pared with the case of the short-range scattering potential in the LSapproach, due to the long-range nature of the scattering potential.However, the variations of Rs along the wire axis direction are verysimilar to those calculated from the LS equation: Rs is large at small

Fig. 3. Impurity-limited resistance of two impurities from the LS equation atT ¼ 30;100;300 K as a function of the impurity separation D. Both impurities arelocated on the wire axis.The horizontal dotted line shows the uncorrelated value2Rsingle , with Rsingle being the single-impurity resistance located on the wire axis.

Fig. 4. Impurity-limited resistance of (a) three and (b) four impurities at T ¼ 300 Kas a function of the maximum separation among impurities Dmax , as shown in (c),where the locations of impurities are schematically drawn. All impurities arelocated on the wire axis. The horizontal dotted lines show the uncorrelated values,3Rsingle and 4Rsingle , with Rsingle being the single-impurity resistance located on thewire axis.


D, whereas Rs approaches to some constant value and, thus, thevariation along the wire axis direction vanishes at large D.

In either case of the LS or NEGF, the value of the resistances Rs

scatters over a few orders of magnitudes and such large fluctua-tions result in the two different physical origins: The fluctuationsin Rs at fixed D are attributed to the variations in cr (the subbandwavefunctions), whereas the fluctuations along the wire axis direc-tion D are due to the trigonometric function dependence in Eq. (15)and, thus, due to the phase interference of electrons among theimpurities. Therefore, the former has nothing to do with the phasecorrelation among multiple impurities2; each impurity could beregarded as nearly independent. Since the central-limit theoremcould be applied in this case [17], the fluctuations with respect tothe vertical direction in Fig. 2 would diminish under some particularimpurity configuration as the channel length becomes longer.

On the other hand, the variations in Rs along the D direction donot generally vanish even for long channel wires, as noted by Kohnand Luttinger [11]. In order to demonstrate this point, we eliminatethe fluctuations associated with the subband wavefunctions; wecarry out similar calculations by placing two impurities on the wireaxis for three different temperatures, T ¼ 30, 100, and 300 K. Thecalculation results are shown in Fig. 3 along with the uncorrelatedvalue 2Rsingle for T ¼ 300 K, where Rsingle is the resistance of thesingle-impurity located on the wire axis. We would like to mentionthat the Born approximation completely breaks down and the cou-pling between the electron and impurity is enhanced due to theconfinement in nanostructures [12]. A large oscillatory behaviorin Rs is observed in the first few nm at any temperature. This oscil-lation results from the trigonometric function dependence in thereflection coefficient RAðEÞ in Eq. (15) and represents the construc-tive phase interference among the two impurities. This interfer-ence effect becomes very strong at low temperature and wouldlead to the Anderson localization if the coupling between the elec-tron and impurity is strong enough. However, at room temperature,this oscillation rapidly damps and Rs approaches 2Rsingle, that is, theuncorrelated limit.

2 There exists a slight phase dependence due to the trigonometric functioninvolved in RAðEÞ of Eq. (15), though D is fixed.

The above findings also hold true for the cases of more than twoimpurities doped in the channel. Similar calculations of theimpurity-limited resistance Rs are carried out by placing three orfour impurities on the wire axis. The exact formulas of the reflec-tion coefficients RAðEÞ are analytically derived from the LS equa-tion. The calculation results for T ¼ 300 K are shown in Fig. 4 asa function of the maximum separation among the impuritiesDmax. The locations of the impurities in between are assumed suchthat the ratios like D1=Dmax and D2=Dmax are fixed, where D1 and D2

are the locations of the impurities as drawn in Fig. 4(c). The nor-malized values of Rs of three different impurity configurationsare shown for each case. The uncorrelated values are given by3Rsingle and 4Rsingle, and indicated with the horizontal dotted lines.Here, Rsingle is the single-impurity resistance located on the wireaxis as before. Again, the variations in Rs along the wire axis direc-tion are large at small Dmax, whereas Rs nearly stays constant asDmax becomes large.

These results that Rs at large impurity separation approachesthe uncorrelated value are rather surprising because no averaging

N. Sano / Solid-State Electronics 128 (2017) 25–30 29

over the configurations of impurities nor energy dissipating scat-tering which randomizes the electron phase is included in theabove analyses. In other word, the phase randomization is takingplace even under the fully coherent circumstances under some partic-ular impurity configuration. This is attributed to the self-average, aswe shall discuss below.

Fig. 5. Ensemble average resistance of two impurities under uniform impuritydistributions as a function of temperature of the reservoirs for three differentscattering potential energies, vc ¼ 50, 100, 200 meV. 2Rsingle represents theuncorrelated limit, where Rsingle is the ensemble average resistance of the single-impurity under uniform impurity configurations.

3.2. Origin of self-average

The fact that the impurity-limited resistance of multiple impu-rities approaches the uncorrelated values at room temperatureimplies that the phase correlation among the impurities is some-how washed out as the impurity separation along the wire axisbecomes large, namely, larger than some phase correlation lengthDphase.

We find that the physical origin of this phase randomizationalong the wire axis direction is closely related to the broadnessof the energy spectrum of in-coming electrons from the reservoirs(source and drain). That is, Rs is averaged by the in-coming elec-trons with many different kinetic energies (wavelengths) whenthe spectrum is broad (or equivalently, temperature of the reser-voirs is high). Therefore, if the temperature is low enough such thatthe energy spectrum of the in-coming electrons is limited to be avery narrow range around the Fermi energy of the reservoirs, thephase coherence would last much longer distances and Rs deviatesfrom the uncorrelated value even at large impurity separation. Thisis indeed confirmed from Fig. 3, in which the oscillation in Rs atT ¼ 30 K is sustained over the entire channel region.

Notice that this is also consistent with the arguments given byKohn and Luttinger [11] for ‘‘self-average.” They claim that someaveraging procedure, in addition to averaging over the impurityconfigurations, is necessary to lead to self-average the transportproperties under coherent circumstances. In their cases, the den-sity of states for the final states after impurity scattering plays thatrole because their consideration is restricted to the electron gas inbulk. In the present case, the final states after scattering are ratherlimited in quasi-1D nanowires and it is not strong enough to leadto self-averaging. Instead, the broadness of the energy spectrumof the in-coming electrons from the reservoirs is attributed toanother averaging process.

However, as is clear from Fig. 4, the values of Rs at large Dmax forthe cases of three and four impurities scatter to some extentaround the uncorrelated values, contrary to the case of two impu-rities. This results from the fact that the transmission probabilityTAðEÞ is very close to zero at such large impurity separation(Dmax P 10 nm) and electrons hardly go through the channelregion. As a result, Rs is greatly affected by a tiny fluctuation inTAðEÞ and scatter around the uncorrelated value. We should noticethat at room temperature, phonon scattering is always inevitableeven in nano-scale channels [18,19]. Since its mean-free-path isaround 10 nm, the phase coherence is almost always destroyedat such large impurity separation. Then, the ensemble-averageover various impurity configurations comes into play in the casesof long channel nanowires. In other words, thanks to the energydissipating scattering, the variations shown at large Dmax in Fig. 4would vanish due to averaging over various impurity configura-tions as the channel length increases. This is indeed true as weshall show below.

Fig. 6. Ensemble average resistances of three and four impurities at T ¼ 300 K as afunction of the maximum impurity separation Dmax . Impurities in between areplaced on the wire axis at random by fixing the maximum separation Dmax amongimpurities. Rsingle represents the resistance of the single-impurity placed on the wireaxis.

3.3. Self-average versus ensemble average

Here, we would like to stress the difference between the self-average and the ensemble average of transport properties. The for-mer averaging is taking place in a single nanowire under somefixed impurity configuration, whereas in the case of ensemble

average the average is taken literally over various impurityconfigurations.

In the present case, the phase correlation length Dphase wherethe constructive phase interference is significant is about 5 nm atroom temperature, as seen in Figs. 3 and 4, and Dphase is much smal-ler than the channel length L (�8–16 nm). Therefore, the phase cor-relation volume inside the nanowire is a fraction of the entirevolume of the channel region. If one takes an ensemble averageof the resistances over many nanowires where impuritiesare assumed to be distributed uniform, the ensemble averageresistance becomes very close to the value of the uncorrelatedresistance unless the scattering potential energy vc is extremelylarge. That is, the ensemble average resistance would be a simplesum of �Rsingle, where �Rsingle is the ensemble average resistance ofthe single-impurity under the uniform impurity configurations.This is confirmed from Fig. 5, in which the ensemble averageresistance of two impurities under various uniform impurity


distributions is plotted as a function of temperature of the reser-voirs for three different scattering potential energies, vc ¼ 50,100, 200 meV. The uncorrelated average resistance, 2�Rsingle, is alsoshown. The deviation between the two results, the exact and theuncorrelated ones, is large when the coupling strength vc is large.However, as temperature increases, the deviation decreases evenfor vc ¼ 200 meV, which is close to the reality.

A similar scenario holds true even for the cases of three and fourimpurities: Fig. 6 shows the ensemble average resistance Rs ofthree or four impurities placed on the wire axis as a function ofthe maximum impurity separation Dmax. The locations of the impu-rities in between are chosen at random with the fixed Dmax. Sinceall impurities are placed on the wire axis, the average values ofRs are somewhat exaggerated. Nevertheless, the large variationsat large Dmax observed in Fig. 4 are greatly suppressed in both casesand the ensemble average resistance at room temperaturebecomes close to the uncorrelated value (within a factor of threeor so). Hence, the classical Ohm’s law is recovered. This is also con-sistent with our finding from more elaborate NEGF simulations, inwhich the ensemble average resistance is indeed proportional tothe number of impurities [16].

4. Conclusions

We have investigated the variability in the impurity-limitedresistance due to localized impurities in quasi-1D nanowires fromthe viewpoint of the phase interference. We have clarified thephysical origin of the ‘‘self-average” of resistances under quasi-1D nanowire structures: Averaging is dominantly taking placethrough the broadness of the energy spectrum of in-coming elec-trons from the reservoirs. However, another averaging process isalso required to achieve the ‘‘self-average” of the resistance underlong-channel nanowire structures, namely, the ensemble averageover impurity configurations. Since the energy-dissipating phononscattering is always involved at room temperature, it breaks thephase coherence among the multiple impurities at large impurityseparations (around 10 nm or more). Then, in addition to the aver-aging over the in-coming electrons with broad energy spectrum,the ensemble average also comes into play to self-average theresistance of multiple impurities in long channel nanowires.Thanks to this energy-dissipating scattering, the variations of Rs

found at large impurity separation under fully coherent circum-stances diminish. Then, the entire resistance becomes self-averaged and close to the uncorrelated value, namely, the seriesresistance of the single-impurity resistances. Hence, the classicalOhm’s law is recovered.

Acknowledgment

This work was supported in part by Ministry of Education,Science, Sports, and Culture under Grant-in- Aid for ScientificResearch (B) (No. 15H03983).

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Drain current local variability from linear to saturation region in 28 nmbulk NMOSFETs


⇑ Corresponding author at: Polygone scientifique MINATEC, 3 Parvis Louis Néel,CS 50257, 38016 Grenoble Cedex 1 (Office 350), France.

E-mail address: [email protected] (T.A. Karatsori).

T.A. Karatsori a,b,⇑, C.G. Theodorou a, S. Haendler c, C.A. Dimitriadis b, G. Ghibaudo a

a IMEP-LAHC, INPG – Minatec, 3 Parvis Louis Néel, CS 50257, 38016 Grenoble, FrancebDepartment of Physics, Aristotle University of Thessaloniki, Thessaloniki 54124, Greecec STMicroelectronics, BP16, 38921 Crolles, France




Keywords:MismatchLocal variabilityThreshold voltageGain factorSource-drain series resistanceModeling28 nm bulkCMOS

In this work, we investigate the impact of the source - drain series resistance mismatch on the drain cur-rent variability in 28 nm bulk MOSFETs. For the first time, a mismatch model including the local fluctu-ations of the threshold voltage (Vt), the drain current gain factor (b) and the source – drain seriesresistance (RSD) in both linear and saturation regions is presented. Furthermore, it is demonstrated thatthe influence of the source – drain series resistance mismatch is attenuated in the saturation region, dueto the weaker sensitivity of the drain current variability on the series resistance variation. The experi-mental results were further verified by numerical simulations of the drain current characteristics withsensitivity analysis of the MOSFET parameters Vt, b and RSD.


1. Introduction

Usually, process variations within CMOS technologies are cate-gorized into global and local variations. Concerning the global vari-ations, the device parameters change smoothly all over the wafer.On the other hand, for local variability or mismatch, each MOStransistor is affected differently even from its close neighbor. Mis-match is by nature an uncorrelated stochastic process, which isincreasing due to the scaling down of CMOS technology. As a result,a crucial issue in MOSFETs and especially in advanced nano-scaleddevices is the study of drain current local variability, as it affectsthe performance of analog but also digital circuits like SRAM cells.

According to the first mismatch studies, the main sources of thedrain current, ID mismatch are related to the local fluctuations ofthe threshold voltage, Vt and the current gain factor, b [1,2]. Thesource – drain (SD) series resistance mismatch and its impact onthe drain current variability of FDSOI devices has been reportedin recent works [3–5].

In this work, we study the SD series resistance mismatch on thedrain current variability in bulk NMOS transistors processed with

28 nm Gate-first technology and extend for the first time the draincurrent local variability model in the saturation region as well.

2. Devices and experimental details

The devices measured in this work are bulk n-MOS transistors,issued from 28 nm planar CMOS technology with channel width(W) varying from 10 down to 0.08 lm and channel length (L) vary-ing from 5 down to 0.03 lm. The devices were fabricated by STMicroelectronics in France and present also pocket implants. Asample of 70 pairs of identical MOS transistors (namely, MOS1and MOS2), electrically independent with symmetric connections,spaced by the minimum allowed distance and laid out in an iden-tical environment, was necessary for matching measurements.Drain current measurements in both linear (VD ¼ 30 mV) and sat-uration regions (VD ¼ 1 V) were performed with Agilent B1500Semiconductor Device Analyzer. Fig. 1(a)–(d) present typicalID-VG characteristics in both linear and saturation regions, illustrat-ing the single device variability over full wafer for the nominaldevice.

As in nominal dimension devices, the drain current differencebetween two paired transistors might reach several decades, thedrain current mismatch, DId/Id, is no longer evaluated with a lineardifference but using the log difference as [4],







Fig. 1. Experimental ID(VG) variability characteristics and their mean value in linear(a and c) and logarithmic scale (b and d) at low (a and b) and high (c and d) drainvoltage of an ensemble of 70 bulk n-MOSFETs with channel width W = 0.08 lm andchannel length L = 0.03 lm.

Fig. 2. Typical DId/Id(VG) (a) and DY/Y(VG) (b) curves in linear region for n-MOS

32 T.A. Karatsori et al. / Solid-State Electronics 128 (2017) 31–36

DID=ID ¼ ln ID2=ID1ð Þ; ð1Þwhere ID1 and ID2 refer to the drain current of MOS1 and MOS2 pair.

3. Drain current mismatch modeling

In order to build a general drain current mismatch model, wehave to take into account all the main sources of drain current localvariability through the sensitivity of the drain current to the MOS-FET parameters, i.e. Vt, b and RSD. Therefore, considering the firstorder Taylor approximation, the drain current variation can beexpressed as the sum of the principal contributions as [3],

dIDID

¼ 1ID

� @ID@Vt

� �

� dVt þ 1ID

� @ID@b

� �

� dbþ 1ID

� @ID@RSD

� �

� dRSD ð2Þ

After calculating the partial derivatives of ID with respect to Vt, band RSD, the expression describing the drain current mismatch inthe linear region is obtained as [3],

r2ðDID=IDÞ ¼ gm

ID

� �2

� r2ðDVtÞ þ ð1� GD � RSDÞ2 � r2 Dbb

� �

þ G2D � r2ðDRSDÞ ð3Þ

where r(DVt) r(Db/b) and r(DRSD) are the standard deviations ofthe threshold voltage, the gain factor b ¼ W � Cox � l0 � VD=L andthe SD series resistance mismatch respectively, gm is the transcon-ductance and GD is the channel conductance in the linear region.

Furthermore, a useful approach concerning the mismatch studyin linear operation is based on the Y-Function defined asY ¼ ID=

ffiffiffiffiffiffi

gmp

, which is independent of RSD. Indeed, a Y-Functionbased methodology has been proposed in order to extract directlythe Vt and b local variations, using the mismatch of the Y-Function[3]. According to [4], the Y-Function mismatch can be modeledfrom weak to strong inversion by,

r2ðDY=YÞ ¼ b � r2ðDVtÞ4 � b � n2 � ðk � T=qÞ2 þ Y2

!

þ 14� r2 Db

b

� �

ð4Þ

The limitation of all above equations is that they are only validin the linear operation regime. In the present work, we extendedthe drain current local variability model described in [4] in orderto include the saturation region in the calculation of the drain cur-rent mismatch. Using again the sensitivity analysis as in Eq. (2) andmaking the assumption that RS ¼ RD ¼ RSD=2, we can calculate thepartial derivative of ID with respect to RSD as,

1ID

@ID@RSD

¼ gm=2þ gd ð5Þ

where gd is the output conductance.As a result, combining Eqs. (2) and (5), it is easy to show that the

drain current local variability from weak to strong inversion inboth linear and saturation regions can be described by,

r2 DIDID

� �

¼ gm

ID

� �2

� r2ðDVtÞ þ ðð1� ðgm=2þ gdÞ � RSDÞ2Þ

� r2 Dbb

� �

þ ðgm=2þ gdÞ2 � r2ðDRSDÞ ð6Þ

Note that, as compared to Eq. (3) which is valid in the linearregion, Eq. (6) is generalized by including also the saturation regionas manifested by the transconductance contribution that maydominate the output conductance term for large drain voltage.


4.1. Experimental results

Fig. 2(a) presents the drain current local variability of n-MOSpaired transistors of the nominal geometry, measured in the linearregion. Note that the drain current deviation below threshold volt-age exceeds 2 decades, making essential the use of the logarithm inEq. (1). The respective Y-parameter mismatch presented in Fig. 2(b) shows a similar trend.

Moreover, the drain current mismatch at high drain voltage isillustrated in Fig. 2(c) and (d) for a small and a large area device,respectively. As expected, according to Pelgrom’s Law, the draincurrent mismatch is significantly lower in large area devices.

devices with W = 0.08 lm and L = 0.03 lm. The corresponding DId/Id(VG) charac-teristics at saturation region for a small (c) but also for a large area device (d).

T.A. Karatsori et al. / Solid-State Electronics 128 (2017) 31–36 33

In Fig. 3(a) and (b), the normalized standard deviation of thedrain current mismatch, r(DID/ID), is plotted as a function of thegate voltage, VG for various geometries in the linear and saturationregions, respectively. Note that, at low drain voltage, there areclearly cases at strong inversion where an increase of r(DID/ID)with VG is observed. This increase, which is not observed in allgeometries, was attributed to SD series resistance variability inFDSOI devices [4]. Therefore, it appears that this phenomenon alsoexists in bulk devices. On the other hand, we observe that, for thesame geometries, no such behavior is clearly observed in the satu-ration region (see Fig. 3(b)).

In order to verify our model, we used Eq. (6) to fit the experi-mental data with 3 fitting parameters, the threshold voltage mis-match, r(DVt), the current gain factor mismatch, r(Db/b) and theRSD mismatch, r(DRSD), in all operation regions. The value of RSD

was extracted with the Y-Function method using several gatelengths [6]. The results are displayed in Fig. 4(a) and (b). Concern-ing the saturation region, we extracted values for r(DVt), r(Db/b)and r(DRSD), which are consistent with those extracted in the lin-ear region. As it is shown in Fig. 4(b), we achieved good agreementbetween experimental and model results. This indicates that theinfluence of DRSD can be significantly attenuated in the saturationregion. This feature can be understood through the last term of Eq.(6) which relates the drain current sensitivity withDRSD, indicatingthat ID is at least twice less sensitive to RSD in the saturation region,where gd is almost equal to 0 (see Fig. 5). This observation is con-firmed in Fig. 6(a) and (b), where the individual matching parame-ter iADVgðVGÞ (Eq. (7)) is presented for various geometries in thelinear and saturation regions, respectively.

iADVg ¼ r DIDID

� ��

gm

ID

� ��

�ffiffiffiffiffiffiffiffiffiffiffi

W � Lp

ð7Þ

The plateau observed in Fig. 6 at low gate voltages nearly corre-sponds to the individual matching parameter iADVt (Eq. (8)). Notethat the abnormal behavior of iADVgðVGÞ observed at low gate volt-ages in long channel devices is due to the fact that the devices arepocket implanted [7].

iADVt ¼ rðDVtÞ �ffiffiffiffiffiffiffiffiffiffiffi

W � Lp

ð8ÞAs we can see in more detail in Fig. 7, r(DVt) has almost the

same value for both linear and saturation regions. The differenceobserved between the two regions at high VG values is due to ther(DRSD) difference, while the slight increase of iADVg in stronginversion is due to r(Db/b). From Fig. 7, it is also clear that the

Fig. 3. Normalized standard deviation of the drain current mismatch versus gate

parameter iADVg is smaller at VD ¼ 1V , since the impact of DRSD

on the drain current variability is less in the saturation region(Eq. (6)).

Figs. 8 and 9 present the individual matching parameters iADVt

and iADb=b, respectively, as a function of the gate length (Eqs. (8)and (9)).

iADb=b ¼ rðDb=bÞ �ffiffiffiffiffiffiffiffiffiffiffi

W � Lp

ð9ÞThe values corresponding to the iADVt parameter are ranging

between 2 and 6.5 mV�lm, in agreement with [8], increasingslightly with the gate length. Moreover, iADb=b ranges from 0.4 to0.6%�lm, verifying that our fitting with including the gain factormismatch is correct. Last but not least, the standard deviation ofthe SD series resistance mismatch versus the channel width is pre-sented in Fig. 10. As can be seen, the RSD and the r(DRSD) follow thesame trend and more specifically their values decrease as the chan-nel width increases. Furthermore, a dependence on the gate lengthis observed at fixed width. Finally, it was found that the normalizedseries resistance local variability, r(DRSD)/RSD, is of the order of 5–20%, which is similar to FDSOI technologies [4].

4.2. Simulation results

To further verify the findings presented above, we performednumerical simulations of drain current mismatch characteristicsin both linear and saturation regions. In order to accurately repro-duce the drain current local variability behavior, we used a MOS-FET compact model based on Lambert W-function and recalledbelow [9],

IDðVG;VDÞ ¼WL

R VD0 leff ðVG;UcÞ � QiðVG;UcÞ � dUc

1þ 1L

R VD0

leff ðVG ;UcÞvsat

� RðVG;UcÞ � dUc

ð10Þ

where the inversion charge Qi is given by,

QiðVG;UcÞ ¼ CoxnkTqLWðeq�Vg�Vt�Uc

nkT Þ ð11Þ

with Uc being the quasi Fermi potential along the channel, Cox beingthe gate oxide capacitance, k � T=q the thermal voltage, n the sub-threshold ideality factor and vsat the saturation carrier velocity.The factor R is related to inversion capacitance and gate oxidecapacitance as [9],

RðVG;UcÞ ¼ Cinv

Cinv þ Coxð12Þ

voltage, VG, for different geometries in linear (a) and saturation region (b).

Fig. 4. Experimental results (symbols) of r2(DID/ID) versus gate voltage, VG, for small and large area devices in linear (a) and saturation (b) region and Model (lines).

Fig. 5. Channel conductance, gd as a function of the gate voltage, VG, in linear (solidline) and saturation region (dashed line) calculated from the nominal device(W = 0.08 lm and L = 0.03 lm).

Fig. 7. Individual matching parameter, iADVg versus gate voltage, VG in linear (blacksymbols) and saturation region (red symbols) for an n-MOS with W = 1 lm andL = 0.05 lm. (For interpretation of the references to color in this figure legend, thereader is referred to the web version of this article.)


where Cinv is the inversion charge capacitance. This factor allows toactivate the saturation velocity effect in strong inversion (R � 1)and to cancel it in weak inversion (R � 0). The effective mobility leff

is related as usual to the inversion charge by the first orderapproximation,

Fig. 6. Individual matching parameter iADVg versus gate voltage, VG extracted by exp

leff ¼l0

1þ h1 � ðQi=CoxÞ ; ð13Þ

where l0 is the low field mobility and h1 is the first order mobilityattenuation coefficient.

erimental data in linear (a) and saturation region (b) for different geometries.

Fig. 8. iADVt versus channel length, L in linear (black symbols) and saturation region(red symbols) for 28 nm BULK nMOSFETs. (For interpretation of the references tocolor in this figure legend, the reader is referred to the web version of this article.)

Fig. 9. iADb=b versus channel length, L in linear (black symbols) and saturationregion (red symbols) for 28 nm BULK nMOSFETs. (For interpretation of thereferences to color in this figure legend, the reader is referred to the web versionof this article.)

Fig. 10. Source – Drain, SD series resistance (blue symbols) and its mismatch bothin linear (black symbols) and saturation region (red symbols) versus channel width,W for 28 nm BULK n-MOSFETs. (For interpretation of the references to color in thisfigure legend, the reader is referred to the web version of this article.)

Fig. 11. Simulation results of r(DID/ID) versus gate voltage, VG for n-MOS deviceswith channel length L = 1 lm and channel widthW = 1 lm for linear (solid line) andsaturation (dashed line) regions.

Fig. 12. Simulation results of parameter iADVg versus gate voltage, VG for n-MOSwith channel length L = 1 lm and channel widthW = 1 lm for linear (solid line) andsaturation (dashed line) regions.

T.A. Karatsori et al. / Solid-State Electronics 128 (2017) 31–36 35

The effect of the SD series resistance has then been taken intoaccount through the gate and drain voltage drops asVG ¼ VG0 � ðRSD=2Þ � ID and VD ¼ VD0 � RSD � ID, VG0 and VD0 beingthe intrinsic gate and drain to source voltages, respectively.

Then, based on the above MOSFET model, the standard devia-tion of the drain current variability has been calculated numeri-

cally using the sensitivity equation (2) for ID with respect to Vt, band RSD for any gate and drain voltage. Fig. 11 shows typical simu-lated variations of r(DID/ID) with VG in the linear and saturationregions. It confirms that the DRSD mismatch has a smaller impacton the drain current variability in the saturation region, thus veri-fying the experimental results behavior. This finding is also sup-ported by the simulated individual matching parametercharacteristics, iADVgðVGÞ, which is also lower in saturation region(see Fig. 12).

5. Conclusions

The impact of the SD series resistance mismatch on the draincurrent variability has been investigated for 28 nm Bulk MOSFETs.A mismatch model that takes into consideration the RSD local vari-ability was developed and used to extract all mismatch parame-ters, including r(DVt), r(Db/b) and r(DRSD), in the linear andsaturation regions. It has been demonstrated that the impact ofRSD on the drain current variability is reduced in the saturationregion due to the lower drain current sensitivity from the seriesresistance variation. Finally, as in FDSOI devices, the SD seriesresistance mismatch, r(DRSD), was found to scale down with gatewidth as RSD, and the normalized series resistance local variabilityparameter r(DRSD)/RSD takes similar values as in FDSOI, demon-strating very good access resistance control in bulk technology.

Acknowledgments

This work has been partly supported by the ENIAC places2beand ECSEL Waytogo Fast projects.


References

[1] Pelgrom MJM, Duinmaijer ACJ, Welbers APG. Matching properties of MOStransistors. IEEE J Solid-State Circ 1989;24:1433–9.

[2] Croon JA, Rosmeulen M, Decoutere S, Sansen W. An easy-to-use mismatchmodel for the MOS transistor. IEEE J Solid State Circ 2002;37:1056–64.

[3] Rahhal L, Bajolet A, Diouf C, Cros A, Rosa J, Planes N, et al. New methodology fordrain current local variability characterization using Y Function method. In:Proc IEEE Intern Conf Microelectronic Test Structures (ICMTS’13). Osaka (Japan).p. 99–103.

[4] Ioannidis EG, Theodorou CG, Haendler S, Josse E, Dimitriadis CA, Ghibaudo G.Impact of source-drain series resistance on drain current mismatch in advancedfully depleted SOI n-MOSFETs. IEEE Electron Dev Lett 2015;36:433–5.

[5] Ioannidis EG, Haendler S, Josse E, Planes N, Ghibaudo G. Characterization andmodeling of drain current local variability in 28 and 14 nm FDSOI nMOSFETs.Solid State Electron 2016;118:4–11.

[6] Ghibaudo G. New method for the extraction of MOSFET parameters. ElectronLett 1988;24:543–5.

[7] Cathignol A, Bordez S, Cros A, Rochereau K, Ghibaudo G. Abnormally high localfluctuations in heavily pocket-implanted bulk long MOSFET. Solid State Electron2009;53:127–33.

[8] Rahhal L, Bajolet A, Manceau JP, Rosa J, Ricq S, Lassere S, et al. Mismatch trendsin 20 nm gate-last bulk CMOS technology. In: Proc IEEE Intern Conf UltimateIntegration on Silicon (ULIS’14). Stockholm (Sweden). p. 133–6.

[9] Shin M, Shi M, Mouis M, Cros A, Josse E, Mukhopadhyay S, et al. Experimentaland theoretical investigation of magnetoresistance from linear regime tosaturation in 14 nm FDSOI MOS devices. IEEE Trans Electron Dev 2015;62:3–8.

http://refhub.elsevier.com/S0038-1101(16)30185-X/h0005
































Benchmarks of a III-V TFET technology platform against the 10-nmCMOS FinFET technology node considering basic arithmetic circuits


⇑ Corresponding author.E-mail address: [email protected] (S. Strangio).

S. Strangio a,⇑, P. Palestri a, M. Lanuzza b, D. Esseni a, F. Crupi b, L. Selmi a

aDPIA, Università degli Studi di Udine, Via delle Scienze 206, 33100 Udine, ItalybDIMES, Università della Calabria, Via P. Bucci, 41C, I-87036 Arcavacata di Rende (CS), Italy




Keywords:III-VTFETFull addersRipple carry adders

a b s t r a c t

In this work, a benchmark for low-power digital applications of a III-V TFET technology platform against aconventional CMOS FinFET technology node is proposed. The analysis focuses on full-adder circuits,which are commonly identified as representative of the digital logic environment. 28T and 24T topolo-gies, implemented in complementary-logic and transmission-gate logic, respectively, are investigated.Transient simulations are performed with a purpose-built test-bench on each single-bit full adder solu-tion. The extracted delays and energy characteristics are post-processed and translated into figures-of-merit for multi-bit ripple-carry-adders. Trends related to the different full-adder implementations (forthe same device technology platform) and to the different technology platforms (for the same full-adder topology) are presented and discussed.


1. Introduction

The sub-threshold swing (SS) represents the key device param-eter to improve the energy efficiency of digital circuits. Among var-ious device proposals for future low power applications, the tunnelfield-effect-transistor (TFET) beat the conventional MOSFET and isconsidered as promising solution to achieve sub-60 mV/dec opera-tion at 300 K in standard CMOS compatible processes [1–13].Therefore, many efforts are being devoted to the fabrication ofTFETs with high performance electrical characteristics [1–5]. Inthis context, full-quantum simulators [6–8] are widely used asmodeling tools to guide the design of such innovative devices,whereas mixed device/circuit simulations are exploited for earlyanalysis at circuit level [9–13]. A virtual III-V TFET technology plat-form has been recently proposed by Baravelli et al. based on 3Dfull-quantum simulations [7,8]. An early benchmark against afuture CMOS FinFET platform [14,15], based on single device andinverter operation, has been shown [8]. In particular, since the fullquantum modeling approach used in [8] does not allow to performcircuit simulations, the inverter operation and the related figures-of-merit (e.g. voltage transfer characteristics - VTC -, VOUT/VIN gain,intrinsic rise and fall times, etc.) have been estimated (i.e. consid-ering the device drain current characteristics and assuming equiv-

alent effective capacitive loads instead of the intrinsic devicecapacitance characteristics).

The purpose of the present paper is to extend such a bench-mark, by considering various 24T and 28T full-adders (FA) blocksas vehicle circuits. Figures-of-merit such as delay and averageenergy per cycle are extracted and discussed for both TFET andCMOS FinFET implementations. The present paper is an extendedversion of the work presented at EUROSOI-ULIS 2016 Conference[13], where only preliminary results on the standard 28T full-adder topology were discussed.

2. Simulation methodology

Fig. 1 sketches the device structures considered in this work,which are: (1) the complementary square cross-section InAs/AlGaSb TFET nanowires proposed in [8]; (2) the 10-nm node CMOSFinFETs described in [14].

Our analysis uses a multi-scale simulation approach, rangingfrom device simulations to circuit simulations. As regards theTFETs, the TCAD simulator Sentaurus SDEVICE [16] has been cali-brated to reproduce the full-quantum simulation of the AlGaSb/InAs hetero-structure [7,8]. At the circuit level, the look-up table(LUT) compact models implemented in Verilog-A enabled time-efficient simulations. As regards the CMOS FinFETs, we used thePredictive-Technology-Models of Multi-Gate transistors (PTM-MG) projected to the 10-nm node available at [15].







Fig. 1. n- and p-type TFET and FinFET (CMOS) device architectures. The red andblue colors indicate the n- and p-doping types, respectively (green: intrinsicsemiconductor, transparent-grey: oxide). TFET dimensions are: LG = 20 nm, nano-wire cross section (LS) = 7 nm, EOT = 1 nm. FinFET dimensions are: LG = 14 nm,tfin = 9 nm, hfin = 21 nm, EOT = 0.7 nm. (For interpretation of the references to colorin this figure legend, the reader is referred to the web version of this article.)

-0.4 -0.3 -0.2 -0.1 010

-11

10-10

10-9

10-8

10-7

10-6

10-5

VDS=-0.4V

VGS (V)

|Dra

in C

urre

nt| (

A)

(a)

pMOSpTFET

0 0.1 0.2 0.3 0.410

-11

10-10

10-9

10-8

10-7

10-6

10-5

VDS=0.4V

VGS (V)

Dra

in C

urre

nt (A

)

(b)

nMOSnTFET

Fig. 2. Transfer-characteristics (ID-VGS) at |VDS| = 400 mV for the transistors simu-lated in this work. Off-currents are matched at 35 pA at |VDS| = 400 mV and |VGS|= 0 V.

-0.5 -0.4 -0.3 -0.2 -0.1 00

0.5

1

1.5

2

2.5

3

VGS=-0.35V

VDS (V)

|Dra

in C

urre

nt| (

A)

(a)pMOSpTFET

0 0.1 0.2 0.3 0.4 0.50

0.5

1

1.5

2

2.5

3

VGS=0.35V

VDS (V)

Dra

in C

urre

nt (

A)

(b)nMOSnTFET

Fig. 3. Output-characteristics (ID-VDS) at |VGS| = 350 mV for the transistors simu-lated in this work.

38 S. Strangio et al. / Solid-State Electronics 128 (2017) 37–42

2.1. Devices and calibration of TFET models

The III-V TFET technology platform consists of n-type andp-type AlGaSb/InAs TFET nanowires. Due to quantum confinementin the 7 � 7 nm2 square cross-section of the nanowire, the defaultsetup of the TCAD model parameters is not adequate. Thus, theenergy-gap (EG) and the electron affinity (v) have been chosen soas to reproduce the same band alignment as in [7]. The dynamicnonlocal-path Band-to-Band Tunneling (BtBT) model parametersfor the direct tunneling process (Apath,dir and Bpath,dir, see [16]) werealso recalculated by using the effective masses from bulk GaSb andInAs [17]. Finally, the effective valence and conduction band den-sity of states (NV and NC) have been increased compared to thedefault value for bulk crystals to improve the matching of the I-Vcurves between TCAD and full-quantum results. The calibratedparameters are summarized in Table 1.

Fig. 2 shows the ID-VGS transfer-characteristics of p-type and n-type TFET and FinFET devices. For reference, the TFET ID-VGS

obtained from full-quantum simulations [8] are also included(symbols). For the same off-current (IOFF) of 35 pA, the pTFET fea-tures a lower on-current (about 1/4) than the nTFET at VDD = 400 -mV. Despite this asymmetry, we keep a 1/1 ratio between the sizeof the nTFETs and pTFETs in the following circuit analysis. Differ-ently from TFETs, the ID-VGS of the n-type and p-type FinFETs(red lines) are essentially symmetric.

Table 1Calibrated parameters used in the TCAD simulations of the AlGaSb/InAs TFETtemplates.

Parameter Al0.05Ga0.95Sb InAs

Band-gap parameters (including quantization effects)Energy gap EG (eV) 1.04 0.59Electron affinity v (eV) 4.01 4.9

Dynamic non-local BtBT model parametersApath (cm�3s�1) 1.51 � 1020 1.44 � 1020Bpath (V/cm) 9.54 � 106 2.94 � 106

Effective conduction and valence band density of statesNC (cm�3) 1.26 � 1018 5.22 � 1017NV (cm�3) 1.8 � 1019 6.6 � 1018

Fig. 3 reports the output characteristics ID-VDS at VGS = 350 mVfor all the considered devices. The TFETs feature a delayed turn-on behavior (superliner ID-VDS [18]), but also a better saturationthan FinFETs at |VDS| above 300 mV.

2.2. Circuit simulations

TFETs have uni-directional IDS-VDS characteristics and thussource and drain terminals cannot be exchanged as in conventionalMOSFETs. The source is thus marked in the TFET symbol, seeFig. 4a. For circuit simulations we employ a Verilog-A model(sketched in Fig. 4b) implemented within the Cadence environ-ment. LUTs including the drain current ID, the gate-to-sourcecapacitance Cgs and the gate-to-drain capacitance Cgd were set up

Look-Up Tables:IDS (VDS ,VGS)Cgd (VDS ,VGS)Cgs (VDS ,VGS)

TFET Verilog-A model(b)

TFET symbols(a)

nTFET

pTFET

G

S

D

G

D

S

IDS

G

S

D

igd

igs

iD

iS

iG

iGate = igd + igs

iDrain = IDS − igd

iSource = −(IDS + igs)

Fig. 4. (a) n-type and p-type TFET symbols definition. (b) Sketch of the Verilog-Amodel based on the look-up tables with the values of ID, Cgs and Cgd as a function ofVDS and VGS.

S. Strangio et al. / Solid-State Electronics 128 (2017) 37–42 39

using the TCAD, by simulating the device at bias points in the VGS

and VDS range (between �800 mV and 800 mV, with 10 mV voltagestep).

As an example of circuit simulation with the proposedapproach, we consider a self-loading inverter, that is an inverterloaded by an identical inverter (Fig. 5a). This condition has beenalready studied in [8], by assuming an equivalent constant loadcapacitance representative of both the input capacitance Cin ofthe loading inverter and of the Miller capacitance due to the deviceCgds of the driving inverter itself. Differently from [8], however,here we simulate the inverter by taking into account the actualbias dependence of the device capacitances, i.e. by employing cur-rent and capacitance LUTs for all the devices, as sketched in Fig. 5a.Fig. 5b and c show the simulated voltage signals for both the riseand fall transitions of the output voltage, respectively. As explainedin [13], since we consider the Miller capacitances as bias-dependent capacitors connected between input and output andnot only as an effective load, the simulated output waveformsshow a plateau as well as a voltage under/overshoot, which arepeculiar behaviors due to the input-to-output capacitive coupling.These features were not included in the simplified estimation of[8], thus resulting in an underestimation of the rise and fall times[13].

3. Benchmark of TFETs vs FinFETs considering full-adders

In this section, the vehicle circuits used for the benchmark arepresented along with the benchmarking protocol. Then, the simu-lation results are presented and discussed.

0 16 32 48 64 80 96 112-0.2

0

0.2

0.4

time (ps)

sign

als

(V)

Vin Vo

0 4 8 12 16 20 24 280

0.2

0.4

0.6

time (ps)

sign

als

(V)

Vin Vo

Self-

load

ing

inve

rter

(a)

(b)

(c)

Tn1

GND

VDD

GND

VDD

Tp1

Tn2

Tp2

ID,P

ID,N

ID,P

ID,N

VoVin

Fig. 5. Schematic of the self-loading inverter simulated in Verilog-A (a). Transientsimulations reporting the rise (b) and fall (c) transitions. Rise time = 92 ps; falltime = 25 ps.

3.1. Full-adder topologies

The transistor level designs of the full-adder topologies arereported in Fig. 6 (TFET implementations only). We consider thestandard and the mirror implementations with 28 transistors(Fig. 6a and b, respectively), and the transmission-gate implemen-tation with driving capacitance (24T-tgd in the following), that iswith inverter stages acting as output buffers, implemented with24 transistors (Fig. 6c). Concerning the 24T-tgd, due to the unidi-rectional conduction of TFETs, the correct operation of the adderis ensured only if the n- and p-type TFETs implementing thetransmission-gates are properly connected. In particular, the cir-cuit schematic is such that the nTFET and the pTFET of eachtransmission-gate has the source (drain) connected toward theinput (output) pin. In fact, although both devices are active duringthe transmission phase (i.e. when VGS

nTFET = VDD and VGSpTFET = 0), only

the n-type (p-type) device is efficient in transmitting the ‘0’ (‘1’)logic value. Thanks to this arrangement of the transistors, thenTFET transmits the logic ‘0’ by allowing the current to flow inthe direction opposite to the data flow (i.e. from outputs towardinputs), whereas the pTFET permits the transmission of the logic‘1’ (with the current flowing in the same direction as the dataflow). In case of bidirectional transistors (as for FinFETs) there isno need to take care of the device orientation due to symmetricdrain/source terminals.

Although other full-adder implementations are possible [19,20],they will not be considered here because they are amenable tooperate in the ultra-low voltage regime (e.g. the transmission-gate topology without output buffers) which is the focus of thepresent paper.

3.2. Test bench and simulation protocol

The block diagram in Fig. 7 has been conceived as a general test-bench for the simulation of full-adders under normal operatingconditions. In fact, the block under test (central box) is placed ina framework including realistic driving and loading blocks. TheAwfm, Bwfm and Cwfm signals consist of random binary waveformswith a length of 100 bits, where each bit is held for a bit-time (Tbit)of 100 ns. This relatively relaxed timing condition has been chosenin order to allow the circuit to operate down to ultra-low VDD

values.For each transition of the sum waveform Swfm, the related delay

is computed, taking as a reference the specific input signal thattriggers the transition (i.e. the latest signal to switch among Awfm,Bwfm and Cwfm). The delay of the carry out signal Co is calculatedfor different cases: propagation of ‘1’ or ‘0’ (P1 and P0), generatecarry (G), delete carry (D). In the ‘‘propagate” mode (i.e. whenA– B), Cowfm follows Cwfm. In the ‘‘generate” and ‘‘delete” modes(i.e. when A = B), we have Co = A = B, regardless of the valueassumed by C. Thus, for each transition of Co, the delay is com-puted taking as a reference either C (when the Co transition takesplace in the ‘‘propagate” mode) or the latest signal to flip betweenA and B (‘‘generate” or ‘‘delete” modes). Although it is possible todefine various delay metrics as discussed above, we will here con-sider the propagation delay (tPropagation). This corresponds to theworst case delay between Co(P1) and Co(P0) and it is the bottle-neck for a multi-bit full-adder implemented as a Ripple-Carry-Adder (RCA) [20], where the theoretical minimum clock period TCLKis given approximately by N � tPropagation, with N being the lengthof the bit words.

The total energy is calculated by integrating the productVDD�iDD,wfm over the simulation time, being iDD,wfm the waveformof the overall current flowing through the full-adder under test.This is then normalized to extract the average energy per bit cycle

VDD

A

C

Co

B

A

C

A B

A

B

A

B

C

A

B

C

S

CB

GND

A CB

BA

28

27

1 2 13 14 15

18 19 205 6

21

22

23

24

25

26

3

49

10

7

8 16

17

11

12

VDD

A B

C

Co

B

A

C

A B

A

B

A

B

C

A

B

C

S

A CB

GND

A CB

28

27

1 2 13 14 15

18 19 205 6

21

22

23

24

25

26

3

4

9

10

7

8 16

17

11

12

A

B

GND

VDD

PN

P

ANCo

GND

VDD

PN

PN

P

PN

P

CN

C

C

GND

VDD

CN

S

GND

VDD

1

2

11

12

9

10

7

8

5

6

3

4

15

16

13

14

19

20

17

18

21

22

23

24

(a)

28T

stan

dard

(b)

28T

mirr

or

(c)

24T

TGD

Fig. 6. Schematic of the full-adder implementations considered in this work: (a) 28T standard, (b) 28T mirror, (c) 24T transmission-gate with output buffers (inverters).


(i.e. per Tbit = 100 ns in this case) as Etot@½Tbit¼100ns�per bit cycle ¼VDD100

R TSim0 iDDdt, where TSim is the overall simulation time (TSim = 100-

�Tbit = 10 ls). At the same time, the steady state current is sampledat the end of each cycle (IDD,DC(i) , ‘i’ being the index of the cycle) inorder to calculate the average static power as PStat;avg ¼VDD100

P1001 IðiÞDD;DC and the static energy as EStat@½Tbit¼100 ns�per bit cycle ¼

PStat;avg � Tbit . Consequently, the average dynamic energy

(EDynper bit cycle) can be also extracted, as the differencebetween the overall energy per cycle and the average static energyper cycle (note that the dynamic energy is essentially independenton Tbit).

In order to evaluate the minimum energy per clock cycleneeded by a 32-bit RCA for various VDD values, results extractedfrom such single-bit blocks were post-processed and translated

+ Ci-1Coi+1

Si+1

‘0’ ‘1’(propagate)

Awfm

A B

CCo

S

Si-1

A B

CCo

S

(Open)

(Open)

(Open)

(Open)

‘0’ ‘1’

Bwfm Cwfm

(propagate)

Cowfm

Awfm Bwfm

Swfm

Cwfm

A B

CCo

S

(random binary sequences)

++

Fig. 7. Simulated test-bench reproducing a normal operating condition for the full-adder under test (central block). Input signals: Awfm , Bwfm and Cwfm. The voltage signals Awfm ,Bwfm , Cwfm , Swfm , Cowfm , as well as the waveform of the overall current absorbed by the full-adder under test are post processed in order to obtain the figures-of-merit ofinterest.

S. Strangio et al. / Solid-State Electronics 128 (2017) 37–42 41

into figures-of-merit for multi-bit adders. A clock period TCLK equalto the minimum time that ensures a correct functioning isassumed. TCLK is estimated as c�N�tPropagation for each VDD, where cis a correction factor to accommodate the worst case propagationdelay, and N is the number of bits of the input operands (in thisstudy: c = 2, N = 32). Then, for each VDD, besides weighting thedynamic energy and the static power to the 32 blocks of the 32-

bit RCAs (E32bit�RCADyn ¼ 32 � E1bit�FA

Dyn and P32bit�RCAStat;avg ¼ 32 � P1bit�FA

Stat;avg , respec-tively), the average static power is multiplied by the minimum TCLK(instead of the fixed Tbit of 100 ns used for the simulations) to

obtain the corresponding static energy (E32bit�RCAStat ¼ P32bit�RCA

Stat;avg � TCLK).

4. Results

Fig. 8 reports the propagation delays of all the considered full-adder blocks. For the same technology platform, the 28T mirrorimplementation turned out to be the fastest, whereas the 24T-tgd is the slowest (see insets in linear scale). However, irrespectiveof the particular circuit implementation, the TFET-based circuitsshow less performance degradation when scaling VDD comparedto FinFETs; this allows the TFET solutions to become faster thantheir FinFET counterparts for VDD below �350 mV. Beside the triv-ial consequence that TFET circuits can operate at a higher clock fre-quency for such reduced VDD, the smaller performance degradation

100 200 300 400 500 10p

100p

1n

10n

100n

VDD (mV)

t Prop

agat

ion (s

)

FinFETTFET

28T std 28T mir 24T tgd

299 300 3012.62.8

33.2

x 10-10

299 300 3018.5

99.510

x 10-10

Fig. 8. Propagation delays of the three full-adder topologies, implemented eitherwith TFETs or with FinFETs.

with VDD scaling with respect to FinFETs has also implications fromthe energy point of view.

In fact, in the energy balance of a circuit, both static anddynamic energy components can be relevant. In particular, at highVDD values the dynamic energy per cycle (Edynamic = a�CL,eq�VDD

2 ,where a is the activity and CL,eq is the equivalent capacitiveload of the circuit) is dominant; on the other hand, when theVDD is scaled down, an increasingly relaxed TCLK is neededdue to larger delays, thus the static energy component(EStatic per cycle = TCLK�VDD�Ileak) becomes dominant.

Fig. 9 reports the estimated static, dynamic and total energy percycle for 32-bit RCAs (each corresponding to 32 blocks of thetopologies in Fig. 6, with either TFETs or FinFETs). The static energyin Fig. 9a follows qualitatively the same trends as the tPropagation inFig. 8 (aside from its further dependence on VDD); in fact theincrease of TCLK with the VDD scaling is much more pronouncedthan the linear dependence of EStatic on VDD. For both the TFETand FinFET technologies, the 24T-tgd solution features slightly lar-ger static energy consumption than the 28T implementations,despite the reduced number of transistors. A systematic analysisof the leakage paths suggests the following explanation for thisfinding: for certain input conditions (e.g. (A,B,C) = (’0’,‘0’,‘0’)), inthe 24T-tgd adders there is a larger number of off-state transistorswhich are biased with |VDS| = VDD, whereas in the 28T implementa-tion the |VDS| is smaller because of the voltage partitioningbetween off-state transistors in series thanks to the staking effect[21].

Looking at the dynamic energy components (Fig. 9b), the 24Tsolutions feature slightly lower active energy consumption percycle, due to reduced effective load capacitance of the circuit.

The total energy per cycle for all the considered 32-bit RCAs isreported in Fig. 9c. For both technology platforms, the RCAs imple-mented with 32 24T-tgd blocks feature, compared to the RCAsimplemented with 32 28T blocks, a slight energy saving at largeVDD (i.e. where the dynamic energy dominates) but also a slightenergy penalty at reduced VDD (i.e. where the static energydominates). It should be noticed that, irrespective of the selectedcircuit topology, the minimum energy point (MEP) for all theFinFET implementations is close to 1000 aJ/cycle for a VDD

close to 250 mV, whereas for the TFET implementations it is about140 aJ/cycle for a smaller VDD close to 150 mV.

These results indicate that, from an energy efficiency point ofview, using steep slope devices is more efficient than changingthe circuit architecture.

100 200 300 400 500

101

102

103

(a)

VDD (mV)

E Sta

tic (a

J/cy

c)

FinFET

TFET

28T std28T mir24T tgd

100 200 300 400 500

101

102

103

104(b)

VDD (mV)

E Dyn

amic (a

J/cy

c)

FinFET

TFET 28T std28T mir24T tgd

100 200 300 400 500102

103

104(c)

VDD (mV)

ETo

tal (a

J/cy

c)

TFET

FinFET

28T std 28T mir 24T tgd

Fig. 9. 32-bit ripple-carry-adder: (a) static energy per cycle, (b) dynamic energy percycle and (c) total energy per cycle as a function of VDD.


5. Conclusions

A III-V TFET technology platform has been benchmarked againstthe predictive models for the 10 nm node CMOS FinFETs, consider-ing three topologies of full-adder as test circuits. The propagationdelay has been selected as the main performance figure-of-meritfor single-bit full-adders. Irrespective of the particular circuittopology, full-adders implemented with TFETs are faster than thecorresponding solutions implemented with FinFET technology forVDD below 350 mV. Considering 32-bit ripple carry adders imple-mented with a chain of 32 single-bit full-adder blocks, the TFET cir-cuits allow energy saving at any VDD in the considered range; inparticular, the minimum energy per cycle of each TFET implemen-tation is �140 aJ/cycle (at VDD = 150 mV), well below the minimumenergy point of �1000 aJ/cycle values for the FinFET implementa-tions (at VDD = 250 mV). The difference in performance and energyproduced by the circuit topology is practically negligible comparedto the differences corresponding to that due to the transistortechnology.

Acknowledgment

The research leading to these results has received funding fromthe European Community’s Seventh Framework Programme undergrant agreement No. 619509 (project E2SWITCH).

References

[1] Ionescu A, Riel H. Tunnel field-effect transistors as energyefficient electronicswitches. Nature 2011;479(7373):329–37.

[2] Dewey G, Chu-Kung B, Boardman J, Fastenau JM, Kavalieros J, Kotlyar R, LiuWK, Lubyshev D, Metz M, Mukherjee N, Oakey P, Pillarisetty R, RadosavljevicM, Then HW, Chau R. Fabrication, characterization, and physics of III–Vheterojunction tunneling Field Effect Transistors (H-TFET) for steep sub-threshold swing‘‘. In: IEEE International Electron Devices Meeting (IEDM).http://dx.doi.org/10.1109/IEDM.2011.6131666. pp. 33.6.1-33.6.4, 5–7 Dec..

[3] Mohata DK et al. Demonstration of MOSFET-like on-current performance inarsenide/antimonide tunnel FETs with staggered hetero-junctions for 300 mVlogic applications. Washington, DC: IEEE International Electron DevicesMeeting (IEDM); 2011. http://dx.doi.org/10.1109/IEDM.2011.6131665. pp.33.5.1–33.5.4.

[4] Guangle Zhou, Li R, Vasen T, Qi M, Chae S, Lu Y, Zhang Q, Zhu H, Kuo J-M, KoselT, Wistey M, Fay P, Seabaugh A, Huili Xing. Novel gate-recessed vertical InAs/GaSb TFETs with record high ION of 180 lA/lm at VDS = 0.5 V. IEEEInternational Electron Devices Meeting (IEDM); 2012. http://dx.doi.org/10.1109/IEDM.2012.6479154. pp. 32.6.1-32.6.4, 10–13 Dec. 2012.

[5] Luong GV, Strangio S, Tiedemannn A, Lenk S, Trellenkamp S, Bourdelle KK, ZhaoQT, Mantl S. Experimental demonstration of strained Si nanowire GAA n-TFETsand inverter operation with complementary TFET logic at low supply voltages.Solid-State Electron 2016;115(Part B):152–9. January, ISSN 0038–1101.

[6] Luisier M, Klimeck G. Performance comparisons of tunneling field-effecttransistors made of InSb, Carbon, and GaSb-InAs broken gapheterostructures. IEEE International Electron Devices Meeting (IEDM); 2009.p. 1–4. http://dx.doi.org/10.1109/IEDM.2009.5424280. 7-9 Dec.

[7] Baravelli E, Gnani E, Grassi R, Gnudi A, Reggiani S, Baccarani G. Optimization ofn- and p-type TFETs Integrated on the Same InAs/AlxGa1-xSb TechnologyPlatform. IEEE Trans Electron Dev 2014;61(1):178–85. http://dx.doi.org/10.1109/TED.2013.2289739.

[8] Baravelli E, Gnani E, Gnudi A, Reggiani S, Baccarani G. TFET inverters with n-/p-devices on the same technology platform for low-voltage/low-powerapplications. IEEE Trans Electron Dev 2014;61(2):473–8. http://dx.doi.org/10.1109/TED.2013.2294792.

[9] Morris DH, Avci UE, Rios R, Young IA. Design of low voltage tunneling-FET logiccircuits considering asymmetric conduction characteristics. IEEE J EmergSelect Topics Circuits Syst 2014;4(4):380–8. http://dx.doi.org/10.1109/JETCAS.2014.2361054.

[10] Avci UE, Morris DH, Young IA. Tunnel field-effect transistors: prospects andchallenges. IEEE J Electron Dev Soc 2015;3(3):88–95. http://dx.doi.org/10.1109/JEDS.2015.2390591.

[11] Strangio S, Palestri P, Esseni D, Selmi L, Crupi F, Richter S, Qing-Tai Zhao, MantlS. Impact of TFET unidirectionality and ambipolarity on the performance of 6TSRAM cells. IEEE J Electron Dev Soc 2015;3(3):223–32. http://dx.doi.org/10.1109/JEDS.2015.2392793. May.

[12] Lanuzza M, Strangio S, Crupi F, Palestri P, Esseni D. Mixed tunnel-FET/MOSFETlevel shifters: a new proposal to extend the tunnel-FET application domain.IEEE Trans Electron Dev 2015;62(12):3973–9. http://dx.doi.org/10.1109/TED.2015.2494845.

[13] Strangio S, Palestri P, Lanuzza M, Esseni D, Crupi F, Selmi L. Benchmarks of a III-V TFET technology platform against the 10-nm CMOS technology nodeconsidering 28T Full-Adders. In: 2016 Joint International EUROSOI Workshopand International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS). Vienna, Austria: Wien; 2016. p. 139–42. http://dx.doi.org/10.1109/ULIS.2016.7440072.

[14] Sinha S, Yeric G, Chandra V, Cline B, Yu Cao. Exploring sub-20 nm FinFETdesign with predictive technology models. In: 2012 49th ACM/EDAC/IEEEDesign Automation Conference (DAC). p. 283–8. http://dx.doi.org/10.1145/2228360.2228414. 3–7 June 2012.

[15] URL: http://ptm.asu.edu.[16] TCAD Sentaurus Device U.G., version G-2012.06; 2012.[17] URL: http://www.ioffe.ru/SVA/NSM/Semicond/.[18] De Michielis L, Lattanzio L, Ionescu AM. Understanding the superlinear onset

of tunnel-FET output characteristic. IEEE Electron Dev Lett 2012;33(11):1523–5.

[19] Weste Neil, Harris David. CMOS VLSI Design: a circuits and systemsperspective. 4th ed. USA: Addison-Wesley Publishing Company; 2010.

[20] Alioto M, Palumbo G. Analysis and comparison on full adder block insubmicron technology. IEEE Trans Very Large Scale Integr VLSI Syst 2002;10(6):806–23. http://dx.doi.org/10.1109/TVLSI.2002.808446.

[21] Magnone P, Crupi F, Alioto M, Kaczer B, De Jaeger B. Understanding thepotential and the limits of germanium pMOSFETs for VLSI circuits fromexperimental measurements. IEEE Trans Very Large Scale Integr VLSI Syst2011;19(9):1569–82.
















http://dx.doi.org/10.1109/JETCAS.2014.2361054

http://dx.doi.org/10.1109/JETCAS.2014.2361054

http://dx.doi.org/10.1109/JEDS.2015.2390591






http://dx.doi.org/10.1109/ULIS.2016.7440072


http://dx.doi.org/10.1145/2228360.2228414

http://dx.doi.org/10.1145/2228360.2228414

http://ptm.asu.edu

http://www.ioffe.ru/SVA/NSM/Semicond/






http://dx.doi.org/10.1109/TVLSI.2002.808446









Study of line-TFET analog performance comparing with other TFET andMOSFET architectures


⇑ Corresponding author at: LSI/PSI/USP – University of São Paulo, Av. Prof.Luciano Gualberto, trav. 3 no 158, 05508-010 Sao Paulo, Brazil.

E-mail address: [email protected] (P.G.D. Agopian).

Paula Ghedini Der Agopian a,b,⇑, João Antonio Martino a, Anne Vandooren c, Rita Rooyackers c, Eddy Simoen c,Aaron Thean c, Cor Claeys c,d

a LSI/PSI/USP – University of São Paulo, Av. Prof. Luciano Gualberto, trav. 3 no 158, 05508-010 Sao Paulo, BrazilbUNESP – Universidade Estadual Paulista, São João da Boa Vista, Brazilc imec, Kapeldreef 75, B-3001 Leuven, Belgiumd E.E. Dept, KULeuven, Leuven, Belgium




Keywords:Line-TFETIntrinsic voltage gainDifferent device architectures

a b s t r a c t

In this work the Line-TFET performance is compared with MOSFET and Point-TFET devices, with differentarchitectures (FinFET and GAA:Gate-All-Around) at both room and high temperatures. This analysis isbased on the experimental basic analog parameters such as transconductance (gm), output conductance(gD) and intrinsic voltage gain (AV). Although the Line-TFETs present worse AV than the point-TFETs,when they are compared with MOSFET technology, the line-TFET shows a much better intrinsic voltagegain than both MOSFET architectures (FinFET and GAA). Besides the AV, the highest on-state current wasobtained for Line-TFETs when compared with other two TFET architectures, which leads to a good com-promise for analog application.


1. Introduction

Tunnel-FETs have been proposed by the international commu-nity as an alternative for MOSFETs, when focusing on extremelysmall technology nodes, due to their high speed switching capabil-ity [1] that allows to improve the energy efficiency of switches.However, as the low on-current is a problem of homo-junctionTFETs, several works report research on different materials and dif-ferent geometries aiming to reach a smaller subthreshold swingand an on-current improvement [2,3].

A planar Line-TFET is an alternative structure that increases theelectric field at the source-pocket junction and consequentlyimproves the on-current and reduces the subthreshold swingwhen compared with the point-TFET silicon devices [4–6].

Although the main focus of the tunnel-FET is the digital switch,some recent work has also pointed out the great potential of thesedevices for analog applications [7–10].

In this work the planar heterojunction Line-nTFET is experi-mentally analyzed through the basic analog parameters, focusingmainly on intrinsic voltage gain. A comparison of the intrinsic volt-age gain of Line-TFETs with devices with different architectures

like FinFET (MOSFET and TFETs) [7] and Gate-all-around (MOSFETand TFET) [11] is also performed, for temperatures ranging fromroom up to 150 �C. For vertical GAA-TFETs, different source compo-sitions (Si and Si0.73Ge0.27) will be also considered.

2. Device characteristics

The studied Line-nTFETs are Si/SiGe heterojunction devices fab-ricated on silicon-on-insulator wafers at imec/Belgium. The p-typeSi0.55Ge0.45 source extends under the gate and a thin intrinsic sili-con pocket layer (�5 nm) is on top. The source and the drainregions are separated by a nominally undoped Si channel.

The gate stack is composed by a 1 nm interfacial SiO2 layer fol-lowed by 1.8 nm of HfO2, 2 nm of TiN and p-doped amorphous sil-icon. The channel width (W) ranges from 110 nm to 200 nm andtwo different gate lengths (L) (1 lm and 130 nm) were evaluated.

Fig. 1 presents a schematic structure of a Line-TFET and moredetails on this structure/fabrication can be found in [6].

3. Analysis and discussion

Since the source of Line-TFETs extends under the gate region,this architecture promotes tunneling in the same electric fielddirection, which is more efficient than the conventional point-tunneling. Besides, the position of the tunneling source/channel







Fig. 1. Line-TFET structure.

0.0 0.5 1.0 1.5 2.010-12

10-10

10-8

10-6

10-4

0.0 0.5 1.0 1.5 2.00

7

14

21

28

VDS=0.5V VDS=0.7V VDS=0.9V VDS=1.2V VDS=1.5V

better SS region

Line-TFETL=1 m

VDS increase

I DS (A

/m

)

VGS (V)

A I DS (

A)

VGS (V)

-0.5 0.0 0.5 1.0 1.5 2.010-15

10-13

10-11

10 -9

10 -7

VDS=1.5V

Increase [Ge]

at source

Ge Si0.56Ge0.44

Si0.73Ge0.27

Si

I DS (A

/m

)

VGS

(V)

B

GAA-nTFET

Fig. 2. Experimental normalized transfer curves of a Line-TFET for different drainbias (A) and of a point-TFET for different source compositions [12] (B).

44 P.G.D. Agopian et al. / Solid-State Electronics 128 (2017) 43–47

junction makes the total tunneling proportional to the L �Wdimensions.

Fig. 2 presents the transfer characteristic normalized by thechannel width of a single Line-TFET for different drain bias (A)and for point-TFETs with different source composition (B) as afunction of gate voltage. From Fig. 2, it is possible to observe thatLine-TFETs (2A) reaches a higher on-state current than point-TFETs (2B), considering the same channel width. This ON-currentimprovement, promoted by the Line-TFET structure, is a result ofthe alignment of the electric field with the tunneling direction thatin turns, results in a strong energy band bending, increasing theband-to-band current. It is also possible to observe from theLine-TFET transfer characteristics (Fig. 2A) that the smaller thedrain bias (VDS), the steeper the drain current (IDS) in the sub-threshold region due to the off current reduction. The SS improve-ment becomes even more pronounced with increasing gate lengthand consequently the tunneling area as reported in [6].

Besides the high on state current, when the output characteris-tic is evaluated (Fig. 3), the line-TFET also presents a good plateauin the saturation like region, showing to be a promising device for

0.0 0.5 1.0 1.510-15

10-13

10-11

10-9

10-7

0.0 0.5 1.0 1.50.0

0.1

0.2

0.3

VGS=1.5VVGS=1.2V

VGS=0.9V

I DS (A

)

VDS (V)

VGS=0.6VL=1um, W=110nm

VGS=1.5V

VGS=1.2V

I DS (A

)

VDS (V)

Fig. 3. Experimental output characteristic of a Line-TFET for different gate bias.

P.G.D. Agopian et al. / Solid-State Electronics 128 (2017) 43–47 45

analog applications, as was already reported for point-TFETs [7,8].However, at low gate bias, it is clear that the saturation like regiondoes not present a plateau, i.e., the output characteristic isdegraded and becomes inappropriate for this kind of application.Since the drain current level changes several orders of magnitudewith the gate bias increase, the drain current was also plotted ina linear scale (inset), in order to better observe the plateau region,confirming the aforementioned.

Considering that the intrinsic voltage gain (AV) is one of themost important figures of merit for analog applications and itcan be calculated by the transconductance (gm) over output con-ductance (gD) ratio, these parameters were evaluated for differentbias, channel lengths and channel widths, aiming to optimize theLine-TFET AV performance.

The gm and gD analysis were performed for different channellengths and different channel widths in order to select the bestcombination of the transistor dimensions to optimize the AV valueas can be seen in Fig. 4.

From Fig. 4A, it is possible to notice that although gm increaseswith the gate bias due to the higher overlap between bands, simi-larly as occurs for point-TFETs, when the comparison between lineand point TFETs focus on the gm dependence with channel length,the line-TFETs presents a direct dependence on L, while pointdevices usually are independent on it. The higher gm for longerchannel length occurs due to the larger tunneling junction areaunderneath the gate as shown in Fig. 4 (source/Si pocket).

0.6 0.8 1.0 1.2 1.4 1.6 1.810-11

10-10

10-9

10-8

10-7

10-6

10-5

VDS

(V)

gm (S

)

VGS

(V)

L=130nm L=1 m

gD (S)

W=110nm

A

0.75 1.00 1.25 1.50

10-11

10-10

10-9

10-8

10-7

10-6

10-5

0.6 0.8 1.0 1.2 1.4 1.610-8

10-7

10-6

10-5

W=110nm W=130nm W=200nm

VDS (V)

gm (S

)

B

VGS=1.5V L=1 m

10-9

10-8

10-7

10-6

10-5

gD (S)

Fig. 4. Transconductance (Left/Bottom axis) and output conductance (Right/Topaxis) for different channel lengths (A) and for different channel widths as a functionof VDS (B).

However, evaluating the gD values, a smaller gate length depen-dence is observed. Besides this, as VDS increases, the TFET devicesoperate more in the ‘‘saturation like” region, resulting in a better(smaller) gD.

The dependence of these two parameters (gD and gm) on chan-nel width (W) were also evaluated for high VGS (1.5 V) as a functionof drain bias (Fig. 4B). Although the drain bias does almost notaffect the transconductance, it increases with the channel width,as expected, due to the junction area increase. Focusing on outputconductance (gD), it was observed that it depends on both the drainbias and the channel width, but in the opposite way. While thehigher drain bias contributes to the gD improvement (the TFEToperates more in the ‘‘saturation like” region), the drain currentincreases with channel width resulting in a gD degradation(increase).

Keeping in mind that the transconductance presented a signifi-cant improvement for longer channel device, while the variationon output conductance is not so important, the obtained intrinsicvoltage gain (AV) for longer devices was higher than the shorterone. Fig. 5 shows the experimental AV for long line-TFETs(L = 1 lm) with different channel widths operating at differentdrain bias. From Fig. 5 it is possible to observe that the output char-acteristic improvement associated with a VDS increase leads to anoptimization of the bias operation point for the analog perfor-mance of all Line-TFETs. However, when the channel width (W)was evaluated, the response of a transistor with W of 130 nm,shows a reduction of two times on transconductance and a strongreduction on gD compared with their counterpart withW = 200 nm, that in turns, results in a best AV value for deviceswith W = 130 nm and L = 1 lm.

Since the line-TFET with W = 130 nm and L = 1 lm shows to beslightly better and the best bias condition was defined above forthe line-TFET architecture and it was already performed forTFET-FinFET and GAA-FinFET architectures in [7,8], respectively,from now on, their analog performance is compared among thesethree different architectures. Besides this analysis, a comparisonof this planar Line-TFET was also performed for different technolo-gies (MOS and TFET).

The first comparison, shown in Fig. 6, is focused on gm and gD ofthese three different architectures. Comparing the TFETs fabricatedin a planar (line) and FinFET structure (Fig. 6A) it is possible to seethat both transconductance and output conductance obtained forplanar devices are very high because the line TFETs becomes tobe dominated by the earlier start of the Band-to-band tunnelingphenomena. However, considering the vertical GAA structure

0.6 0.8 1.0 1.2 1.4 1.60

20

40

60

80

100

AV (d

B)

VDS (V)

VGS=1.5V L=1 m W=110nm

W=130nm W=200nm

Line-TFET

Fig. 5. Experimental AV for Line-TFETs for different VDS and channel widths atVGS = 1.5 V.

Line-TFET FinFET-TFET10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

VGS=1.7V

VGS=1.7V

gm (S) and g

D (S)gm (S

) and

gD (S

)

gmgd

VDS=0.9V

Line-TFET GAA-TFET (Ge27%)10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

VDS=1.5V

Fig. 6. Experimental comparison of gm and gD at optimum point for differentarchitectures: Line-TFET � FinFET (A) and Line-TFET � GAA-TFET (B). 25 50 75 100 125 150

15

30

45

60

75 GAA-MOSFET Line- TFET GAA-TFET , Si source GAA-TFET , Si Ge (27%) source

AV (d

B)

Temperature (oC)

VDS=1.5VVGS=1.7V

Fig. 8. Experimental comparison of AV as a function of temperature among Line-TFET, GAA-TFET (with different source compositions) and GAA-MOSFET, for GAA-TFET optimal bias point (VGS = 1.7 V and VDS = 1.5 V).

46 P.G.D. Agopian et al. / Solid-State Electronics 128 (2017) 43–47

(Fig. 6B), only the transconductance stands out due to itsimprovement.

Making the analog evaluation for different temperatures (fromroom to 150 �C), the AV performance among the planar Line-TFETand transistors fabricated with the FinFET structure (tunnel-FETand MOSFET), shows a smaller AV for Line-TFETs than for the TFETwith the FinFET structure (Fig. 7). It occurs because line-TFETs aremore dependent of BTBT and as a consequence a higher gD wasobtained.

However, when line-TFETs are compared with the conventionalFinFETs (MOSFET technology), the AV of Line-TFETs is at least 30 dBhigher for all temperatures because the BTBT tunneling current isless dependent of VDS than the drift current.

Considering the gate-all around transistors, like nanowiredevices, it is well known that for smaller diameter, the couplingbetween gate and channel is higher, resulting in a predominanceof BTBT rate along all the source/channel junction area [13]. As aconsequence it can be obtained a better subthreshold swing behav-ior, higher gm and consequently higher transistor efficiency (gm/IDS) at weak conduction regime as reported by [14], whichincreases the intrinsic voltage gain increases only in this operationregion. However, transistors with higher diameter is more TATdependent (less BTBT dependence), which degrades the weakinversion, but it is less drain voltage dependent, resulting in a bet-ter output conductance, Early voltage and consequently the intrin-sic voltage gain at strong conduction as already reported in [7,8].

Focusing on the performance of intrinsic voltage gain in thestrong conduction regime, the same analog comparison was per-

25 50 75 100 125 1500

15

30

45

60

75

90 VDS=0.9VVGS=1.7V

Line-TFET FinFET - TFET FinFET - MOSFET

Temperature (oC)

AV (d

B) =24dB

=30dB

Fig. 7. Experimental comparison of AV as a function of temperature among Line-TFET, FinFET-TFET and FinFET MOSFET, for FinFET-TFET optimal bias point(VGS = 1.7 V and VDS = 0.9 V).

formed, but now considering Line-TFETs and vertical GAA struc-tures (Si-MOSFETs and TFETs with Si and Si0.73Ge0.27 sources) ascan be seen in Fig. 8. Since the line-TFETs reaches a higher BTBTcurrent while GAA structures are more TAT dependent, the GAA-TFETs present higher AV values than the Line TFETs, independenton the source composition.

However when the Line-TFET is compared with a GAA MOSFET,the Line TFET seems to be better again.

Although Line-TFETs do not reach AV values as high as for GAA-TFETs and Fin-TFETs, when a high on-state current is required, theplanar Line-TFET can be considered as an alternative, since itreaches on-state currents much higher than the other TFET struc-tures studied in this paper.

4. Conclusion

This paper presents an analysis of the intrinsic voltage gain ofLine-TFETs and makes a comparison with devices fabricated withvertical GAA and FinFET structures for both TFET andMOSFET tech-nologies. The results show that this planar line-TFET architecturedoes not present the highest AV values when compared with thetwo other vertical TFET architectures (FinFET-TFET and GAA-TFET), however it reaches a very high on-state current, which tillnow was a road block for another TFET structures. Therefore it ispossible to conclude that Line-TFETs can be a good alternative toreplace MOSFETs since it reaches the highest on-state currentsand a better intrinsic voltage gain than the advanced MOSFETarchitectures (at least 30 dB higher than FinFETs and 10 dB higherwhen compared with GAA-MOSFETs).

Acknowledgments

The authors would like to thank CNPq and FAPESP for the finan-cial support during the execution of this work. Part of the work hasbeen performed within the frame of imec’s Core Partner programon Logic Devices.

References

[1] Ionescu AM, Riel H. Tunnel field-effect transistors as energy-efficientelectronics switches. Nature 2011;479:329–37.

[2] Verhulst A et al. Complementary silicon-based heterostructure tunnel-FETswith high tunnel rates. IEEE Electron Dev Lett 2008;29(12):1398–401.

[3] Nah J et al. Ge-SixGe1-x core-shell nanowire tunneling field-effect transistors.IEEE Trans Electron Dev 2010;57(8):1883–8.









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[4] Verreck D et al. Quantum mechanical performance predictions of p-n-i-nversus pocketed line tunnel field-effect transistors. IEEE Trans Electron Dev2013;60(7):2128–34.

[5] Schmidt M et al. Line and point tunneling in scaled Si/SiGe heterostructureTFETs. IEEE Electron Dev Lett 2014;35(7):699–701.

[6] Walke AM et al. Fabrication and analysis of a Si/Si0.55Ge0.45 heterojunction linetunnel FET. IEEE Trans Electron Dev 2014;61(3):707–15.

[7] Agopian PGD et al. Experimental comparison between trigate p-TFET and p-FinFET analog performance as a function of temperature. IEEE Trans ElectronDev 2013;60:2493–7.

[8] Agopian PGD et al. Influence of the source composition on the analogperformance parameters of vertical nanowire-TFETs. IEEE Trans Electron Dev2015;62:16–22.

[9] Zhao Q-T et al. Strained Si and SiGe nanowire tunnel FETs for logic and analogapplications. J Electron Dev Soc 2015;3(3):103–14.

[10] Sedighi B et al. IEEE Trans Circ Syst-I: Regular Pap 2015;62(1).[11] Agopian PGD et al. Comparison between vertical silicon NW-TFET and NW-

MOSFET from analog point of view. EuroSOI-ULIS 2015:233.[12] Martino JA et al. The impact of the Ge concentration in the source for vertical

tunnel-FETs. ECS Trans 2015;66(4):79–86. doi: http://dx.doi.org/10.1149/06604.0079ecst.

[13] Sivieri VB, Agopian PGD, Martino JA. Impact of diameter on TFET conductionmechanisms. In: 30th Symposium on microelectronics technology and devices(SBMicro). p. 1–4. doi: http://dx.doi.org/10.1109/SBMicro.2015.7298146.

[14] Schulte-Braucks C et al. Experimental demonstration of improved analogdevice performance in GAA-NW-TFETs. In: 44th European Solid State DeviceResearch Conference (ESSDERC). p. 178–81. 10.1109/ESSDERC.2014.6948789.





















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Confinement orientation effects in S/D tunneling


⇑ Corresponding author at: Nanoelectronics Research Group, Departamento deElectrónica, Universidad de Granada, Campus Fuentenueva S/N, 18071 Granada,Spain.

E-mail address: [email protected] (C. Medina-Bailon).

C. Medina-Bailon ⇑, C. Sampedro, F. Gámiz, A. Godoy, L. DonettiNanoelectronics Research Group, Departamento de Electrónica, Universidad de Granada, Campus Fuentenueva S/N, 18071 Granada, SpainCITIC Universidad de Granada, 18071 Granada, Spain




The most extensive research of scaled electronic devices involves the inclusion of quantum effects in thetransport direction as transistor dimensions approach nanometer scales. Moreover, it is necessary tostudy how these mechanisms affect different transistor architectures to determine which one can bethe best candidate to implement future nodes. This work implements Source-to-Drain Tunneling mech-anism (S/D tunneling) in a Multi-Subband Ensemble Monte Carlo (MS-EMC) simulator showing the mod-ification in the distribution of the electrons in the subbands, and, consequently, in the potential profiledue to different confinement direction between DGSOIs and FinFETs.


1. Introduction

The study of alternative technical approaches for electronicdevices is necessary to fulfill the requirements of power consump-tion, delay time and scalability demanded by ITRS [1]. Currently,there are two main work trends on the simulation of semiconduc-tor processes and devices. The first one is the study of quantumeffects in the nanometric dimensions of the conventional devices.The second one is mainly focused on novel engineering solutionsto create improved device architectures.

The inclusion of quantum effects in the transport direction ismandatory when the dimensions of the electronic devices arereduced. In particular, Source-to-Drain tunneling (S/D tunneling)allows electrons to go through the potential barrier instead ofrebound from it. When this quantum effect is taken into account,the height of the potential barrier is modified increasing the sub-threshold current. Moreover, this phenomenon introduces noisebecause the number of affected electrons has a random nature. Aballistic non-equilibrium Green’s Function (NEGF) approach hasdemonstrated that S/D tunneling is a scaling limit due to the rea-sons mentioned above [2]. In addition, it will distort the MOSFEToperation at transistor channel lengths around 3 nm [3]. Thisphenomenon is of special interest when the operation regime isnear-threshold because the leakage current increases and Vth

decreases [4].At the same time, different technological architectures are pro-

posed to overcome the limitations of conventional planar devices

[5,6]. For this reason, new transistor architectures based on multi-ple gates [7] are replacing standard technology as a way to keepshort channel effects (SCEs) under control. Furthermore, theincreased electrostatic confinement provided by multiple gatesrelaxes the manufacturing constraints in comparison to conven-tional planar devices. For example, a channel thickness (TSi) isrequired to be one fourth of the channel length to guaranteeacceptable short-channel effects in SOI technology. However,extremely thinner TSi can represent a critical parameter in the fab-rication of electronic devices as they are scaling down. This criticalTSi of a double gate transistor is approximately twice as wide as TSi

of a single-gate device with the same short-channel properties. Ittherefore alleviates the fabrication problem. If we consider a dou-ble gate device, these gates can be oriented horizontally, Double-Gate Silicon-On-Insulator (DGSOIs), or vertically, FinFETs. Ideally,both channels are activated simultaneously and feature identicalcharacteristics. The gates are parallel to the standard wafer orien-tation for DGSOIs whereas they are perpendicular in FinFETs asdepicted in Fig. 1. It should be highlighted that the FinFET is a 3Dstructure whereas our MS-EMC simulator makes use of a 2Ddescription. However, it was demonstrated that FinFETs with abig enough aspect ratio show similar behavior in all transportregimes when 2DMS-EMC, which consider infinite fin height, andother 3D codes are used [8].

This work presents a meticulous comparison between DGSOIsand FinFETs by means of a Multi-Subband Ensemble Monte Carlo(MS-EMC) simulator when S/D tunneling mechanism is taken intoaccount. It will be shown the influence of the orientation on theS/D tunneling and, consequently, on the device characteristics.

The outline of this work is as follows. Section 2 gives an over-view of the code developed to carry out our research, where the







Fig. 1. DGSOI and FinFET structures analyzed in this work. 1D Schrödinger equation is solved for each grid point in the transport direction and BTE is solved by the MCmethod in the transport plane.

Table 1Effective mass in silicon for DGSOI and FinFET devices studied in this work where mx

is the transport mass and mz is the confinement mass.

Device Valley mx my mz

DGSOI D2 mt mt ml

(100)h011i D4 2mlmtmlþmt

mlþmt2

mt

FinFET D2 mt ml mt

(0 �11)h011i D4mlþmt

2mt 2mlmt

mlþmt

C. Medina-Bailon et al. / Solid-State Electronics 128 (2017) 48–53 49

starting point simulation frame and the S/D tunneling algorithmare accurately described. Subsequently, the results and discussionsare summarized in Section 3. Finally, the conclusions of this paperare summed up in Section 4.

2. Simulation set-up

Our MS-EMC simulator is based on the mode-space approach ofquantum transport [9]. The device structure is divided into slicesalong the confinement direction where the 1D Schrödinger equa-tion is solved, whereas the 2D Boltzmann Transport Equation(BTE) is solved in the transport plane as showed in Fig. 1. Bothequations are coupled to the 2D Poisson equation to keep theself-consistency of the solution. This simulator has already demon-strated its capabilities studying different advanced nanodevices[10–13]. The main advantage of this tool against NEGF approachis the reasonable computational time when scattering mechanismsand quantum effects on the ultrascaled devices are taken intoaccount.

In addition, the fundamentals of the free-flight technique of anelectron used in Monte Carlo algorithms are based on the stochas-tic and ergodicity processes. It calculates the positions of each elec-tron in the transport direction after a random flight time whichfinishes because of the random choice of a scattering event. Aftereach flight, the new position and transport properties of the elec-trons are calculated. Depending on the carrier location and energy,our algorithm estimates the probability of undergoing a tunnelprocess. For this reason, another advantage of the MS-EMC simula-tor is the ability to switch on and off the tunneling process as it isincluded in a separate routine after each iteration.

The model employed here to include the S/D tunneling is anextension of the non-local band-to-band tunneling (BTBT) algo-rithm [14]. In that work, the same classical path and tunnelingprobability were considered, whereas the starting and ending pointin the tunneling path belong to Valence and Conduction Band,respectively. The main advantage of this method is that, once it

has been implemented in the simulator, it is possible to extend itfrom the study of BTBT to that of S/D tunneling because thedescription of both mechanisms is based on the same assumptions.

In this work, the performance of DGSOI and FinFET devices isanalyzed when S/D tunneling is included in order to determine itsimpact. The considered confinement direction of these devices onstandard wafers changes between (100) for planar DGSOIs and(0 �11) for vertical FinFETs, and h011i for the transport directionas depicted in Fig. 1. The differences in the confinement directionmodify the electron distribution in the subbands, and, conse-quently, the potential profile. The carrier transport effective massis alsomodified [15]. Table 1 summarizes the masses of each deviceand Table 2 shows their numerical values.Whereml ¼ 0:916m0 andmt ¼ 0:198m0 are the longitudinal and transversal effective massesin silicon, respectively,m0 is the electron free-mass,mx is the trans-port mass,mz is the confinement mass, and D2 and D4 represent thedegeneration factors of each valley. Moreover, the lower energysubband changes from D2 in DGSOI to D4 in FinFET.

These devices have been parametrized for gate lengths rangingfrom 5 nm to 20 nm. The rest of the technological parametersremains constant, channel thickness TSi = 3 nm, gate oxide withEquivalent Oxide Thickness EOT = 1 nm and metal gate work func-tion of 4.385 eV.

The position and energy of each electron are calculated aftereach free-flight as described above. In a semiclassical approxima-tion, if the total energy of this electron is lower than the potential

Table 2Numerical values of effective mass in silicon for DGSOI and FinFET devices studied inthis work where mx is the transport mass and mz is the confinement mass.

Device Valley mx my mz

DGSOI D2 0:198 0:198 0:916(100)h011i D4 0:326 0:557 0:198

FinFET D2 0:198 0:916 0:198(0 �11)h011i D4 0:557 0:198 0:326

Fig. 3. Energy profile of the lowest energy subband in the 10 nm device for DGSOI(valley D2) and FinFET (valley D4) with and w/o S/D tunneling with VGS ¼ 0:6 V andVDS ¼ 100 mV.

50 C. Medina-Bailon et al. / Solid-State Electronics 128 (2017) 48–53

barrier at this position, the electron must undergo a backscattering.When S/D tunneling is taken into account, there is a probability forthe electron to go through the barrier. There are two steps to deter-mine that probability at a specific energy.

Firstly, the tunneling probability of the electron Tdt is calculatedusing the WKB approximation [16]:

TdtðEÞ ¼ exp �2�h

Z b

a

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

2m�trðEiðxÞ � EÞ

p

dx

( )

ð1Þ

where a and b are the starting and ending points, E and m�tr are the

energy and transport effective masses of the electron, respectively,and EiðxÞ the energy of the i-th subband. This approximation hasalready been used to study this phenomenon in other electrondevices [17]. Our MSB-EMC simulator offers a detailed descriptionof the subband structure. Consequently, Tdt has been calculatedfor each electron keeping in mind the minimum energy of its sub-band instead of the Conduction Band [18].

Fig. 2. Representation of the tunneling model: the potential barrier (a) is inverted andNewton’s second law of motion (c) until it reaches the ending point b (d).

In that point, several assumptions have been considered aftereach integration step to enhance the calculation of Tdt and toreduce the computational effort. The exact starting and endingpoints in the tunneling path are calculated to evaluate Tdt . In addi-tion, a maximum tunneling rejection length is also introduced(Lmax). If the tunneling length of an electron from the starting pointto a specific integration step is higher than Lmax, the calculation of

the particle is placed at the starting point a (b), it follows a classical path obeying


Tdt stops. Lmax has been chosen herein at Lmax = 10 nm because Tdt

decreases substantially for higher lengths. It remains constantregardless of the channel length.

Secondly, a rejection technique is used to determine whetherthe particle will tunnel or not. A uniform distributed random num-ber rdt is generated and compared to Tdt . On the one hand, ifrdt > Tdt , the electron will turn back with vx ¼ �vx. On the otherhand, if rdt 6 Tdt , the electron will go through the barrier.

Subsequently, if the electron undergoes a tunnel process, it isrequired to find the most probable tunneling path to completelydetermine its new position. The motion inside the barrier obeysNewton mechanics considering an inverted potential profile andballistic transport [19]. This classical trajectory could be found bythe following steps [4] as shown in Fig. 2. Firstly, a pseudo-particle is placed at the starting point a with zero kinetic energy(Fig. 2(b)). It is assumed that this particle is going to exit the barrier

Fig. 4. Average effective mass of the electron distribution with the lower energysubband of the valley D2 (solid) and of the valley D4 (dashed) as a function of thetotal energy and the total population in the 10 nm device including S/D tunnelingfor DGSOI (top) and FinFET (bottom) with VGS ¼ 0:6 V and VDS ¼ 100 mV.

with the same transport properties. Consequently, its flightdirection is maintained before starting its motion. It is also markedto force a ballistic transport inside the barrier. Then, it acceleratesin this system according to Newton’s second law of motion (Fig. 2(c)):

a! ¼ qn

m�tr

ð2Þ

where n is the electric field. Lastly, it reaches the ending point b(Fig. 2(d)). Thereafter, the particle recovers its transport properties.


A set of simulations at low bias condition has been performed todetermine the importance of S/D tunneling on each device. Themodifications in the energy profile of the lower energy subbandsand the carrier transport effective mass caused by the differencein the confinement directions are shown in Figs. 3 and 4, respec-

Fig. 5. Electron distribution in arbitrary units in the lower energy subband as afunction of total energy in the 10 nm device including S/D tunneling for DGSOI (top)and FinFET (bottom) with VGS ¼ 0:6 V and VDS ¼ 100 mV.

52 C. Medina-Bailon et al. / Solid-State Electronics 128 (2017) 48–53

tively. Both devices present similar energy profiles but the lowerenergy subband changes from D2 in DGSOIs to D4 in FinFETs(Fig. 3). This change modifies the distribution of the populationand the effective transport mass in the subbands. Moreover,Fig. 3 shows the increase of the potential barrier when S/D tunnel-ing is considered because of the existence of electrons locatedinside the potential barrier.

The average effective transport mass of the electrons as a func-tion of the total energy and the total population which undergoesthis tunnel process is higher in the FinFET than in the DGSOI asdepicted in Fig. 4. These values correspond to mx of the fundamen-tal valleys in Table 2. It is also represented in Fig. 4 the lowerenergy profile of the less populated valleys: D2 in FinFET, and D4

in DGSOI. The average effective mass in these non-fundamentalsubbands decreases for the FinFET whereas it increases for theDGSOI. Despite this, the average effective mass continues beinghigher for the less populated valley in FinFET than in DGSOI.

As a result, assuming similar energy profile (Fig. 3), whichmeans similar tunneling length at a specific starting point a, thehigher is the value of m�

tr in the fundamental valley in Eq. (1) forthe FinFET orientation, the smaller is Tdt . Besides, the value of m�

tr

in the non-fundamental valley is higher in the DGSOI than in theFinFET, whereas the energy profile remains constant between both

Fig. 6. Percentage of electrons near the potential barrier affected by S/D tunnelingrespect to the total number of electron with lower energy than the top of the barrierin the same region as a function of LG at low drain bias for DGSOI (top) and forFinFET (bottom).

valleys. However, the reduction of the population in this valleydecreases the number of particles involved in S/D tunneling. Forthese reasons, the FinFET reduces its effectiveness of the tunnelphenomenon compared to the DGSOI one.

The higher Tdt , the higher the probability of an electron under-going S/D tunneling for the same energy. It therefore increases thenumber of particles affected by S/D tunneling for the DGSOI thanfor the FinFET. This effect is shown in Fig. 5 where the electron dis-tribution in arbitrary units from the fundamental subband as afunction of total energy is represented.

Electrons with reduced energy must go through longer tunnel-ing paths. When its length is similar to 10 nm, which correspondsto LG in Fig. 5, the population decreases substantially. That is thereason why the maximum tunneling rejection length has been cho-sen at 10 nm.

The same effect is also shown in the percentage of electronsnear the potential barrier affected by S/D tunneling respect tothe total number of electron with lower energy than the top ofthe barrier in the same region, which is higher for DGSOI(Fig. 6 top) than for FinFET (Fig. 6 bottom). In addition, there is amaximum of this percentage for the FinFET due to a reduced heightof the potential barrier. When VGS increases, the height of thepotential barrier decreases causing the enhancement of the ther-mionic current. It therefore induces the reduction of the numberof electrons near the potential barrier with lower energy. It is nec-essary to highlight that the change in the channel length modifies

Fig. 7. ID vs. VGS as a function of LG at low drain bias with and w/o considering S/Dtunneling for DGSOI (top) and FinFET (bottom).

Fig. 9. Difference between the threshold voltage (DVth) of a simulation consideringS/D tunneling and w/o taking it into account as a function of LG for DGSOIs andFinFETs at low drain bias condition and TSi ¼ 3 nm.

Fig. 8. Threshold voltage (Vth) for FinFETs and DGSOIs as a function of LG at low biascondition and TSi ¼ 3 nm with and w/o considering S/D tunneling.


the tunneling length and, consequently, Tdt . For this reason, thenumber of particles that suffer S/D tunneling increases when thedevices are scaling down. By way of contrast, the maximum per-centage appears in DGSOI devices but it is shifted to higher gatevoltages (not shown).

This quantum effect produces a noticeable modification of theID � VGS characteristics (Fig. 7). Despite the increase of the poten-tial barrier when S/D tunneling is included (Fig. 3), a higher currentlevel is observed. The number of electrons that flows from sourceto drain is higher because of the possibility of tunneling throughthe barrier. This increase is also exacerbated when the devicesare scaled down. As it is shown, the influence of the S/D tunnelingis lower in the FinFET (Fig. 7 bottom) compared to DGSOI (Fig. 7top).

The inclusion of tunneling introduces an important reduction inthe threshold voltage (Vth) as it is shown in Fig. 8. Due to thereduced number of particles affected by this phenomenon in theFinFET compared to the DGSOI, the shift of the Vth is smaller inthe vertical device than in the horizontal one. This effect is ampli-fied in both devices as the channel length is reduced.

The impact of the S/D tunneling on the electrostatics can beobserved in Fig. 9 where the threshold voltage variation (DVth)between a simulation with and without taking it into account is

shown. This difference is also aggravated for reduced LG becausethe influence of this quantum effect in the electrostatics is lowerin the FinFET.

4. Conclusions

This work presents the implementation of S/D tunneling in aMSB-EMC simulator for the study of its impact in DGSOIs and Fin-FETs. Our simulations show important differences fully caused bythe change in the confinement directions in both DGSOIs and Fin-FETs when S/D tunneling is taken into account due to the electrondistribution and the variation of transport effective mass. Never-theless, FinFET devices show less degradation in their subthresholdcharacteristics, and therefore are better candidates to implementfuture nodes, especially for ultra-low power applications.

Acknowledgment

The authors are grateful for the support given by the SpanishMinistry of Science and Innovation (TEC2014-59730-R), H2020 -REMINDER (687931), and H2020 - WAYTOGO-FAST (662175).

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http://dx.doi.org/10.1063/1.1845586














Process modules for GeSn nanoelectronics with high Sn-contents


⇑ Corresponding author.E-mail address: [email protected] (C. Schulte-Braucks).

C. Schulte-Braucks a,⇑, S. Glass a, E. Hofmann a, D. Stange a, N. von den Driesch a, J.M. Hartmann b,c,Z. Ikonic d, Q.T. Zhao a, D. Buca a, S. Mantl a

a Peter-Gruenberg-Institute 9 (PGI-9) and JARA-FIT, Forschungszentrum Juelich GmbH, 52428 Juelich, GermanybUniversity of Grenobles Alpes, F38000, FrancecCEA, LETI, MINATEC Campus, F-38054 Grenoble, Franced Institute of Microwaves and Photonics, School of Electronic and Electrical Engineering, University of Leeds, LS2 9JT Leeds, United Kingdom




Keywords:GeSnMOSFETHigh-k/metal gateNiGeSn

This paper systematically studies GeSn n-FETs, from individual process modules to a complete device.High-k gate stacks and NiGeSn metallic contacts for source and drain are characterized in independentexperiments. To study both direct and indirect bandgap semiconductors, a range of 0–14.5 at.%Sn-content GeSn alloys are investigated. Special emphasis is placed on capacitance-voltage (C-V)characteristics and Schottky-barrier optimization. GeSn n-FET devices are presented includingtemperature dependent I-V characteristics. Finally, as an important step towards implementing GeSnin tunnel-FETs, negative differential resistance in Ge0.87Sn0.13 tunnel-diodes is demonstrated at cryogenictemperatures. The present work provides a base for further optimization of GeSn FETs and novel tunnelFET devices.


1. Introduction

Recently, GeSn alloys have emerged as promising group IVsemiconductors for electronic [1] as well as photonic [2,3] applica-tions. The breakthrough in epitaxial growth of high-Sn content andstrain relaxed layers, enabled fundamental direct bandgap groupIV alloys grown on Si [4,5]. The direct bandgap property is arequirement for efficient Si based light emitters. However, suchalloys may also serve as performance boosters in nanoelectronics.The small effective mass and associated reduction of intra-valleyscattering yields high mobility C-electrons. Performance of GeSnbased n-type Metal Oxide Semiconductor Field Effect Transistors(MOSFETs) should then be superior to those of their pure Gecounterparts. In addition, the possibility of combining directband-to-band tunneling and low bandgap should yield efficienttunnel field effect transistors (TFETs).

Mobility calculations, using the 8-band k.p method for theC-valley band structure and effective mass (including nonparabol-icity) for the L-valley band structure, predict a significant mobilityenhancement as soon as the population of C-valley is sufficientlylarge. The calculations take acoustic phonon, deformationpotential, alloy disorder, ionized impurity, and inter-valleyscattering into account. Modulation of the U-valley population

can be achieved either by changing Sn-content or layer strain.For Sn contents below �9 at.% GeSn alloys are indirect bandgapsemiconductors. Hence, the electron mobility is dominated byelectrons occupying the L-valley. For larger Sn contents, abovethe indirect to direct bandgap transition, the C-valley becomesincreasingly populated and the electron mobility is boosted signif-icantly. The calculated Sn-dependent C-valley population andeffective (weighted-average) mobility is shown in Fig. 1(a). GeSnpseudomorphically grown on Ge is Sn-content dependently biaxi-ally compressively strained. However, growing thicker GeSn layersleads to strain relaxation or even tensilely strained GeSn whencombining different Sn-contents [6,7]. Decreasing compressivestrain has the same effect as increasing Sn content, leading to anincrease of U-valley population and of U-electron mobility accord-ing to Fig. 1(b). In contrast, L-electron mobility is of the order of4 � 103 cm2/V s for all Sn-contents and strain values presentedhere. The large difference between U- and L-electron mobilitycomes from a much larger effective mass of the L-electrons. How-ever, just above the indirect to direct transition, the U-electronmobility is still limited by strong inter-valley U-L scattering, whichgives a large relative contribution to total scattering due to a largeL-valley density of states (while the L-electrons are less affected,because of a smaller density of states of C). Together with a smallfraction of C-electrons, this implies that in alloys with 8.5 at.% Sn,at the direct to indirect transition, the mobility is always domi-nated by the L-electrons. However, when U-L spacing increases,







Fig. 1. (a) Calculated C-valley population (top) and effective electron mobility, at 300 K and 1014 cm�3 electron density, vs Sn-content (bottom) at zero strain. (b) U and (c)effective electron mobilities for various GeSn alloys, dependent on biaxial strain.

C. Schulte-Braucks et al. / Solid-State Electronics 128 (2017) 54–59 55

by decreasing strain or increasing Sn-content, inter-valley scatter-ing is reduced, and C-population becomes significant. Conse-quently, not only the U-electron mobility but also the effectiveelectron mobility, displayed in Fig. 1(c), strongly increases. It is alsoworth noting that biaxial strain induces a non-negligible aniso-tropy of the C-valley, and in case of compressive strain the in-plane mobility, relevant for MOSFETs, is larger (by up to �20%)than perpendicular mobility.

Preliminary works on p- and n- MOSFETs [8,9] and even TFETs[10] based on GeSn alloys have been reported, however, the Sn-contents and strain values were far below the indirect to directtransition. The low solid solubility of Sn in Ge < 1 at.% and thenon-equilibrium growth restricts the thermal budget to tempera-tures <350 �C for Sn-contents above 10 at.% making process inte-gration challenging.

In this work we discuss advances on low temperature processmodules for GeSn-FET devices with Sn-contents up to 13 at.%,including high-k/metal gate stack deposition and low resistivitymetallic NiGeSn contact formation. Emphasis is placed on the fab-rication and characterization of metal-semiconductor-metal(MSM) diodes for Schottky-barrier height (SBH) extraction andSchottky-barrier tuning by dopant segregation (DS). GeSn n-FETsare fabricated using these modules and, as a step towards noveldevices, p-i-n tunneling diode characterization is presented.

2. Experimental

Due to the low solid solubility of Sn in Ge (<1 at.%) growth con-ditions for GeSn with up to 13 at.% Sn are far from equilibrium. Anindustry compatible AIXTRON TRICENT RP-CVD epitaxial reactorwas employed to grow these layers on 200 mm Ge buffered Si(1 0 0) wafers [11]. All process temperatures were kept below350 �C in order to avoid Sn-diffusion and segregation. As a firstkey module, MOS-capacitors (MOScaps) with high-k/metal gatestacks on GeSn were investigated. After a wet HF-HCl surfacepreparation, 6 nm HfO2 high-k dielectric was deposited at lowtemperature by atomic layer deposition (ALD) followed by 40 nmsputter deposited TiN metallization both using 200 mm, industrycompatible reactors. MOScaps with Sn-contents between 0 at.%(Ge-substrate) and 12.5 at.% were fabricated. Standard CMOS tech-nology, such as photo lithography and reactive ion etching, wasused to define the structures. The fabrication ended with a lift-off process after the deposition of 150 nm Al for contacts followedby forming gas annealing at 300 �C. A set of Capacitance-Voltage(C-V) characteristics at different frequencies measured on

TiN/HfO2/Ge0.915Sn0.085 capacitors is shown in Fig. 2(a). The goodGeSn/HfO2 interface quality is evidenced by the small frequencydependent flat-band voltage shift and the small frequency disper-sion in accumulation. Typical for low bandgap semiconductors, theC-V curves feature a strong minority carrier inversion responseeven at high frequencies >100 kHz. As a consequence, a reliableextraction of the interface state density (Dit) using the conductionmethod at room temperature becomes difficult [12]. However, theminority carrier inversion response is reduced at lower tempera-tures. We have thus used the low temperature conductance methodas described in work by Nicollian and Brews [13] at T < 120 K toextract Dit values of 2 � 1012 cm�2 eV�1 at midgap for GeSn capac-itors with different Sn contents (Fig. 2(b)). A study focusing on theprocess development and characterization of ternary SiGeSn MOS-caps has been published recently [14].

A second fundamental module is contact formation. Metal-semiconductor-metal (MSM) diodes based on NiGeSn/GeSn Schot-tky contacts were fabricated using an oxide mask. After nativeoxide removal, 10 nm of Ni were deposited by sputter depositionand �23 nm NiGeSn was formed by rapid thermal annealing for10 s in N2/H2 forming gas atmosphere. Unreacted Ni was removedby sulfuric acid (96% aq.). The van-der-Pauw method [15] has beenused to measure the sheet resistance of the so formed NiGeSnfilms. The lowest sheet resistance was obtained by stano-germanidation at 325 �C [16]. The low-resistive NiGeSn-phasecould be maintained over the complete available Sn-content rangefrom 0 to 12.5 at.%. The sheet resistance of NiGeSn for several Sn-contents is shown in Fig. 3(d). Furthermore, a smooth NiGeSn/GeSninterface was obtained as shown by the cross-sectional Transmission-Electron-Microscopy (TEM) image in the inset of Fig. 3(d).

Current transport properties across a metal-semiconductor con-tact are determined by the Schottky-barrier. Previous studies haveinvestigated the electron Schottky-barrier on NiGeSn/Ge0.958Sn0.042

[17] and hole Schottky-barrier on NiGeSiSn/Ge0.86Si0.07Sn0.07 [18].Here, we determine the NiGeSn/GeSn hole Schottky-barrier fromMSM diodes with different contact areas and for several Sn-concentrations using the activation-energy method. The advantageof this method is that the electrically active contact area does notneed to be known, e.g. current crowding does not affect theSchottky-barrier extraction. The temperature dependent I-V char-acteristics were measured in a liquid nitrogen cooled cryostatunder high vacuum where the temperature range from 400 K to100 K is covered in 10 K incremental steps. From Arrhenius plotsof the current characteristics for different voltages (Fig. 3(a)) theSchottky-barrier height (SBH) was extracted. According to

Fig. 2. (a) CV-characteristics of TiN/6 nm HfO2/Ge0.915Sn0.085 MOScap for a set of frequencies. (b) Dit at midgap for several Sn-contents extracted at temperatures below 120 K.

Fig. 3. Investigation of NiGeSn Schottky-contacts. (a) Arrhenius plot of current characteristics for a 12.5 at.% Sn sample. The linear region is fitted and SBH is extracted fromthe slope. (b) SBH vs. applied bias from (a). The SBH for 0 V is extracted by linear extrapolation. (c) Extracted 0 V SBH for various Sn contents. (d) Sheet resistance of NiGeSnfabricated on several GeSn layers. The inset depicts a TEM micrograph of a NiGeSn/GeSn contact.

56 C. Schulte-Braucks et al. / Solid-State Electronics 128 (2017) 54–59

thermionic-emission-diffusion theory, the voltage dependent SBHcan be extracted from the slope s of the linear region in theln|I/T2| plot via

SBH ¼ �s � ke;

where k is Bolzmann’s constant and e the electron charge. Outsidethis linear region, the current is determined by the series resistance(high temperatures) or the shunt resistance (low temperatures).The primary source of the former is the GeSn resistivity while thelatter is impacted by parasitic currents. As the MSM diode consistsof two back-to-back Schottky diodes, the current corresponds to the

reverse bias I-V characteristic at all times. The magnitude of thecurrent is given by the lower Schottky-barrier – hole or electronbarrier – in undoped semiconductors. In our case the holeSchottky-barrier is observed, as the nominally intrinsic GeSn layersare actually p-type. The main reasons for the voltage dependence ofthe SBH observed in Fig. 3(b) are image force and static loweringdue to the applied voltage. By linearly extrapolating to 0 V theseeffects are suppressed and the hole Schottky-barrier is obtained.Fig. 3(c) shows the results for NiGeSn/GeSn Schottky contacts withSn contents of 0 at.%, 7 at.% and 12.5 at.%. Throughout the entire Sncontent range, the hole Schottky-barrier remains below 0.10 eV,making NiGeSn an ideal contact for p-type devices. However, this

Fig. 4. High-resolution TEM image of the NiGeSn/GeSn interface after BF2 implan-tation with 10 kV and 1 � 1015 cm�2 proving the good crystalline quality of theGeSn after NiGeSn-formation.


might imply very high Schottky-barriers for electrons leading tohigh S/D resistances for n-type GeSn and demanding further inves-tigation on n-type GeSn-contacts over a wide Sn-content range.

For a metal-semiconductor interface with high carrier concen-trations, the tunneling current component through the barrier isincreased, which reduces the experimentally observed SBH. Awell-known method to modify the SBH using this effect is dopantsegregation [19]. Dopants are implanted shallowly into the contactwindows before metallization. During the following stano-germanidation step the entire implanted region is consumed.Therefore, semiconductor quality is conserved as the damaged areais fully converted to stano-germanide. The high-crystalline qualitycan be seen in the high-resolution TEM-image in Fig. 4.

Due to the different solubility of dopants in metal and semicon-ductor the snow plough effect leads to dopant diffusion throughthe metallic region into the semiconductor at the interface. Thisresults in a sharp doping profile with a high dopant concentrationat the metal-semiconductor interface. The dopant segregationeffect in GeSn for both n- and p-type dopants is presented below.Phosphorous (P), arsenic (As) and boron (BF2) were implanted intoGeSn test-structures with a dose of 1 � 1015 cm�2 at energies of 7,

Fig. 5. SIMS-profiles of NiGeSn/GeSn contacts with 10 at.% Sn: For Phosphorous implantaand Boron (c) profiles. For higher sensitivity As and B are measured as GeAs and GeB.

13 and 10 keV, respectively. In GeSn, P and As act as n-typedopants, while B is a p-type dopant. The implanted region was thenconverted into NiGeSn as described above. Subsequently, dopingprofiles were measured by means of Time of Flight Secondary-Ion-Mass-Spectrometry (ToF-SIMS). Whereas there is no peak vis-ible in the doping profile for P, a snow plough effect is observed forboth As and B leading to a peak in the As/B-concentration at theNiGeSn/GeSn interface (Fig. 5). The differences in DS for then-type dopants As and P might be attributed to differences in sol-ubility and diffusion. Nonetheless, as DS is possible both for n- andp-type dopants, this effect can be used to modify the SBH.

In order to investigate the impact of DS, NiGeSn contacts werefabricated on in-situ phosphorus doped Ge0.875Sn0.125 (GeSn:P)with a 2.7 � 1018 cm�3 n-type carrier concentration. DS was thenperformed with As or B using the process described above. Sinceactivated As provides electrons in GeSn, DS increases the majoritycarrier concentration at the NiGeSn/GeSn:P interface. For p-type B,DS yields the opposite. An increase in majority carrier concentra-tion at the interface allows for a higher tunneling componentthrough the barrier. Consequently, the effective SBH observed bythe charge carriers is reduced. Fig. 6 shows I-V characteristics mea-sured from one NiGeSn contact to the next, for samples without DSor with As or B DS. As expected, the I-V curves become more andmore Ohmic when increasing the electron concentration at theNiGeSn/GeSn:P interface (e.g. by switching from B DS to no DS toAs DS samples).

Combining the above described process modules, GeSnn-MOSFETs were fabricated with Sn-contents of 0 at.%, 7 at.% and12.5 at.% using ion implanted source/drain (S/D) contacts afterforming a gate stack with TiN/HfO2. Transfer curves of Ge0.93Sn0.07

n-FETs for a series of temperatures are shown in Fig. 7.At room temperature, the device shows a low Ion/Ioff ratio while

a reduced on current at lower temperatures is due to the poor n+/pjunctions in the S/D regions. The limited process temperaturesused here in order to avoid Sn diffusion (max. 300 �C), was notenough to recrystallize the amorphized regions created by ionimplantation, leading to very poor junctions with low activationand high access resistances. This is even more critical for highSn-content devices, as shown in Fig. 8 at 80 K. Apart from theun-healed implantation damage, the unintentional backgrounddoping of GeSn increases with the Sn-content. Furthermore, thebandgap is decreased. Both factors lead to increased S/D-leakageand gate induced drain-leakage (GIDL) which is caused by band-to-band tunneling and increases exponentially with the reducedbandgap. This is also visible in the temperature dependence ofthe transfer characteristics in Fig. 7. The S/D leakage stronglydecreases for temperatures below 200 K. The solution for main-taining crystalline GeSn is the use of in-situ doping and selective

tion no segregation was observed (a), whereas there is a clear peak in the Arsenic (b)

Fig. 6. Impact of DS on n-type Ge0.875Sn0.125:P. As the n-type carrier concentrationat the NiGeSn/GeSn:P interface increases, the I-V characteristic becomes moreOhmic.

Fig. 7. Transfer characteristics of Ge0.93Sn0.07 n-FETs at different temperatures.

Fig. 8. Id/Ion ratio of GeSn n-FETs at 80 K for several Sn-contents.

Fig. 9. Temperature dependent I-V measurements of a Ge0.87Sn0.13 p-i-n diodeshowing clear NDR at cryogenic temperatures.

58 C. Schulte-Braucks et al. / Solid-State Electronics 128 (2017) 54–59

growth in the S/D region. The in-situ doping is discussed below interms of tunneling diodes.

As a demonstration of the potential of direct bandgap GeSn forband to band tunneling and the advantage of in-situ doping overion implantation, we have fabricated GeSn tunneling diodes as animportant step towards advanced GeSn based TFETs. We couldpush the Sn-content up to 13 at.% as a follow up to previous resultswith a stack of 9 at.% and 11 at.% [1] enabling an even lower band-gap and higher directness of the GeSn. As a proof of band-to-bandtunneling, negative differential resistance (NDR) is observed atcryogenic temperatures (Fig. 9), demonstrating a high doping levelof both p- and n-type dopants, which is essential for MOSFETs andTFETs. However, due to enhanced diffusion and trap assisted tun-neling (TAT) in this low-bandgap semiconductor, the NDR vanishesfor temperatures above 100 K. For forward bias > 0.1 V two distinctregions, separated by a kink in the slope of the I-V curve, are visi-ble. While the middle part of the curve 0.1 V < Vd < 0.3 V can beattributed to TAT, the diffusion current dominates for strong for-ward bias >0.3 V. We expect further improvements in the peak tovalley current ratio and a move towards room temperature NDRwith optimized doping profiles.

3. Conclusion

In this work, process module developments for GeSn FETs werepresented and assembled to for the fabrication of GeSn n-FETs. Awide range of Sn-contents was covered, allowing the study of bothindirect and direct bandgap GeSn alloys. TiN/HfO2/GeSn MOScaps,showing good C-V characteristics with Dit levels of 1012 eV�1cm�2,have been studied for use as gate stacks. NiGeSn is shown to havelow sheet resistances over the entire Sn-content range and verysmall Schottky barrier heights on p-GeSn. To further optimize theSchottky contacts, dopant segregation with both As and B, wasdemonstrated for NiGeSn contacts. In the case of n-GeSn, it isshown that As dopant segregation leads to increasingly Ohmic con-tact behavior. Due to the metastability of GeSn, junctions made byion implantation have proven to be challenging. A possible solutionis in-situ doping which reveals its potential in GeSn-tunnel diodeswith 13 at.% Sn where characteristic negative differential resis-tance is observed at cryogenic temperatures.

Acknowledgments

This research received funding from the EU FP7 projectE2SWITCH (619509) and the BMBF project UltraLowPow(16ES0060 K).


References

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http://dx.doi.org/10.1063/1.4927622

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http://dx.doi.org/10.1038/nphoton.2014.321

http://dx.doi.org/10.1038/nphoton.2014.321

http://dx.doi.org/10.1021/acsphotonics.5b00372

http://dx.doi.org/10.1063/1.4829360

http://dx.doi.org/10.1021/am5075248

http://dx.doi.org/10.1021/am5075248




http://dx.doi.org/10.1021/acs.chemmater.5b01327




http://dx.doi.org/10.1021/acsami.6b0242

http://dx.doi.org/10.1021/acsami.6b0242




http://dx.doi.org/10.1088/0268-1242/30/5/055003

http://dx.doi.org/10.1088/0268-1242/30/5/055003











http://dx.doi.org/10.1016/j.mseb.2008.09.037





Study of silicon n- and p-FET SOI nanowires concerning analogperformance down to 100 K


⇑ Corresponding author.E-mail address: [email protected] (B.C. Paz).

Bruna Cardoso Paz a,⇑, Mikaël Cassé b, Sylvain Barraud b, Gilles Reimbold b, Maud Vinet b, Olivier Faynot b,Marcelo Antonio Pavanello a

aDepartment of Electrical Engineering, Centro Universitário da FEI, São Bernardo do Campo, BrazilbDépartement des Composants Silicium – SCME/LCTE, CEA-LETI Minatec, Grenoble, France




Keywords:Analog performanceNanowiresFin width influenceTemperature influenceMobility

This work presents an analysis of the performance of silicon triple gate SOI nanowires aiming the inves-tigation of analog parameters for both long and short channel n-type and p-MOSFETs. Several nanowireswith fin width as narrow as 9.5 nm up to quasi-planar MOSFETs 10 lm-wide are analyzed. The fin widthinfluence on the analog parameters is studied for n-type and p-MOSFETs with channel lengths of 10 lmand 40 nm, at room temperature. The temperature influence is analyzed on the analog performance downto 100 K for long channel n-MOSFETs by comparing the quasi-planar device to the nanowire with finwidth of 14.5 nm. The intrinsic voltage gain, transconductance and output conductance are the mostimportant figures of merit in this work. An explicit correlation between these figures of merit and themobility behavior with temperature is demonstrated.


1. Introduction

Scaling plays an important role in the continuity of the CMOSroadmap. The reduction of the transistors dimensions broughtnew challenges to the semiconductor industry and the scientificcommunity. Problems related to the loss of control of the channelcharges appeared due to scaling and revealed to be crucial ondetermining the performance degradation of the devices. Theseundesirable effects known as short channel effects motivated thedevelopment of new architectures and technologies. Multiple gatefield effect transistors have been proposed to overcome such prob-lems and push the limits of scaling beyond those imposed by con-ventional planar devices [1].

Tridimensional structures characterized by semiconductorstripes surrounded by the gate have shown good electrostatic cou-pling and strong short channel effects immunity. By reducing thedimension of these stripes to a few nanometers, a new generationof devices called nanowires (NWs) has been evolved. Recently,many works have reported the excellent performance of NWs [2–4], showing their advantages for digital applications, associatingthem to others technologies such as strain and investigating differ-ent fabrication processes to enhance their performance. Moreover,other published works focus on the investigation of the transport

characteristics of NWs and their mobility dependence on temper-ature and semiconductor materials [5–7]. Concerning analog appli-cations, NWs performance are still nearly unexplored, not muchattention has been paid and the first work has been recently pub-lished [8]. The importance on studying the analog performance ofNWs remains not only on their application in analog circuits, butalso on their integration in mixed analog-digital circuits such ascomparators and converters.

In this work we present an experimental study of analog prop-erties for silicon Silicon-On-Insulator (SOI) NWs, analyzing both n-type and p-MOSFETs with channel lengths (L) of 10 lm and 40 nmand fin width (WFIN) varying from 9.5 nm to 10 lm, at room tem-perature. For the n-MOSFETs, the quasi-planar device (WFIN = 10 -lm) is compared to the NW with WFIN = 14.5 nm, from 300 Kdown to 100 K. An explicit correlation between the analog perfor-mance of Si NWs and their mobility behavior is presented for thefirst time, to the best of our knowledge. Moreover, it is the firsttime where the analog parameters of such ultimate devices areexplored at cryogenic temperatures. Numerical simulations arealso presented in order to explain the similarity observed for theintrinsic voltage gain (AV) for both n-type and p-MOSFETs varyingWFIN. Transconductance (gm), output conductance (gD), transcon-ductance over drain current ratio (gm/IDS) and Early voltage (VEA)are important figures of merit studied in this work. Transport char-acteristics are also investigated as a function of temperature andWFIN to justify the results observed for gm and gD.







0.0 0.2 0.4 0.6 0.8 1.0 1.20.0

0.5

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5

10

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T: 300, 250,200, 150and 100K

1E-6

1E-5

1E-4

1E-3

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10

Gate voltage (V)

Solid line: WFIN = 10µmDashed line: WFIN = 14.5nmVDS = 0.9V

1E-6

1E-5

1E-4

1E-3

0.01

0.1

1

10

100Normalized drain current - IDS/Wef (µA/µm)

µ

Fig. 2. IDS/Wef as a function of VGS for long channel n-MOS, from 300 K to 100 K, atVDS = 40 mV and 0.9 V.

50 100 150 200 250 300 3500.42

0.44

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50 100 150 200 250 300 35015

25

35

45

55

65

Thre

shol

d vo

ltage

(V)

Temperature (K)

nMOSL = 10 mµ

WFIN = 10µm WFIN = 14.5nm

k T ln(10)/q Subt

hres

hold

slop

e (m

V/d

ec)

x x

Fig. 3. Extracted threshold voltage and subthreshold slope as a function of T for n-

B.C. Paz et al. / Solid-State Electronics 128 (2017) 60–66 61

2. Devices and measurements

The measured transistors are silicon [110]-oriented triple gateNWs fabricated at CEA–Leti using SOI substrate and multi fingerstructures with 50 fins in parallel. The gate stack is composed byHfSiON/TiN (EOT = 1.4 nm), silicon thickness (HFIN) is 11 nm andburied oxide is 145 nm thick. Details about the fabrication of thetransistors can be found in [2,9]. Fig. 1 presents a cross-sectionTEM image (a) and a schematic (b) of the studied Si SOI NWMOSFET.

The measured curves of drain current (IDS) normalized by effec-tive channel width (Wef = 2HFIN + WFIN) as a function of gate volt-age (VGS) with drain voltage (VDS) of 40 mV and 0.9 V for longchannel n-MOS NW (WFIN = 14.5 nm) and quasi-planar devices(WFIN = 10 lm) from 300 K down to 100 K are shown in Fig. 2. Asindicated in Fig. 3, the devices present the subthreshold slope (S)near the theoretical limit of k � T � ln(10)/q [10] and the thresholdvoltage variation with temperature (DVTH/DT) is equal to �0.74and �0.56 mV/K, for quasi-planar and NW n-MOS, respectively.The VTH results of devices in this work are similar temperature-dependent comparing to FinFETs in literature [11], where DVTH/DT = �0.58 and �0.70 mV/K for WFIN = 20 and 370 nm, respec-tively. The threshold voltage has been extracted by the secondderivative method [12] and the subthreshold slope by oVGS/o(logIDS) versus VGS curves [13].

Fig. 4 shows |IDS| � L for n-type and p-MOS with L of 10 lm and40 nm, WFIN of 15 nm and 25 nm, at room temperature and |VDS|= 40 mV. Devices with L = 40 nm and WFIN = 15 nm present Sslightly degraded around 70 mV/dec for both n- and p-MOS, whilefor WFIN = 25 nm S is 95 mV/dec and 83 mV/dec, for n- and p-MOS,respectively. As WFIN increases, the short channel effects increaseas well, due to poor electrostatic control of the channel region.The short channel devices present lower |IDS| � L than long channelNWs as VGS increases, indicating mobility degradation and strongerinfluence of series resistance effects.

MOS with L = 10 lm.

0.0 0.5 1.00.0

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Normalized drain current - |IDS L (µA µm)

|VDS| = 40mVT = 300K

1E-6

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1Solid line: L = 10µmDashed line: L = 40nm

WFIN = 15nm WFIN = 25nm

pMOS

|


3.1. Channel width influence – long channel n- and p-MOS

Fig. 5 presents the transconductance normalized by the effectivechannel width (gm/Wef) as a function ofWFIN, for both n- and p-MOSwith L = 10 lm, at 300 K. Devices were biased in saturation with|VDS| = 0.9 V and gate voltage overdrive (VGT = VGS � VTH) of 0, 200and 400 mV. The maximum transconductance is also presented inthe same figure.

From Fig. 5, it is observed that gm/Wef decreases (degrades) withWFIN reduction for the n-MOS and increases (improves) for thep-MOS. Besides, the n-type devices show higher gm/Wef values incomparison to p-MOSFETs. The transconductance behavior isstrongly related to the effective carriers’ mobility (leff), wherethe plan related to the fin height (1 1 0)/[110] favors the holes

(a) (b)

Si

poly-Si

BOX

SiO2

TiNHfSiON

HFIN

WFIN

5nm

Fig. 1. Si SOI NW MOSFET cross section TEM image (a) and schematic (b).

Gate voltage (V)

Fig. 4. |IDS| � L as a function of VGS for n-type and p-MOS at |VDS| = 40 mV and300 K.

mobility and the plan related to the fin width (1 0 0)/[110] favorsthe electrons mobility [10]. In Fig. 5, for VGT equal to 400 mV, gm/Wef degrades 19% comparing the quasi-planar and the narrowestn-MOS, while for p-MOSFETs an improvement of 52% is observed.

Fig. 6 shows leff as a function of VGT, extracted through the splitC-V method [14], for the n-MOSFETs of Fig. 5. It is indicated themain scattering contributions, Coulomb, phonon and surfaceroughness and it is observed that Coulomb scattering is dominant

0.01 0.1 100

5

10

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45

L = 10 mµ |VGT| = 0V |VGT| = 200mV |VGT| = 400mV Maximum gm

Nor

mal

ized

tran

scon

duct

ance

- g m

/Wef (µ

S/µm

)

Fin width (µm)

|VDS| = 0.9V

Open symbols: pMOSClosed symbols: nMOS

Fig. 5. gm/Wef as a function of WFIN for n- and p-MOS, L = 10 lm, |VDS| = 0.9 V, |VGT|= 0, 200 and 400 mV and maximum gm.

-0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.10

50

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scatt

erin

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WFIN = 19.5nm WFIN = 14.5nm WFIN = 9.5nm

WFIN = 10µm WFIN = 99.5nm WFIN = 59.5nm WFIN = 39.5nm

Effe

ctiv

e m

obili

ty (c

m2 /V

s)

Gate voltage overdrive (V)

nMOSL = 10 mµT = 300K

Coul

omb

Fig. 6. leff as a function of VGT for n-MOS with L = 10 lm.

0.01 0.1 101E-11

1E-10

1E-9

1E-8

|VGT| = 0V |VGT| = 200mV |VGT| = 400mV


Nor

mal

ized

out

put c

ondu

ctan

ce -

g D/W

ef (S

/µm

)

Fin width (µm)

L = 10 mµ|VDS| = 0.9V

Fig. 8. gD/Wef as a function of WFIN for n- and p-MOS, L = 10 lm, |VDS| = 0.9 V, |VGT|= 0, 200 and 400 mV.

62 B.C. Paz et al. / Solid-State Electronics 128 (2017) 60–66

at VGT = 0 V, while at moderate inversion, VGT equal to 200 mV and400 mV, phonon scattering determines the effective mobilitybehavior. Analyzing leff as a function of WFIN, extracted for then-MOSFETs at VGT = 0, 200 and 400 mV, in Fig. 7, it is observed thatas the sidewall surfaces (1 1 0) contribution becomes more impor-tant to the effective mobility, which means reducing WFIN, the leff

degrades 26% at VGT = 400 mV, which is close to the gm/Wef degra-dation obtained in Fig. 5.

Fig. 8 presents the output conductance normalized by theeffective channel width (gD/Wef) as a function of WFIN, for bothn- and p-MOS with L = 10 lm, at 300 K, |VDS| = 0.9 V and |VGT| = 0,

0.01 0.1 1050

100

150

200

250

300

350nMOSL = 10 mT = 300K

VGT = 0VVGT = 200mVVGT = 400mV

Effe

ctiv

e m

obili

ty (c

m2 /V

s)

Fin width ( m)µ

µ

26%

Fig. 7. leff as a function of WFIN for n-MOS, L = 10 lm, VGT = 0, 200 and 400 mV.

200 and 400 mV. For both n- and p-MOS, gD/Wef decreases(improves) as WFIN is reduced in almost one order of magnitude,comparing the narrowest and the widest devices. The output con-ductance relates IDS and VDS (gD = dIDS/dVDS) and its improvement isexpected in NWs due to their better electrostatic control andreduced channel modulation effect (CME) [15].

Fig. 9 shows the results for the calculation of AV, which is givenby the gm/gD ratio, as a function of WFIN. For both n- and p-MOS, itis observed that AV follows the same trend of the inverse of gD/Wef,which reduction decreasing WFIN is responsible for increasing(improving) significantly the intrinsic voltage gain of NWs in com-parison to wide MOSFETs. This strong improvement of AV indicatesan important advantage of such devices concerning their analogperformance.

From Fig. 9, it is also observed that the intrinsic voltage gain ishigher at lower VGT, which occurs because gm and gD have differentdependences on VGT. Fig. 10 presents both gm/Wef and gD/Wef as afunction of VGT for quasi-planar and narrow n-type and p-MOSFETs. It is clear that both gm and gD increase with VGT rise.However, it is possible to observe that gD degradation is strongerthan gm improvement, which causes AV reduction varying VGT from0 V to 400 mV.

3.2. Channel width influence – short channel n- and p-MOS

Fig. 11 presents gm/Wef as a function of WFIN, for both n- andp-MOS with L = 40 nm, at 300 K, |VDS| = 0.9 V and VGT = 0, 200and 400 mV. For short channel devices, the transconductancebehavior is not only determined by the effective mobility, once

0.01 0.1 10

60

65

70

75

80

85

90

95 |VGT| = 0V |VGT| = 200mV |VGT| = 400mV

Intri

nsic

vol

tage

gai

n (d

B)

Fin width (µm)


|VDS| = 0.9VL = 10 mµ

Fig. 9. AV as a function of WFIN for n- and p-MOS, L = 10 lm, |VDS| = 0.9 V, |VGT| = 0,200 mV and 400 mV.

(a)

-0.1 0.0 0.1 0.2 0.3 0.4 0.502468

10121416182022

nMOS, WFIN = 10 mµ

µ

µ

µ

µ

µ

pMOS, WFIN = 10 mnMOS, WFIN = 9.5nmpMOS, WFIN = 15nm

L = 10 m|VDS| = 0.9V

Nor

mal

ized

tran

scon

duct

ance

- g m

/Wef (µ

S/µm

)


(b)

0.0 0.1 0.2 0.3 0.41E-5

1E-4

1E-3

0.01

0.1nMOS, WFIN = 10 m

pMOS, WFIN = 10 mnMOS, WFIN = 9.5nmpMOS, WFIN = 15nm

L = 10 m|VDS| = 0.9V

Nor

mal

ized

out

put c

ondu

ctan

ce -

g D/W

ef (µ

S/µm

)


Fig. 10. gm/Wef (a) and gD/Wef (b) as a function of VGT for quasi-planar and narrown- and p-MOS, L = 10 lm and |VDS| = 0.9 V.

0.01 0.1 10

200

400

600

800

1000

1200

1400

1600

1800

Nor

mal

ized

tran

scon

duct

ance

- g m

/Wef

(µS/

µm)

Fin width (µm)

|VGT| = 0V |VGT| = 200mV |VGT| = 400mV

|VDS| = 0.9VL = 40nm


Fig. 11. gm/Wef as a function of WFIN for n- and p-MOS, L = 40 nm, |VDS| = 0.9 V,|VGT| = 0, 200 and 400 mV.

0.01 0.1 1020406080

100120140160180200220

Nor

mal

ized

tran

scon

duct

ance

- g m

/(Wef/L

)(µS

)

Fin width (µm)

nMOS - L = 10 mµ

µ nMOS - L = 40nm pMOS - L = 10 m pMOS - L = 40nm

|VDS| = 0.9V|VGT| = 400mV

Fig. 12. gm/(Wef/L) as a function of WFIN for n- and p-MOS, L = 40 nm and 10 lm,|VDS| = 0.9 V and |VGT| = 400 mV.

0.01 0.1 10

1E-5

1E-4

Nor

mal

ized

out

put c

ondu

ctan

ce -

g D/W

ef (S

/µm

)

Fin width (µm)

|VDS| = 0.9VL = 40nm

|VGT| = 0V |VGT| = 200mV |VGT| = 400mV


Fig. 13. gD/Wef as a function of WFIN for n- and p-MOS, L = 40 nm, |VDS| = 0.9 V,|VGT| = 0, 200 and 400 mV.


short channel effects (SCE) and series resistance play an importantrole. For example, for the n-MOSFETs, besides leff decreases withWFIN reduction, causing a degradation of gm/Wef, a strong oppositebehavior is expected to predominate due to improved SCE in NWs,as demonstrated in [8]. Moreover, as WFIN reduces the series resis-tance (RS) effects increase, leading to the gm/Wef degradationobserved for the WFIN narrower than 25 nm.

In order to compare the results of gm for both long and shortchannel nanowires, Fig. 12 presents gm normalized by Wef/L, forboth n-type and p-MOSFETs with L = 10 lm and 40 nm and |VGT|= 400 mV. It is observed that long channel devices present higher

gm/(Wef/L) in comparison to short channel devices, because ofstrong mobility degradation with channel length reduction. FromL of 10 lm to 40 nm, there is a decrease of 75% and 57%, forquasi-planar n-type and p-MOS, respectively. This percentageremains similar for narrow transistors, for WFIN around 14.5 nm,gm/(Wef/L) decreases 70% and 60%, for n-type and p-MOS,respectively.

Fig. 13 presents gD/Wef as a function of WFIN, for both n- and p-MOS with L = 40 nm, at 300 K, |VDS| = 0.9 V and VGT = 0, 200 and400 mV. As observed for the long channel transistors in Fig. 8,gD/Wef also improves for both n- and p-MOS by decreasing WFIN

due to CME reduction. Once the effective channel length reductionin saturation is more significant as the transistor becomes shorter,better CME control is more important in short channel transistors.

From the results of gm and gD, Fig. 14 shows AV as a function ofWFIN for devices with L = 40 nm. The inverse of the output conduc-tance defines the trend of AV varying WFIN, what leads to the greatimprove of 20 dB for the narrowest NWs comparing to the quasi-planar MOSFET for both n- and p-MOS. An interesting observationis that both n- and p-MOSFETs show very similar values for AV andits behavior with respect to WFIN, despite the fact that they presentdifferent values of gm/Wef and gD/Wef. Higher values for gm/Wef andgD/Wef are observed for the n-type devices in comparison to the p-MOSFETs due to higher leff. As the effective mobility may affectsimilarly gm and gD, its influence may disappear by taking thegm/gD ratio, which emphasizes that channel modulation is the

0.01 0.1 105

10

15

20

25

30

35

Intri

nsic

vol

tage

gai

n (d

B)

Fin width (µm)

|VGT| = 0V |VGT| = 200mV |VGT| = 400mV


|VDS| = 0.9VL = 40nm

~20dB

Fig. 14. AV as a function of WFIN for n- and p-MOS, L = 40 nm, |VDS| = 0.9 V, |VGT| = 0,200 mV and 400 mV.


main effect on determining AV, suggesting that both n- andp-MOSFETs may suffer similarly from CME.

To verify if n- and p-type devices present similar CME, tridi-mensional numerical simulations have been performed with Sen-taurus Device Simulator, from Synopsys [16]. Fig. 15 presentssimulation results for the electrons and holes density along thechannel position for n- and p-MOS at 300 K, L = 40 nm andWFIN = 15 nm. As indicated in the schematics in Fig. 15, carriers’

(a)-10 0 10 20 30 40 50

1E13

1E14

1E15

1E16

1E17

1E18

1E19

1E20

1E21

Drain

SourceGate

BOX

At the center of thetop interface, nearthe drain

DR

AIN

Car

rier d

ensi

ty (c

m-3

)

Channel position (nm)

nMOS pMOS

SOU

RC

E

L = 40nmWFIN = 15nmVGT = 0mVDashed: |VDS| = 0.9VSolid: |VDS| = 1.2V

(b) -10 0 10 20 30 40 50

1E13

1E14

1E15

1E16

1E17

1E18

1E19

1E20

1E21

Drain

SourceGate

BOXAt the center of thesidewall interface, near the drain

DR

AIN

Car

rier d

ensi

ty (c

m-3

)

Channel position (nm)

nMOS pMOS

SOU

RC

E

L = 40nmWFIN = 15nmVGT = 0mVDashed: |VDS| = 0.9VSolid: |VDS| = 1.2V

Fig. 15. Simulation results for the carrier density at the top interface (a) and theside interface (b) along the channel position for n- and p-MOS, L = 40 nm,WFIN = 15 nm, |VGT| = 0 V, |VDS| = 0.9 and 1.2 V.

density has been extracted at the top (a) and sidewall (b) SiO2/Siinterfaces, where the conduction happens, near the drain, wheredepletion is induced by drain voltage for the device operating insaturation. Bias condition is |VGT| = 0 V and |VDS| = 0.9 and 1.2 V,where the devices operate in saturation regime. A dotted line indi-cates the channel doping concentration (1 � 1015 cm�3). When thecarrier density is higher than 1 � 1015 cm�3, an inversion layer isobserved, otherwise the region is depleted, as it is possible to notenear the drain. The CME can be seen in Fig. 15 by the longerdepletion region as the |VDS| is increased. For both applied VDS

and interfaces analyzed, the depletion region is very similarcomparing n- and p-MOSFETs, being the effective channel lengthof the p-MOS only 1 nm shorter than for the n-MOS. These closeresults for the carriers’ density sustain that the n- and p-MOSsuffer from similar CME, which explains the close gD and, as aconsequence, AV results.

3.3. Temperature influence

Fig. 16 shows gm/IDS presented as a function of IDS/(Wef/L) for n-MOS with L = 10 lm, at VDS = 0.9 V. Quasi-planar and NW FETs arecompared from 300 K to 100 K. Reducing either T or WFIN, gm/IDSincreases. The maximum value of gm/IDS is determined in weakinversion by (1), where n is the body factor, q is the electron chargeand k is the Boltzmann constant [10]. Although gm/IDS in weakinversion must be higher for NWs in comparison to quasi-planarMOSFETs, once the better the electrostatic control the closer n is

1E-8 1E-7 1E-6 1E-50

25

50

75

100

125 Weak inversion

Strong inversion

Tran

scon

duct

ance

ove

r dra

in c

urre

nt ra

tio (V

-1)

Normalized drain current - IDS/(Wef/L) (A)

Solid lines: WFIN = 10µmDashed lines: WFIN = 14.5nm

300K

100KL = 10 mµVDS = 0.9V

Moderate inversion

nMOS

Fig. 16. gm/IDS as a function of IDS/(Wef/L) for n-MOS, L = 10 lm and VDS = 0.9 V.

10 100

300

400

500

600

700800900

nMOSL = 10 mµVGT = 400mV

WFIN = 10 nm WFIN = 14.5nm

Effe

ctiv

e M

obili

ty (c

m2 /V

s)

Temperature (K)

T -0.88

Fig. 17. leff as a function of T for n-MOS, L = 10 lm, at VGT = 400 mV.

100 200 30010

20

30

40

50

60

100 200 3001E-3

0.01

0.1

100 200 300200

300

400

500

600

700nMOSL = 10 m

nMOSL = 10 m


T -0.88

nMOSL = 10 mµ µ µ

VGT = 400mVVDS = 0.9V

Nor

mal

ized

tran

scon

duct

ance

(µS/

µm)

Temperature (K)



T -0.88

Nor

mal

ized

out

put c

ondu

ctan

ce (µ

S/µm

)

Temperature (K)


T -0.88Effe

ctiv

e m

obili

ty (c

m2

Temperature (K)

(a) (b) (c)

x/V

s)

Fig. 18. gm/Wef (a), gD/Wef (b) and leff (c) as a function of T for n-MOS, L = 10 lm, at VDS = 0.9 V and VGT = 400 mV.

100 200 30060

62

64

66

68

70

72

74


Intri

nsic

vol

tage

gai

n (d

B)

Temperature (K)

AV VEA


nMOSL = 10 mµ

200

300

400

500

600

700

800

900

o

Early

vol

tage

(V)

Fig. 19. AV and VEA as a function of T for n-MOS, L = 10 lm, at VDS = 0.9 V andVGT = 400 mV.


to unity, Fig. 16 shows higher differences than expected and strongdegradation for WFIN = 10 lm, especially at low temperatures. Thiseffect is related to the current originated from tunneling in thedrain region under the gate, known as gate-induced-drain-leakage (GIDL) current [17]. As observed in Fig. 2 at VDS = 0.9 V,GIDL current is one order of magnitude higher for WFIN = 10 lmthan 14.5 nm and appears at higher values of VGS decreasing T,which explains the degradations in the gm/IDS curves. Strongerimmunity to GIDL effect allows NWs to present maximum gm/IDSclose to ideal values, even at T = 100 K.

gm

IDS

� �

¼ qn� k� T

ð1Þ

According to [18], at saturation, gm/IDS can be estimated by (2),where RS, leff and Wef are the parameters that depend on WFIN.Extracting RS according to [19], an increase of a factor close to 10is obtained from WFIN of 10 lm to 14.5 nm, while leff decreasesof a factor close to 1.5. As Wef reduces almost 3 orders ofmagnitude, it is found to be the key parameter in (2), where gm/IDS varies with the inverse of RS � leff �Wef, explaining highergm/IDS for the NW than the quasi-planar FET.

gm

IDS

� ��

�

�

�

sat

¼ 2VGT

� 1þ ðRSleffCoxWefVGT Þ2L

1þ ðRSleffCoxWefVGT ÞL

" #

ð2Þ

Fig. 17 presents leff as a function of T, for long channel n-MOSwith WFIN of 10 lm and 14.5 nm, extracted at VGT = 400 mVthrough split C-V [14]. As previously discussed in Fig. 6, at

VGT = 400 mV, phonon scattering has the dominant contribution,which can be confirmed by analyzing the temperature influenceon the effective mobility. Above 100 K, leff shows the phononmobility dependence with temperature, lph / T�c [20], wherethe temperature dependence coefficient (c) is found to be closeto 0.88 for both NW and quasi-planar FETs. Bellow 100 K, surfaceroughness limited contribution becomes dominant, phonon scat-tering is negligible and, as consequence, leff saturates [21].

Fig. 18 presents gm/Wef (a), gD/Wef (b) and leff (c) as a functionof T, for long channel n-MOS. Both gm/Wef and gD/Wef have beenextracted at VDS = 0.9 V and VGT = 400 mV. The dashed line indi-cates the same temperature dependence coefficient (/ T�0.88).Reducing T, it is observed that gm/Wef and gD/Wef increases follow-ing similar dependence in relation to leff behavior with tempera-ture. For the transconductance, results show clearly that itsvariation with temperature is mainly due to mobility. For the out-put conductance, the rate of increase with temperature reductionis slightly higher than what is observed for leff.

Fig. 19 shows AV and VEA as a function of T. As expected by theresults of gm and gD, the temperature effect is almost annulatedone by each other, leading to a smooth decrease with temperaturereduction. Once gD increases with a higher rate than gm, decreasingT from 300 K to 100 K, AV shows a smooth decrease of 3.6 dB and2.1 dB for WFIN of 14.5 nm and 10 lm, respectively. As VEA followsthe inverse of gD as well, once VEA = IDS/gD, much higher (more than2.3 times) values are obtained for the nanowire, in comparison toWFIN = 10 lm, due to improved CME control.

4. Conclusions

Results of analog parameters of scaled silicon nanowires SOIMOSFETs have been presented for both long and short channel n-and p-type transistors. Temperature influence has been studieddown to 100 K for long channel n-MOSFETs.

An explicit dependence on the effective mobility has been pre-sented for transconductance of long channel devices varying finwidth. The reduced output conductance of nanowires due to chan-nel modulation effect control determines strong improvements onthe intrinsic voltage gain. Similar channel modulation effects forboth short channel n-type and p-MOSFETs has been demonstrated,leading to similar intrinsic voltage gain results varying fin width.

Temperature influence is mainly determined by the phononmobility dependence and its effect is almost annulated by takinggm/gD, giving soft increase of intrinsic voltage gain with tempera-ture increase.


The nanowires have shown great improvements concerninganalog performance, due to short channel effects control, reducedchannel modulation effect and better body factor. Even n-typeMOSFETs presenting lower effective mobility than quasi-planartransistors, both n-type and p-NWs presented 20 dB of increase forintrinsic voltage gain in devices with L = 40 nm and WFIN = 15 nm,at room temperature.

Acknowledgements

The authors would like to acknowledge the IBM/STMicroelec-tronics/Leti Joint Development Alliance, CNPq, CAPES and FAPESPprocess 2015/10491-7 for the financial support to this work.

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An in-depth analysis of temperature effect on DIBL in UTBB FD SOIMOSFETs based on experimental data, numerical simulations andanalytical models


⇑ Corresponding author at: Department of Electrical Engineering, Centro Univer-sitário da FEI, São Bernardo do Campo, Brazil.

E-mail address: [email protected] (A.S.N. Pereira).

A.S.N. Pereira a,b,⇑, G. de Streel a, N. Planes c, M. Haond c, R. Giacomini b, D. Flandre a, V. Kilchytska a

a ICTEAM, Université catholique de Louvain, Louvain-la-Neuve, BelgiumbDepartment of Electrical Engineering, Centro Universitário da FEI, São Bernardo do Campo, Brazilc STMicroelectronics, Crolles, France




Keywords:Fully-Depleted Silicon-On-Insulator (FDSOI)UTBBDIBLTemperature dependence

The Drain Induced Barrier Lowering (DIBL) behavior in Ultra-Thin Body and Buried oxide (UTBB) transis-tors is investigated in details in the temperature range up to 150 �C, for the first time to the best of ourknowledge. The analysis is based on experimental data, physical device simulation, compact model(SPICE) simulation and previously published models. Contrary to MASTAR prediction, experiments revealDIBL increase with temperature. Physical device simulations of different thin-film fully-depleted (FD)devices outline the generality of such behavior. SPICE simulations, with UTSOI DK2.4 model, only par-tially adhere to experimental trends. Several analytic models available in the literature are assessed forDIBL vs. temperature prediction. Although being the closest to experiments, Fasarakis’ model overesti-mates DIBL(T) dependence for shortest devices and underestimates it for upsized gate lengths frequentlyused in ultra-low-voltage (ULV) applications. This model is improved in our work, by introducing atemperature-dependent inversion charge at threshold. The improved model shows very good agreementwith experimental data, with high gain in precision for the gate lengths under test.


1. Introduction

Driven by the continuous demand for the increase of the oper-ation speed and the integration density of complex digital circuits,semiconductor technology continues its progress in device scalingdown to 20 nm and beyond. Drain Induced Barrier Lowering (DIBL)is one of the measures that allows for assessing electrostatic integ-rity of the device and its capability for scaling down. Strong crite-rion on DIBL is imposed with typically considered values of DIBLlower than 100 mV/V [1,2]. The Ultra-Thin Body and Buried oxide(BOX) (so-called UTBB) Fully Depleted (FD) Silicon on Insulator(SOI) technology is widely considered as one of the candidates ableto satisfy this criterion featuring excellent electrostatic integrity.This is achieved thanks to the thin body and thus good control ofthe channel from the gate; thin BOX and thus suppression/reduc-tion of fringing electric field lines penetration in BOX; introductionof Ground Plane (GP), or highly doped region just underneath theBOX and thus suppression of the coupling through the substrate

[2–4]. It was demonstrated that the scalability of UTBB devicescan reach the 8 nm node if the silicon film and the BOX thicknessesare scaled down to 5 nm and 10 nm, respectively [2]. However,DIBL may vary with temperature and hence devices that fit therequirements at room temperature, may become out of specifica-tions at higher temperatures.

Studying the temperature effects (from room temperature up to150 �C) is important for two reasons. Firstly, it is, evidently, crucialfor high-temperature applications. With deeper electronics pene-tration in everyday life (automotive, health/medical, smartdevices), such usually considered niche-applications start to goout from a niche and get more attention. Secondly, good under-standing of high-temperature effects are important even forroom-temperature (RT) applications, as these devices can beaffected by self-heating with channel temperature reaching�100 �C under normal operation conditions [5–7].

Some results/data on DIBL variation from room to high temper-ature available in the literature shows that the DIBL of 0.4–1.5 lm-long bulk Si MOSFETs increase with temperature specially forshorter devices [8,9]. For 28 nm long UTBB devices [10], an increaseof DIBL by about 20 mV/V over 100 �C was observed when







68 A.S.N. Pereira et al. / Solid-State Electronics 128 (2017) 67–71

compared to RT. However, in-depth analysis of DIBL evolution withtemperature in such devices was not performed before.

The present work provides a detailed analysis of DIBL behaviorat high temperatures (up to 150 �C) in UTBB FDSOI MOSFETs basedon experimental data, physical device simulations (Atlas), compactmodelling (SPICE) and several previously published analyticalmodels. The final aim is a revision of previously published model(s) to be applicable for DIBL prediction in a wide temperaturerange. This paper is an extended version of the work/abstract pre-sented at EuroSOI/ULIS conference 2016 [11].

2. Experimental details

The experimental devices were fabricated at ST Microelectron-ics. More details can be found e.g. in [12]. Devices feature a BOXthickness (tBOX) of 25 nm and silicon body (tSi) of 7 nm. The metalgate stack is composed of 2.3 nm of HfSiON with an equivalentoxide thickness (tOX) of 1.3 nm. The measured devices aren-channel MOSFETs with gate lengths (L) from 34 to 500 nm andchannel width (W) of 1 lm. The channel is left undoped. Both stan-dard VT (STDVT) and low VT (LVT) devices were characterized up to150 �C for DIBL evaluation.

Drain current versus gate voltage, ID-VG characteristics weremeasured in linear and saturation regimes. The DIBL values werecalculated from DVG/DVD, where VG is the gate voltage at theconstant current value of 10�7 (W/L) for low drain voltage (VDL)of 50 mV or high drain voltage (VDH) of 1 V.


3.1. Experiments

Fig. 1 shows the experimental DIBL behavior as a function oftemperature for the devices with different gate lengths. The

25 50 75 100 125 1500

10

20

30

40

50

60

70

80

90Open: LVTClosed: STDVT

DIB

L (m

V/V

)

T (oC)

>L

Lines: MASTAR [13]

Fig. 1. Measured DIBL as a function of temperature (symbols) and MASTARmodeling (lines) for STDVT and LVT of 38, 42, 60, 90, 120 and 500 nm long devices(from top to bottom).

Table 1Different FD nMOSFET structures simulated with Atlas.

UTBB overlap UTBB underlap

tSi (nm) 7 7tox (nm) 1.3 1.3tBOX (nm) 25 25L (nm) 50 50LS (nm) 0 10

increase of DIBL with temperature can be clearly observed for bothLVT and STDVT transistors. Moreover, this increase is stronger inshorter devices. DIBL values calculated using MASTAR software[13] for the above physical device parameters are plotted on thesame graph for the sake of comparison. They are seen to be inde-pendent of temperature. More details on MASTAR model tempera-ture results will be given below, in Section 3.3.

3.2. Physical and compact model simulation

In order to verify whether some particular process featurescould generate the observed DIBL behavior we performed physicaldevice simulations using Atlas software [14]. Table 1 presents thevarious thin-film FD nMOSFETs (NA = 1015 cm�3) we assessed withthe following objectives:

– Comparison between Underlapped and Overlapped structureswas done to detect possible effect of effective channel lengthvariation with temperature.

– Comparison between thin and thick BOX devices aimed at dis-tinguishing possible effect of mean channel position variationwith temperature.

– An ideal double gate (DG) structure was also studied to removeany possible channel depth position and substrate depletioneffects.

Fig. 2 presents the DIBL for different thin-film FD structuressimulated with Atlas [14]. For all simulated structures, the trendis the same and is identical to that of experimental results ofFig. 1, highlighting that this DIBL temperature dependence is phys-ical and not specific to the measured UTBB devices or to the exper-imental setup. The lower DIBL values among single gate devices areobtained for UTBB with underlap, as expected.

Fig. 3 shows the DIBL variation with temperature from circuit-level SPICE simulations using UTSOI DK2.4 model from CEA-Leti

DG UTB FDSOI

7 7 301.3 1.3 1.3tBOX = tox 150 15050 50 20010 0 0

25 50 75 100 125 150 175 200 2250

10

20

30

40

50

60

70

80UTBB Underlap UTBUTBB Overlap FDSOI DG

DIB

L (m

V/V

)

T (oC)

VDL = 50mVVDH = 1V

Fig. 2. DIBL as a function of temperature from Atlas simulations of different SOIstructures.

25 50 75 100 125 150

0

2

4

6

8

10

12

14Experimental L = 42nmExperimental L = 60nm UTSOI DK2.4 L = 42nm UTSOI DK2.4 L = 60nm

DIB

L(T)

- D

IBL

(25o C

) (m

V/V

)

T (oC)

STDVT

Fig. 3. DIBL increase with temperature for devices with L = 42 and 60 nm (STDVT)extracted from measurements and SPICE simulations.

A.S.N. Pereira et al. / Solid-State Electronics 128 (2017) 67–71 69

and ST Microelectronics [15] compared to experimental data forstandard VT devices with L of 42 and 60 nm. The UTSOI DK2.4model qualitatively reproduces the experimental DIBL dependenceon temperature. However, the modeled DIBL(T) variation is quali-tatively incorrect underestimating DIBL increase with temperature,particularly for shorter-length devices.

3.3. Analytic models analysis

In this section, an analysis of previously published models isperformed in a view of their applicability for DIBL prediction in awide temperature range. We assessed the ability of different ana-lytic models to reproduce DIBL vs. temperature increase in UTBBdevices. Three models are considered:

(1) MASTAR software [13], which is based on Voltage DropTransformation (VDT) model [16,17].

(2) Arshad’s model [18], an improved version of MASTAR model,which takes into account the effective channel length (LEFF),the mean channel position in the thin film (YMEAN) and thesubstrate depletion.

Fig. 4. Experimental and modeled DDIBL/DT up to 150 �C as a function of channellength.

(3) Fasarakis’ model [19] which is a threshold voltage model,defining the DIBL as the difference between the thresholdvoltage, VT, for low and high drain voltage. These resultshave been obtained as follows.

Fig. 4 shows the DIBL variation with temperature, i.e. dDIBL/dT(in a T range up to 150 �C) extracted from the experiments andfrom different models published in literature as a function of gatelength. It can be noticed that both Arshad’s and Fasarakis’ modelsdescribe the trends, featuring enhanced DIBL vs T increase with Lshortening.

3.3.1. MASTAR modelThough temperature is an input parameter and MASTAR soft-

ware [13] can calculate the drain current and SCE (Short-ChannelEffects) for different temperatures, the DIBL extracted from MAS-TAR has no dependence on temperature (Figs. 1 and 4). This hap-pens because the DIBL equation used by MASTAR is based on theVDT model [16,17], which takes into account just dimensionaland materials variables. Originally developed for bulk devices,the approach for FDSOI transistors is presented in Eq. (1) [1,13]

DIBL ¼ 0:8eSieOX

1þ t2SiL2

� �

tOXL

tSi þKtBOXL

� �

VD ð1Þ

where eSi is the silicon permittivity, eOX is the oxide permittivityand K is the factor that represents how deep the gate field in thechannel region extends in the buried oxide, its value is calculatedby Eq. (2)

K ¼ 3ðL� tSiÞðL� tSiÞ þ 3tBOX

ð2Þ

3.3.2. Arshad’s modelArshad’s model [18] can be adapted for different T by consider-

ing YMEAN (T) and LEFF (T) extracted from simulations. Substratedepletion (considered in Arshad’s model) and its variation withtemperature can be neglected in our case as GP provides an effi-cient screening. The YMEAN is extracted from the electron concen-tration of the simulated structure file saved at the VG point ofDIBL extraction. The expression to calculate its value is (3)

YMEAN ¼R tSi0 y � eC dyR tSi0 eC dy

ð3Þ

where eC is the electron concentration and y is the vertical positionin the silicon film. The YMEAN value is used to correct the tSi and tOXvalues, which are changed to tSiel and tOXel, and are given by (4) and(5)

tSiel ¼ tSi � YMEAN ð4Þ

tOXel ¼ tOX þ eSieOX

� �

YMEAN ð5Þ

Effective length correction in Arshad’s model considers theimpact of the underlap gate–source/drain regions. This is madeby introducing the underlap (spacer in Arshad’s model) length(LS) (accounting for both gate-to-source and gate-to-drain under-lap regions) to calculate effective channel length, as presented in(6)

LEFF ¼ Lþ ð2LSÞ ð6ÞHowever, those LEFF from (6) have no dependence with temper-

ature. Hence, we also extracted LEFF values from simulated electronconcentration at different VG points for each temperature asdescribed in [20]. As an example, Fig. 5 shows YMEAN and LEFF vari-ation with temperature for the devices with the gate length of 38and 120 nm. The YMEAN shifts towards bottom interface (with

25 50 75 100 125 15032

33

34

35

36

113

114

115

116

117

118

L EFF

(nm

)

T(oC)

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

L = 38nm L = 120nm

YM

EA

N(n

m)

YMEAN

LEFF

Fig. 5. Simulated YMEAN (open symbols) and LEFF (closed symbols) at the VG point ofDIBL extraction and VD = 1 V as a function of temperature for Arshad’s model (YMEAN

measures from top Si-gate oxide interface).

Fig. 6. DIBL as a function of temperature for the devices with L = 38 and 120 nm.

25 50 75 100 125 1505.0x109

1.0x1010

1.5x1010

2.0x1010

2.5x1010

3.0x1010

3.5x1010

4.0x1010

4.5x1010

5.0x1010

L = 120nm VD = 50mV L = 120nm VD = 1V L = 38nm VD = 50mV L = 38nm VD = 1V

QTH

(cm

-2)

T (oC)

Lines: Fasarakis et alSymbols: Extracted from simulations

Fig. 7. QTH as a function of temperature for Fasarakis’ model and extracted fromsimulations for L = 38 and 120 nm.

70 A.S.N. Pereira et al. / Solid-State Electronics 128 (2017) 67–71

thicker oxide and hence higher DIBL) and effective length shortenswith T increase. Both facts naturally result in DIBL increase athigher T featuring also some enhancement for the shorter lengths,thus confirming our experimental results. However, incorporationof these dependences is not at all sufficient to reproduce experi-mental DIBL(T) results (from Fig. 1).

3.3.3. Fasarakis’ modelIn Fasarakis’ model [19], the VT is quantitatively defined as the

gate voltage at which the minimum carrier charge sheet density(QINV) at the effective conductive path reaches a value QTH ade-quate to achieve the turn-on condition, such a definition is equiv-alent to the constant current method of VT extraction. The effectiveconductive path is defined according to [21]. The VT expression forVSUB = 0 is given by (7). The third term of original equation in [19]was neglected because of zero VSUB condition.

VT ¼ VFB þ Af VthlnQTHNA

n2i tSi

� �

� Bf /d � VthlnQTHNA

n2i tSi

� �� 12

/d þ VD � VthlnQTHNA

n2i tSi

� �� 12

ð7Þ

where VFB is the flat-band voltage, Vth is the thermal voltage (k�T/q),/d is the junction built-in voltage, ni is the intrinsic silicon concen-tration, Af and Bf are dependent on dimensional parameters of thetransistors. The QTH value is defined by (8)

QTH ¼ 7 � 1010 1þ 8VDkLþ 4

tOXtBOX

� ��2

ð8Þ

where k is the natural length along the channel. The channel posi-tion (YMEAN) is calculated from equation

YMEAN ¼ AC � tSi ð9Þwhere AC is a model parameter. For geometrical parameters lyingwithin wide ranges in real device applications AC value is 0.05[19]. Considering AC and tSi values for our experimental devicesthe calculated YMEAN is 0.35 nm.

Fasarakis’ model shows much better results comparing to othermodels (Fig. 4). However, it gives stronger dependence than exper-imentally observed one, particularly overestimating DDIBL/DT val-ues as well as absolute DIBL values (see Fig. 6) in shorter devicesand underestimating them in long ones.

3.3.4. Upgrade of Fasarakis’ modelWe believe that the reason of such quantitative disagreement is

that the temperature dependence of the channel position (YMEAN)

and the inversion charge defined at the threshold condition (QTH)in Fasarakis’ model were not taken into account. Our proposal isto extract YMEAN and QTH for each temperature from simulatedelectron concentration at VG points (low and high VD) of DIBLextraction. YMEAN is extracted from Eq. (3) and QTH values are cal-culated by multiplying the electron concentration value at YMEAN

position by the YMEAN value itself. Fig. 7 shows the QTH values asa function of temperature calculated using Fasarakis originalmodel (Eq. (8)) and extracted from simulations. It can be observedthat Fasarakis’ model values are constant in all temperature rangeand the extracted values have temperature dependence.

Therefore, in order to upgrade Fasarakis model we propose toincorporate QTH(T) dependence. We introduce the QTH valuesobtained above (by simulations) in Fasarakis’ original model. Theresults are shown in Figs. 4 and 6, referred as ‘‘Fasarakis + QTH(T) +YMEAN dependence”. It can be observed that the proposed upgradedmodel reproduces well the experimental data in the whole L rangeunder consideration. Note that the proposed improvement is themost accurate with experimental data, presenting a precision gainof e.g. 35% for L = 120 nm. Thus, the upgraded model can be usedto estimate/predict the temperature dependence of DIBL in UTBB

A.S.N. Pereira et al. / Solid-State Electronics 128 (2017) 67–71 71

devices with different lengths. It is worth noting a significantimprovement in the model accuracy even for longer devices, wherethe other models get far from experimental results. This is impor-tant as in some applications, especially ULV, the use of channellengths above the minimal length of the technology is common tominimize current leakage [22] and to have better analog perfor-mance [23].

4. Conclusions

The DIBL dependence on temperature in UTBB FD SOI MOSFETswas analyzed. The experimental results revealed increase of DIBLwith temperature. This trend is confirmed by both physical andSPICE simulations. The fact that physical device simulations of dif-ferent thin-film architectures provide the same trends emphasizesgenerality of such DIBL temperature behavior. Existing models,however, do not allow to reproduce DIBL(T) dependence properly.We proposed a way to physically upgrade the threshold voltagemodel of Fasarakis et al., by including inversion charge (andaccounting for channel position) dependence on temperature inorder to correctly reproduce/predict DIBL variation with tempera-ture for devices with different lengths. The obtained results showvery good agreement with experimental data and significant gainof precision for both shortest devices and for longer ones withchannel lengths in the range used for low leakage ULV digital orgood output conductance analog applications for this technology.

Acknowledgments

A.S.N. Pereira and R. Giacomini would like to thank FAPESP(process 2014/11627-7) and CNPq for the financial support. Thework is partially funded by FNRS (Belgium), Eniac Places2be andEcsel WAYTOGO FAST projects.

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Characterization and modelling of layout effects in SiGe channelpMOSFETs from 14 nm UTBB FDSOI technology


⇑ Corresponding author at: STMicroelectronics, 850 rue Monnet, B.P. 16, F-38926Crolles, France.

E-mail addresses: [email protected] (R. Berthelon), [email protected] (F. Andrieu).

R. Berthelon a,b,c,⇑, F. Andrieu b, S. Ortolland a, R. Nicolas a, T. Poiroux b, E. Baylac a, D. Dutartre a, E. Josse a,A. Claverie c, M. Haond a

a STMicroelectronics, 850 rue Monnet, B.P. 16, F-38926 Crolles, FrancebCEA-LETI, Minatec Campus, 17 rue des Martyrs, 38054 Grenoble, FrancecCEMES-CNRS, 29 Rue Jeanne Marvig, 31055 Toulouse Cedex 4, France




Keywords:CMOSUltra-Thin-Body and Buried-Oxide Fully-Depleted-On-Insulator (UTBB FDSOI)SiGeStressStrainLayout effectsLength of diffusion (LOD)SA/SB parametersThreshold voltageMobility

a b s t r a c t

The introduction of strained channel is mandatory to achieve high performance in Ultra-Thin-Body andBuried-Oxide Fully-Depleted-Silicon-On-Insulator (UTBB FDSOI) technology. Especially, compressiveSiGe channel has been demonstrated to enhance hole mobility and therefore pMOSFETs drive currents.At the same time, the performance gain induced by this mechanical stressor comes along with layoutseffects. In this study, we characterize experimentally the impact of the active region dimensions andshape on the threshold voltage and linear drain current of SiGe channel pMOSFETs directly on insulatorfabricated for the 14 nm technology node. The pMOS threshold voltage increases by 105 mV for a gate-to-STI distance of 80 nm compared to 980 nmwhile IODLIN decreases by 51%. An analytical model is proposedto reproduce the layout dependences. The model is based on the stress profile, taking into account boththe stress from the SiGe channel and from SiGe source/drain. It reproduces the experimental data with agood accuracy in the cases of symmetric and asymmetric layouts, provided a typical relaxation length of112 nm is used. Finally, a special attention is paid on multifinger transistors, since they are widely used instandard cells designs.


1. Introduction reproduced into compact models in order to assure the functional-

The 14 nm node UTBB-FDSOI (Ultra-Thin Body and BuriedOxide – Fully Depleted Silicon On Insulator) technology highlightsa �34% delay (or +50% frequency) improvement along with a100 mV supply voltage reduction (0.8 V vs. 0.9 V) over the 28 nmFDSOI technology on a inverter ring oscillator with a fan-outFO = 3 [1]. This performance makes this technology competitivecompared to 14 nm finFET and even more flexible for multi-purpose applications, thanks to its high body-bias efficiency [1].High-speed capability is mainly achieved thanks to the introduc-tion of a high-k metal gate first, a 6 nm thin SiGe channel and SiGesources/drains in pMOSFETs. Both the SiGe channel and SiGesources/drains lead to high level of stress in the pMOSFET channel.Intrinsically, these strained channels also exhibit strong layouteffects, as evidenced in literature [2–4]. Such effects should be

ity and the performance of the designs. In this study, we character-ize and reproduce the layout dependences thanks to an analyticalmodel, which is based on measured strain profiles.

First, a special attention is paid on the level of stress induced bythe SiGe channel and SiGe sources/drains. Then, we propose ananalytical model based on the physical mechanical behavior tocapture the layout dependences. Finally, this model is used toreproduce the threshold voltage and the linear current variationsfor several layouts. Especially, asymmetric layouts of the activeregions, as well as the number of gate fingers have been investi-gated. In all configurations, the model enables to reproduce theexperimental data with a good accuracy.

2. Stress in devices

2.1. Technology summary

Studied devices are from the 14 nm UTBB-FDSOI technologydeveloped at STMicroelectronics [1]. FDSOI devices are built on a6 nm-thick silicon film on top of a 20 nm Buried-Oxide (BOX)









Table 1Elastic constants of Silicon, Germanium and Si0.75Ge0.25.

Elastic constants C11 (GPa) C12 (GPa) C44 (GPa)

Silicon 165.8 63.9 79.6Germanium 128.5 48.3 66.8Si0.75Ge0.25 156.6 60 76.4

-2

-1

0

[GPa

] =-64.3 MPa/%

R. Berthelon et al. / Solid-State Electronics 128 (2017) 72–79 73

resulting in excellent electrostatic behaviors. pMOSFETs channel ismade of Silicon-Germanium in order to boost the performancesover the 28 nm node. Devices feature TiN/HfO2 gate-first high kmetal gate integration and in-situ Boron-doped SiGe source/drain.In this study, we focus on Super-Low Threshold Voltage (SLVT) fla-vor with gate length of 20 nm, transistor width of 170 nm and acontacted poly pitch (CPP) of 90 nm.

2.2. Channel-induced stress

The integration of SiGe by the Ge-enrichment technique [5]leads to an intrinsically strained SiGe channel directly on insulator(SiGeOI) in pMOSFETs (Fig. 1). The strain comes from the latticemismatch between Silicon (aSi ¼ 5:431 Å) and Germanium(aGe ¼ 5:658 Å). After heteroepitaxy of SiGe on Silicon and conden-sation (oxidation performed at 1100 �C for 50 s), the lattice param-eter of SiGe matches the one of the underneath Silicon leading tothe in-plane strain �cc = �yy (Fig. 2).

The SiGe lattice parameter aSiGe can be expressed as a functionof the Germanium concentration in the SiGe channel x [6]:

aSiGe ¼ 5:431þ 0:2xþ 0:027x2

The in-plane strain in the SiGe film �xx is then derived from thelattice mismatch:

�xx ¼ aSi � aSiGeaSiGe

With aSi = 5.431 Å is the lattice parameter of Silicon. The rela-tionship between the strain and the biaxial stress is given byHook’s law, using elastic constants of Silicon [7].

rxx

ryy

rzz

ryz

rxz

rxy

0

B

B

B

B

B

B

B

@

1

C

C

C

C

C

C

C

A

¼

C11 C12 C12 0 0 0C12 C11 C12 0 0 0C12 C12 C11 0 0 00 0 0 C44 0 00 0 0 0 C44 00 0 0 0 0 C44

0

B

B

B

B

B

B

B

@

1

C

C

C

C

C

C

C

A

�xx�yy�zz�yz�xz�xy

0

B

B

B

B

B

B

B

@

1

C

C

C

C

C

C

C

A

SOI SiGeheteroepitaxy

Ge-enrichment

SiGeSi

BOX

Si0.75Ge0.25 6nm

20nm

SiO2

BOX

Si

BOX

Fig. 1. Scheme of the Ge-enrichment process used to obtain Si0.75Ge0.25 film directlyon insulator.

Si

Ge

a(Si0.75Ge0.25)

a(Si) BOX

SiG

eSi

Fig. 2. Strain in SiGe after Ge-enrichment due to th

The elastic constants of SiGe are different compared to the oneof pure Silicon and can be determined through Vegard’s law:

CijðxÞ ¼ CijðSiÞ þ xðCijðGeÞ � CijðSiÞÞTable 1 gives the elastic constants of Silicon, Germanium and

Si0.75Ge0.25. Finally, the biaxial stress as a function of the Germa-nium concentration is given by:

rbiaxial ¼ �ðxÞ � C11ðxÞ þ C12ðxÞ � 2C12ðxÞ2C11ðxÞ

!

and is plotted in Fig. 3. For the Germanium concentration of interest(x < 50%), a linear fit provides a satisfactory approximation.

rCH ¼ c � x with c ¼ �64:3 MPa=%

As a result, the introduction of Si0.75Ge0.25 leads to a biaxialcompressive stress of r = �1.6 GPa in the pMOSFET channel.

2.3. Stress induced by the source and drain

The global stress induced by the SiGe channel integration is notthe only source of stress in the device. The heteroepitaxy of

x

z

y

xx= yy

zz

BOX

SiO2

SiG

e

e lattice mismatch between SiGe and Silicon.

0 20 40 60 80 100-7

-6

-5

-4

-3

Linear approximationfor x<0.5

Theory

Bia

xial

stre

ss σ

Ge concentration x [%]

Fig. 3. Biaxial stress in SiGe grown on Silicon according the Germanium concen-tration x, compared to a linear approximation.

Param. Value [nm]

tpoly+tTIN+tox 21.5+3.5+3.3=28.3

tch 6

tBOX 20

tSD 18

Lgate/2+Lspa 12+9=21

LSD/2 24.5

Germanium concentrations

x 25-40%

y 20-50%

LSD/2

Lgate/2

tpoly

tch

tBOX

tSD

Si1-xGex

Si1-yGeytox

Lspa

tTiN

Fig. 4. (Left) Schematics of the simulated structure. (Right) Geometry parameters used in this study.

3

Longitudinal stress σxx [G

Pa]

2

1

0

-1

-2

-3

Fig. 5. 2D mapping of the longitudinal stress rL from finite element mechanicalsimulation with x = 25% and y = 30%.

0 10 20 30 40 50-1.0

-1.5

-2.0

-2.5

-3.0

-3.5x=25%;30%;35%;40%

Long

itudi

nal s

tress

σL [

GP

a]

y Ge concentration in raised source/drain [%]

Fig. 6. Total longitudinal stress rL in the channel at 1 nm below the gate and in themiddle of a fully strained Si1�xGex channel for different Ge concentrations y inraised source/drain.

0 10 20 30 40 500.0

-0.2

-0.4

-0.6

-0.8

-1.0

x=25%x=30%x=35%x=40%Lo

ng. s

tress

from

S/D

[GP

a]

y Ge concentration in raised S/D [%]

SSD=-15.7MPa/%

Fig. 7. Additional stress induced only by the source/drain, measured at 1 nm belowthe gate and in the middle of the gate according to the Germanium concentration insource/drain and for different Si1�xGex channel (fully strained). Linear relationshipis evidenced with sensibility SSD = �15.7 MPa/%.

74 R. Berthelon et al. / Solid-State Electronics 128 (2017) 72–79

Si1�yGey:B as Sources and Drains (S/D) of the transistor leads to anadditional stress in the channel. Using finite element mechanicalsimulations (with COMSOL software), the longitudinal stress rL

(i.e. along the h1 1 0i transport direction) in the channel has beencalculated for different Germanium concentrations in the channel(x) and in the Source/Drain (y) while the geometry of the structureremains unchanged (Figs. 4–6). The simulated structure corre-sponds to a ‘‘not isolated device” and thus consists of half a transis-tor because of symmetry plans. The channel is intrinsically strained

from Si1�xGex integration. The additional stress in the channelinduced by source and drain comes from the relaxation of SiGe:B.As the source and drain relax, the Si1xGex film underneath in thesource/drain region is under a tensile stress while the channelregion is put under compression from both sides. By varying theconcentrations x and y, it is found that the additional stress fromthe Si1�yGey source and drain does not depend on the Germaniumconcentration in the channel x (Fig. 7). This is due to the fact thatSi1�yGey source and drain are deposited on a Si1�xGex channelfeaturing the lattice parameter of Silicon, whatever its Germaniumconcentration x. Therefore, the lattice mismatch between thechannel and the source and drain only depends on theGermanium concentration in source and drain y. A good linearitybetween the additional stress and the Germanium concentrationin source/drain y is observed with proportionality coefficientSSD = �15.7 MPa/% for the considered geometry.

3. Relaxation model

3.1. Channel relaxation

The SiGe channel enrichment is processed before the patterningof the active area. The etching of the Shallow Trench Isolation (ormesa isolation) introduces a free boundary condition at the edges.

Lac=800nm

BOXd Si0.75Ge0.25

0 200 400 600 800-1.4-1.2-1.0-0.8-0.6-0.4-0.20.00.20.4

Symbols: NBD measurementsLine: model with λ=112nm α=0.124

Stra

in ε

xx [%

]

d distance along Lac [nm]

Fig. 8. Strain along a Si0.75Ge0.25 channel of active length Lac = 800 nmmeasured byNano-Beam Diffraction (NBD) and compared with the analytical model.

SA

Lac

SB

Lg =20nmDummy gate

d

Device under test

SOU

RC

E DR

AIN

Fig. 10. Typical layout of devices under test. The gate-to-STI distances SA/SBdepend on the number of dummy gate fingers.


There is thus a stress discontinuity at the edge of the SiGe film.Consequently, the compressive stress in the film tends to relax.The strain in SiGe is measured after etching by Nano-BeamDiffraction along an active length of Lac = 800 nm and considering25% of Germanium (Fig. 8). At the active border, the stress relaxesdue to the free boundary condition introduced by etching. Far fromthe active border, the SiGe channel is fully strained. The stressprofile along the active area is modeled thanks to an analyticalmodel [8]:

f ðd;LacÞ ¼ 12

1� exp �dk

� �� a

þ 1�expd� Lac

k

� �� a� �� 1=a

With d the position along the length Lac of the active region, kthe typical relaxation length and a a fitting parameter. The typicalrelaxation length l is used to reproduce the relaxation that occursover a certain distance from the edge of the active area. The stressin the SiGe channel is derived from this so-called stress function f ,according to the Germanium concentration in the channel x:

rCH ¼ rðxÞ � f ¼ c � x � fWhen the dimension of the active area is strongly reduced, the

edge effects become predominant leading to a partially strainedfilm as evidenced in Fig. 9. The model gives a good qualitativeagreement with the measured strain profile with fit parametersk = 112 nm and a = 0.124.

Lac

BOXd Si0.75Ge0.25

0.0 0.2 0.4 0.6 0.8 1.00.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

λ=112nmα=0.124

Lac=1980nmLac=540nmLac=360nm

Lac=180nm

Long

itudi

nal s

tress

σL [

GP

a]

Relative position along active d/Lac

Fig. 9. Longitudinal stress value along the active position d from the analyticalmodel for different active lengths Lac, considering x = 25%.

3.2. The effectiveness of S/D-induced stress on a (partially) relaxedchannel

The stress induced in the channel by the raised source and draindepends on the initial level of strain in Si1�yGey:B, which is directlylinked to the Germanium concentration in the source/drain y. Asseen before, because of the patterning, the SiGe channel can be par-tially relaxed. As a result, the lattice parameter in the channel is nolonger the one of Silicon. The source and drain can thus be depos-ited on a channel with a lattice parameter larger than the one ofSilicon. This lattice parameter depends on the level of relaxationof the channel. If the channel is partially relaxed, the intrinsicstrain in raised source and drain is reduced since the lattice mis-match between the channel and the source/drain is lower. In orderto take this effect into account, it is convenient to introduce theequivalent Germanium concentration yeq. yeq can be defined asthe Ge concentration in the source/drain integrated on a fullystrained channel Si1�xGex channel, for which the stress inducedby the source/drain is equivalent to the one induced by Si1�yGeyon a Si1�xGex channel under partial relaxation. This equivalent con-centration is derived from the initial Germanium concentrations xand y and using the stress function f :

yeq ¼ y� xð1� f ÞThe additional stress from the source/drain rSD is then derived

using the sensibility SSD previously extracted from simulations per-formed on ‘‘not isolated channel” and assuming the equivalentGermanium concentration in the source/drain yeq:

rSD ¼ SSDyeq

rSD ¼ SSDðy� xð1� f ÞÞIf the channel is fully strained (stress function f = 1), the stress

from the source/drain does not rely on the Germanium concentra-tion in the channel, as previously demonstrated by simulations. Inthe extreme case of a fully relaxed channel (stress function f = 0),the stress from the source/drain depends on the difference of Ger-manium concentrations in the source/drain and in the channel (i.e.y� x). For short active length, the channel can be partially relaxed(see Fig. 9). In this intermediate case, the stress from source/drainis linked to the level of relaxation of the channel.

Finally, the total longitudinal stress in the Si1�xGex channeltransistor with Si1�yGey source/drain at a position d along an activeregion of a total length Lac is:

rLðd; Lac; x; yÞ ¼ cxf ðd; LacÞ þ SSDðy� xð1� f ðd; LacÞÞÞ

0 25 50 75 100 125 150-12

-10

-8

-6

-4

-2

0

2

Δμ/ μ

= Δ

I D/I D

[%]

Applied long. tensile stress [MPa]

L=10µm

x=25%

x=0%

Fig. 11. Piezoresistive coefficients extraction from hole mobility relative variationaccording to the applied longitudinal tensile stress for two different initialGermanium concentration.

<110>/(100)

0.0 -0.5 -1.0 -1.5 -2.00

1

2

3

4

5

6

Hol

e m

obili

ty ra

tio

Longitudinal compressive stress σL [GPa]

Fig. 12. Model of hole mobility ratio in a SiGe channel vs. its longitudinalcompressive stress.


For short channels, the longitudinal stress can be considered asthe one at the middle of the channel since the channel length is sig-nificantly lower than the active length. For instance, the longitudi-nal stress in the middle of a Si0.75Ge0.25 channel with a gate lengthof 20 nm, located in the middle of an active length Lac = 0.36 lm,with Si0.7Ge0.3:B source/drain is rL = �1.7 GPa, assuming a typicalrelaxation length of k = 112 nm. In this case, 75% of the longitudinalstress comes from the channel (corresponding to rCH component)and 25% from the source/drain (corresponding to rSD component).

4. Layout effect and corresponding model

In this section we investigate the layout effects relative to thegate-to-STI distances SA/SB (also called the length of diffusionLOD) on short channel devices (Lg = 20 nm, see Fig. 10). Thestress value of interest is taken at the middle of the channel(d = SA + Lg/2), which is a relevant approximation for short chan-nels. The active length is Lac = SA + SB + Lg. The value of SA andSB varies according to the number of dummy gates fingers on theactive region, with a Contacted-Poly-Pitch (CPP) of 90 nm. Themeasurement of transistors with various dummy gates thusenables to characterize the layout effects linked to the longitudinalstress, while other layout parameters remain unchanged. Espe-cially, the gate length Lg is kept constant and the source/drainregions are in a similar configuration (i.e. SiGe:B in between twogates) whatever the number of dummy gate fingers of the layout.

In this study, we focus on two relevant electrical parametersimpacted by the stress: the threshold voltage VT, extracted at aconstant current, and the IODLIN drain current in linear regime(measured at a drain voltage of |VD| = 50 mV and at a given over-drive |VG � VT| = 0.5 V). IODLIN is influenced by the hole mobilityin the channel and the series resistance.

In order to understand and interpret our experimental results,we have built an analytical model. In this model, the link betweenthe longitudinal stress and the threshold voltage is established by afirst order linear sensibility of SVT = �113 mV/GPa. This sensibilityis consistent with the valence band shift used in Ref. [9] and calcu-lated from Ref. [10], in case of biaxial stress (DEV = 103 mV/GPa).

Regarding the mobility, we use the piezoresistive model to pre-dict the mobility variation according to the level of longitudinalstress:

dll

¼ �PLdrL

With l being the hole mobility, PL the longitudinal piezoresis-tive coefficient in the h1 1 0i channel orientation and rL the longi-tudinal stress. After integration, the mobility can thus be calculatedas:

lðrLÞlðrL ¼ 0Þ ¼ exp

Z rL

0�PLðsÞds

� �

This model requires the knowledge of the evolution of the lon-gitudinal piezoresistive coefficientPL with the level of initial stressin the device r. For the stress range of interest, we use the piezore-sistive coefficients extracted on long channels (Lg = 10 lm) atr = 0(h1 1 0i Si channel) and at r = �1.6 GPa (h1 1 0i SiGe with x = 25%),which are PLð0Þ = 0.56 GPa�1 and PLð�1:6Þ = 0.74 GPa�1 respec-tively (Fig. 11).

From these measurement, the evolution of PL with rL isassumed as linear. The relative sensibility can be calculated asK = �0.11 GPa�2, and the final model of mobility enhancementgiven by:

lðrLÞlðrL ¼ 0Þ ¼ exp �PLðrL ¼ 0Þ � rL �K

2r2

L

� �

The mobility ratio from this analytical model is represented inFig. 12.

Finally, the IODLIN current model and threshold voltage modelare given by:

IODLIN ¼ Id0 exp �PLrL �K2r2

L

� �

VT ¼ VT;0 þ SVTrL

With Id0 and VT;0 being respectively the IODLIN current andthreshold voltage of a device which is unstrained in the longitudi-nal direction.

5. Experimental results

5.1. Symmetric layouts

Layouts are called symmetric if SA = SB. In this configuration,the gate-to-STI distance from the source side is equal to the onefrom the drain side. The nMOS threshold voltage VT, extracted ata constant current of 300 nA �W/L with VD = 50 mV, as well asthe drain current IODLIN, measured at a constant overdrive|VG � VT| = 0.5 V are shown in Fig. 13 for symmetric layouts with

250

300

350

400V T [

mV

]nMOS W=170nm Lg=20nm

I OD

LIN [ μ

A/μ

m]

0 200 400 600 800 1000100

150

200

SA=SB [nm]

a

b

Fig. 13. (a) Threshold voltage VT and (b) IODLIN drain current of nMOS for symmetriclayouts, as a function of SA = SB. Gate length is Lg = 20 nm, channel width isW = 170 nm and VT flavor is SLVT.

0 200 400 600 800 10000

-50

-100

-150

-200

-250

Symbols:exp.Lines:model

pMOS W=170nm Lg=20nm

I OD

LIN [ μ

A/μ

m]

SA=SB [nm]

Id0=-42.8µA/µmλ=112nmα=0.124

Fig. 15. pMOS IODLIN drain current for symmetric layouts, as a function of SA = SB.Gate length is Lg = 20 nm, channel width is W = 170 nm, VT flavor is SLVT andGermanium concentrations are x = 25% and y = 30%.

0 200 400 600 800 1000-150

-200

-250

-300

-350

-400

-450

SB=980nm

SB=80nm

symbols:exp.lines:model


VT,0=-0.489Vλ=112nmα=0.124Thre

shol

d vo

ltage

VT [

mV

]

SA [nm]

Fig. 16. pMOS threshold voltage VT for asymmetric layouts as a function of SA andfor SB fixed at either SB = 980 nm or SB = 80 nm. Gate length is Lg = 20 nm, channelwidth is W = 170 nm, VT flavor is SLVT and Germanium concentrations are x = 25%and y = 30%.

0 200 400 600 800 1000 1200-150

-200

-250

-300

-350

-400

-450


pMOSW=170nmL=20nm

VT,0=-0.489Vλ=112nmα=0.124

Thre

shol

d vo

ltage

Vth [m

V]

SA = SB [nm]

Fig. 14. pMOS threshold voltage VT for symmetric layouts, as a function of SA = SB.Gate length is Lg = 20 nm, channel width is W = 170 nm, VT flavor is SLVT andGermanium concentrations are x = 25% and y = 30%.


different gate-to-STI values SA = SB. No layout-dependence isobserved since VT and IODLIN are constant whatever the activelength. This result is expected since the nMOS features unstrainedsilicon channel. It also confirms that the STI does not induce anystress into the device. Figs. 14 and 15 show the pMOS VT (extractedat a constant current of 70 nA �W/L with VD = �50 mV) and IODLIN,respectively, as a function of SA = SB. The pMOS threshold voltageincreases by 105 mV from SA = SB = 980 nm to SA = SB = 80 nmwhile IODLIN decreases by 51%. The change in threshold voltageand mobility comes from the relaxation of the SiGe stress in thechannel that occurs at the active/STI frontiers. For short activeregions, the channel is partially relaxed and thus the electricalcharacteristics are impacted. These layout-dependences are repro-duced with a good accuracy by our aforementioned stress-basedmodel with a typical relaxation length k of 112 nm.

5.2. Asymmetric layouts

The layout effects are also characterized for asymmetric layouts,with different gate-to-STI distances between source and drainsides. In such layouts with SA– SB, the distance with the activeborder on drain side, SB, is fixed at either SB = 980 nm orSB = 80 nm. These asymmetric layouts enable to characterize the

proximity effect of one active border only. Fig. 16 shows thethreshold voltage variations for asymmetric layouts. Similarly tosymmetric layouts, the proximity of the active border leads tothreshold voltage increase. The threshold voltage is directly limitedby the shorter gate-to-STI distance. A VT shift of 54 mV is foundbetween SB = 980 nm and SB = 80 nm while SA = 980 nm. This VT

shift is due to the stress relaxation on the active border of the drainside only and is approximately half the VT shift induced by theproximity of two edges (54 mV vs. 105 mV). IODLIN is similarlyimpacted as demonstrated in Fig. 17. IODLIN is also strongly limitedby the shorter gate-to-STI distance and decreases by 30% betweenSB = 980 nm and SB = 80 nm while SA = 980 nm. Both VT and IODLINvariations for asymmetric layouts are well reproduced by our ana-lytical model, provided a = 0.124 as a value of the asymmetryparameter.

5.3. Multifinger transistors

In a design, transistors can be built on a same active area. Espe-cially, multifinger MOSFETs consist of different transistors in paral-lel and on the same active region, sharing source and drain nodesas illustrated in Fig. 18. Such layouts are particularly efficient toenhance the drivability of standard cells. In this configuration, each

0 200 400 600 800 1000-50

-100

-150

-200

Id0=-42.8µA/µmλ=112nmα=0.124

Symbols:exp.Lines:model


SB=80nm

SB=980nm

I OD

LIN

[μA/

μm]

SA [nm]

Fig. 17. pMOS IODLIN drain current for asymmetric layouts as a function of SA andfor SB fixed at either SB = 980 nm or SB = 80 nm. Gate length is Lg = 20 nm, channelwidth is W = 170 nm, VT flavor is SLVT and Germanium concentrations are x = 25%and y = 30%.

0 5 10 15 20 25-200

-250

-300

-350

-400

VT,0=-0.489Vλ=112nmα=0.124SS=80mV/dec

Multifinger

1 active gate(SA=SB test structure)



Thre

shol

d vo

ltage

VT [m

V]

Number of gates (dummy or not)

Fig. 19. Threshold voltage of multifinger pMOS as a function of the number of gates.Gate length is Lg = 20 nm, channel width is W = 170 nm, VT flavor is SLVT andGermanium concentrations are x = 25% and y = 30%.

160

180

2001 active gate (SA=SB)


]


elementary transistor of multifinger MOSFETs is unique because ofa unique set of gate-to-STI distances SAi/SBi. Indeed, the stressrelaxation occurring at the active borders will affect each fingerdifferently. Therefore, the level of stress in the channel of each fin-ger directly depends on its position.

In order to derive the threshold voltage VT according to thenumber of fingers Nf, we consider the Nf transistors built in paralleland for a conduction in the subthreshold regime (no impact of driftcurrent):

VTðNf Þ ¼ �SS= lnð10Þ ln 1Nf

X

Nf

i¼1

exp�VTðSAi; SBiÞSS= lnð10Þ

� �

!

with SS the subthreshold swing of the tested devices (considered inthe following to be 80 mV/decade). A good agreement betweenmodel and experimental data is observed (Fig. 19). Multifinger dataare compared to the 1-finger transistor reference (data fromFig. 14), located at the middle of the active area (this time, the restof the gates are dummies, as previously illustrated in Fig. 10). Thisresult highlights the impact of the fingers close to the active border,slightly increasing the threshold voltage of the whole structure(+17 mV at Nf = 11 fingers). However, one can see that the globalVT of multifinger devices can be well approximated by the VT ofthe central transistor. This is because this latter is the minimumVT of all the devices in parallel and the minimum VT governs thetotal VT.

Same methodology is applied to estimate IODLIN of multifingerstransistors. However, in such designs, the different fingers are notat the same gate voltage overdrive VG � VT since fingers feature

SB1SA1

SB3SA3

DRAIN

SOURCE

Fig. 18. Illustration of multifinger transistors layout built in parallel (in thisexample, the number of finger is Nf = 5). Each elementary transistor exhibitsdifferent gate-to-STI distances SA/SB.

different threshold voltages according to their gate-to-STI dis-tances (SAi/SBi). A simple model of linear drain current can be usedin order to take into account the overdrive shift for each finger:

IDðVGÞ ¼ bjVG � VT j

1þ h1jVG � VT jAt |VG � VT| = VGT0 = 0.5 V, ID = IODLIN. Thus, ID can be written as

a function of IODLIN:

IDðSA; SBÞ ¼ IODLINðSA; SBÞ � VGT

VGT0� 1þ h1jVGT0j

1þ h1jVGT j� �

The parameter h1 = 0.3 is used in the following because it repro-duces well our experimental ID(VG) curves. Finally, IODLIN of multi-fingers is measured at |VG � VT(Nf)| = VGT0, with VT(Nf) previouslydescribed, and can thus be calculated following:

IODLINðNf Þ ¼ 1Nf

X

Nf

i¼1

IDðSAi; SBiÞ

The multifinger pMOS IODLIN is shown in Fig. 20. Our model oftransistors in parallel well reproduces the experimental data, pro-vided an additional series resistance of 10 Ohm considered forNf > 10. This additional resistance may be linked to wires/contactin our structure since it also affects multifinger nMOS IODLIN(Fig. 21). The multifinger transistor is compared to the 1-finger ref-

0 5 10 15 20 25

60

80

100

120

140

Id0=-42.8μA/μmλ=112nmα=0.124θ1=0.3

Multifinger

Symbols: exp.Lines: models

I OD

LIN [μ

A/μ

m

Number of gate (dummy or not)

Fig. 20. Multifinger pMOSFETs IODLIN as a function of the number of fingers,compared to a single-finger pMOS lied on an active regions of the same dimensions.Gate length is Lg = 20 nm, channel width is W = 170 nm, VT flavor is SLVT andGermanium concentrations are x = 25% and y = 30%.

0 5 10 15 20 25

100

120

140

160

180

200

w/o Radd

Radd=10Ω

Symbols: expLine: model

nMOS W=170nm Lg=20nmI O

DLI

N [ μ

A/μm

]

Number of fingers

Fig. 21. Multifinger nMOSFETs IODLIN drain current as a function of the number offingers with or without an additional series resistance of 10 Ohm. Gate length isLg = 20 nm, channel width is W = 170 nm, VT flavor is SLVT.


erence with same active length (SA = SB in Fig. 10, data fromFig. 15). The multifinger design is more sensible to the single-finger design (for a given active dimension), this because the fin-gers close to the active border lowers IODLIN in the former case.Especially, IODLIN is 13% lower for multifinger at Nf = 11 than forsingle-finger layout, this, due to the fingers located close to theactive/STI frontier.

6. Conclusion

In this study, we investigate the layout effects induced by theSiGe channel in the pMOSFETs of the 14 nm UTBB-FDSOI technol-ogy. The threshold voltage and the linear drain current are charac-terized vs. the active dimensions (length) and position of the gate.This layout effect is induced by the stress relaxation on the activeborders (active/isolation frontier) that occurs during the isolationpatterning. An analytical model based on the stress profile is pro-posed to reproduce the threshold voltage and linear drain currentdependences with layouts. This model takes into account both the

intrinsic stress from the SiGe channel and the additional stressfrom the source/drain. Mechanical simulations as well as physicalcharacterizations enable us to extend this model to a wide range ofGermanium content and layout configurations. Finally, a goodagreement is found with experimental data for both symmetricand asymmetric layouts. Multifinger transistors (i.e. transistorswith multiple gates connected in parallel and put on a same activeisland) have also been characterized and modeled as they arewidely used in standard cells designs, demonstrating the strongimpact of gate fingers close to the active borders.

Acknowledgements

This work was partly supported by the Catrene Dynamic-ULP,Places2be KETs and Nano2017 projects, through the French min-istry of Industry.

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[2] DeSalvo B, Morin P, Pala M, Ghibaudo G, Rozeau O, Liu Q, et al. A mobilityenhancement strategy for sub-14 nm power efficient FDSOI technologies. In:IEEE IEDM. p. 7.2.1–4.

[3] Cheng K, Khakifirooz A, Loubet N, Luning S, Nagumo T, Vinet M, et al. Highperformance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFETand strained SiGe channel PFET. In: IEEE IEDM. p. 419.

[4] Andrieu F, Cassé M, Baylac E, Perreau P, Nier O, et al. Strain and layoutmanagement in dual channel (sSOI substrate, SiGe channel) planar FDSOIMOSFETs. In: Proc of ESSDERC conference. p. 106–9.

[5] Glowacki F, Le Royer C, Morand Y, Pédini J-M, Denneulin T, Cooper D, et al.Ultrathin (5 nm) SiGe-On-Insulator with high compressive strain (�2 GPa):from fabrication (Ge enrichment process) to in-depth characterizations. Solid-State Electron 2014;97:82–7.

[6] Dismukes JP, Ekstrom L, Steigmeier EF, Kudman I, Beers DS. Thermal andelectrical properties of heavily doped Ge-Si alloys up to 1300 K. J Appl Phys1964;35:2899.

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[8] Poiroux T et al. In: MOS-AK workshop, Grenoble; 2015.[9] Rieger MM, Vogl P. Electronic-band parameters in strained Si1�xGex alloys on

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investigation of hole transport in strained Si1�xGex/SOI pMOSFETs: part I –scattering mechanisms in long channel devices. IEEE Trans Electron Dev2011;59(2):316–25.










































Back-gated InGaAs-on-insulator lateral N+NN+ MOSFET: Fabrication andtypical conduction mechanisms

http://dx.doi.org/10.1016/j.sse.2016.10.0190038-1101/� 2016 Published by Elsevier Ltd.

⇑ Corresponding author.E-mail address: [email protected] (H.J. Park).

H.J. Park a,⇑, L. Pirro a, L. Czornomaz b, I. Ionica a, M. Bawedin a, V. Djara b, V. Deshpande b,S. Cristoloveanu a

a IMEP-LaHC, Minatec, Grenoble INP, Univ. Grenoble Alpes, CNRS, Grenoble, Franceb IBM Research, Ruschlikon, Switzerland




Keywords:III–VInGaAsSOIpseudo-MOSFETMOSFETWafer bondingCarrier mobilityStrainSelective regrowth

Back-gated InGaAs-on-insulator lateral N+NN+ MOSFETs are successfully fabricated by direct wafer bond-ing and selective epitaxial regrowth. These devices were characterized using a revisited pseudo-MOSFETconfiguration. Two different transport mechanisms are evidenced: volume conduction in the undepletedregion of the film and surface conduction at the interface between InGaAs and buried insulator. We pro-pose extraction techniques for the volume mobility and interface mobility. The impact of film thickness,channel width, and length is evaluated. Additional measurements reveal the variation of the transistorparameters at low temperature and under externally applied uniaxial tensile strain.

� 2016 Published by Elsevier Ltd.

1. Introduction

The extension of Moore’s law is based on two pillars: (i) electro-static integrity of small transistors and (ii) improvement of trans-port properties for high speed. Only fully depleted devices, suchas FinFETs, planar SOI or nanowires, benefit from excellent controlof the gate on the channel, leading to attenuated short-channeleffects and leakage current. Technology-wise, Semiconductor onInsulator (SOI) is the most straightforward, and pragmaticapproach. Mobility boosters consist in adding strain, selecting thecrystal orientation or, more drastically, replacing silicon with moretalented semiconductors [1–5].

According to ITRS predictions [6], high-mobility channel mate-rials such as Ge, SiGe and III–V compounds are promising candi-dates for the next generations of MOSFETs, able to deliver thenecessary power-performance benefits and added functionalityfor CMOS and System-on-Chip applications [7–9]. Furthermore,devices fabricated on semiconductor-on-insulator substrates havebetter electrostatic control with decreased short channel effects

and reduced leakage current [10–12]. Merging the merits of III–Vcompounds and SOI is a recent option explored as starting sub-strate (III–V on insulator) for device fabrication. In particular,InGaAs-on-insulator structures are attractive [13] to integratehigh-performance FinFETs [14], planar MOSFETs on insulator andhybrid InGaAs/SiGe CMOS circuits [15]. This technology is rapidlyevolving. Nevertheless, InGaAs-on-insulator films are prone toadditional carrier scattering, compared to layers grown on bulkcrystalline buffers such as InP [16] or InAlAs [17], owing to thepresence of the buried oxide (BOX) and related back interface.

Our work is focused on the technological optimization viadetailed investigation of transport properties in simple testdevices. In0.53Ga0.47As layers transferred on oxide were character-ized using a modified version of the well-known pseudo-MOSFET(W-MOSFET) configuration [18]. Lateral N+NN+ structures havebeen fabricated on InGaAs-on-insulator layers to mimic the chan-nel transport of a MOSFET while minimizing the impact ofprocess-induced damages. Section 2 presents the main processingsteps [19]. The measurement set-up and typical transistor charac-teristics are shown in Section 3. A suitable procedure, based on theextension of Y-function technique, is proposed in Section 4 forextracting the electron mobility in the film volume and at the







H.J. Park et al. / Solid-State Electronics 128 (2017) 80–86 81

interface. We discuss the carrier mobility as a function of filmthickness, temperature from 77 K to 300 K, and uniaxial tensilestrain.

2. Material and device processing

The fabrication of back-gated lateral N+NN+ transistors utilizessome of the key steps developed for InGaAs FinFETs [15]. Thecharacteristics are expected to be representative of those infully-processed devices with back-gate operation. The n-layer is anon-intentionally doped InGaAs-on-insulator (InGaAs-OI) grownin a metal organic vapor phase epitaxial reactor. InGaAs-OIlayers on Si which have an initial doping concentration ofND � 2 � 1017 cm�3 are prepared by direct wafer bonding ofnominally-undoped In0.53Ga0.47As films of varying thickness(25 nm, 50 nm, 100 nm and 200 nm) grown on InP wafers asdescribed in [20]. The carrier concentration measured by Hall Effecton a 200-nm-thick InGaAs on InP layer before bonding is of 2–3 � 1016 cm�3. The buried oxide (BOX) consists of 25 nm thermalSiO2, 10 nm Al2O3 and the high-k dielectric stack used in [14], fora resulting C BOX of 0.11 lF/cm2.

The fabrication of lateral N+NN+ structures starts with the depo-sition of a SiO2 hard-mask to define the length of the n-region(Fig. 1(a)). Sn-doped In0.53Ga0.47As N+ regions (ND = 5 � 1019 cm�3)are selectively grown (Fig. 1(b)) at low temperature as in [21]. Thehard-mask is removed (Fig. 1(c)) and a mesa isolation is performedby wet etching (Fig. 1(d)). The top interface of the n-region isformed with same high-k dielectric as used for the bottom inter-face. The process is completed by the deposition of a SiO2 layer(Fig. 1(e)), etching via holes and W metal contacts (Fig. 1(f)). Itshould be noted that although the bottom and top InGaAs/high-kinterfaces are formed with the same deposition process, they differin the fact that the bottom interface is exposed to the thermal bud-get of the N+ selective epitaxial process, contrary to the top inter-face. This leads to a difference in the interface trap density

Fig. 1. Schematic processing sequence of lateral N+NN+ test structure: (a) SiO2

hardmask on InGaAs-OI layer with bottom passivation, (b) growth of N+ InGaAscontacts, (c) hardmask removal, (d) mesa wet etching, (e) top passivation andinterlayer dielectric deposition, (f) contact vias and metallization.

comparable that the difference between Gate-first andReplacement-metal-gate devices in [14].

Fig. 2 shows the schematic of the tested structures. The draincurrent variation with drain bias confirms the ohmic behavior ofthe contacts.

3. Current and transconductance characteristics

The device characterization was performed by sweeping thegate bias VG applied on the substrate and measuring the resultingdrain current (ID) between source and drain contacts. This deviceis similar to Pseudo-MOSFET (W-MOSFET) [22], where the stan-dard pressure-adjustable probes are replaced by implanted N+

source and drain regions. This configuration is preferable becausethe impact of series resistance and probe-induced defects on themobility is reduced. The channel dimensions are also better

Fig. 2. Measured drain current ID versus drain bias VD for gate bias VG = 0,L = 200 lm and W = 20 lm.

Fig. 3. Back-gate ID � VG characteristics of lateral N+NN+ InGaAs-OI structures for(a) 25 nm, (b) 50 nm, (c) 100 nm and (d) 200 nm thick InGaAs film. Note thetransition from full depletion (a) to partial depletion (d).

10

15

20

25

I D (μ

A)

VG (V)

ID

L=200μmVD=200mV

0.0

0.5

1.0

1.5

2.0 gm

gm (μS)

-8 -4 0 4 8

1.5

2.0

(a)

(b)

82 H.J. Park et al. / Solid-State Electronics 128 (2017) 80–86

defined by the inter-contacts distance, representing the channellength L and width W.

3.1. Drain current

Transfer characteristics are reported in Fig. 3 for transistorswith variable InGaAs channel thickness. All devices present a mod-ulation of the drain current with gate voltage, the degree of whichdepends on thickness. For positive VG, the field effect induces theformation of an accumulation region at the film-BOX interface,whereas for negative VG, the film is subject to depletion. The thin-ner channel (Fig. 3a) shows the typical signature of full-depletionoperation: very low leakage current, high ON/OFF current ratio, rel-atively steep subthreshold slope. These parameters tend to degradein thicker films (Fig. 3b and c), albeit the ON current increases. The200 nm thick InGaAs transistor (Fig. 3d) operates at the limit ofpartial depletion since the drain current saturates and remainshigh for increasingly negative gate voltage.

Fig. 5. (a) On-resistance RON versus channel length Lg extracted at VG = 8 V andVDS = 50 mV for four different InGaAs-OI thickness. (b) Sheet resistance Rsheet

deduced from (a) versus InGaAs film thickness fitted by a two parallel conductancemodel.

-8 -4 0 4 8-1.5

-1.0

-0.5

0.0

0.5

1.0

VFBδ g

m/δ

V G (S

/V)

VG (V)

VT

Fig. 6. (a) Drain current ID (plain symbols) and transconductance gm (emptysymbols) versus gate bias. The dashed line represents the ‘volume’ current IVol. (b)Corresponding gm derivative versus VG, which features a double threshold voltagebehavior. tIII-V = 200 nm and W = 20 lm.

Fig. 4. Minimum subthreshold swing (SS) versus channel length (L) for devices withInGaAs film thickness of 25 nm, 50 nm, 100 nm, and 200 nm.

-8 -4 0 4 80

1

2

3

4

5

6

7

I D (μ

A)

VG (V)

ID

L=200μmVD=200mV

0.0

0.5

1.0

gm

gm ( μS)

Fig. 7. Drain current ID (plain symbols) and transconductance gm (empty symbols)versus gate bias in 25 nm thick InGaAs film with W = 20 lm.

Fig. 8. Drain current ID versus gate bias VG in 200 nm thick devices with differentwidths. L = 200 lm, VD = 200 mV.

0

250

500

750

1000

1250

1500

1750

μ Vol (

cm2 /V

.S)

W = 2.5um W = 5um W = 10um W = 20um

(a)


The gradual change from full depletion to partial depletion isalso reflected by the variation of the subthreshold swing (SS) withthickness: SS increases massively in 200 nm film (Fig. 4).

Fig. 5(a) shows the ON-resistance which varies linearly with thechannel length. Extrapolation of these curves to L = 0 indicates thatall samples have a similar contact resistance (about 5 kX lm),which is rather low for InGaAs-OI samples thanks to the optimizedprocess of the source/drain terminals. The slope of the linesindicates the sheet resistance of the film (measured at VG = +8 V),which strongly depends on thickness as illustrated in Fig. 5(b). Thiscurve can be modeled by considering two parallel conductionchannels [23].

10010L (μm)

100100

50

100

150

200

250

300

μ Vol (

cm2 /V

.S)

L (μm)

tIII-V = 50 nm tIII-V = 100 nm tIII-V = 200 nm

500

750

1000

1250

1500

1750

2000

μ Vol (

cm2 /V

.S)

μVol (IdVg)μVol (Yvol)

(b)

(c)

3.2. Transconductance

Fig. 6(a) shows the drain current ID (plain symbols) and associ-ated transconductance gm (empty symbols) versus gate bias inthick InGaAs film (200 nm). A plateau is visible in ID(VG) curve forVG � 0 and the gm(VG) characteristic features two unusual peaks.It is known that in conventional MOSFETs the derivative of thetransconductance with respect to gate bias yields one peak, theposition of which indicates the threshold voltage [22]. In our sam-ples, there are two clear peaks (see Fig. 6(b)) which give evidencefor a double conduction mechanism in the III–V film. Since thefilms are doped, volume conduction is possible even in absenceof VG. A negative gate bias induces a depletion region at the film-BOX interface, which modulates the thickness of the conductionvolume. The left peak in Fig. 6(b), obtained for negative gate bias,indicates the threshold voltage VT. This means that for VG > VT,the depletion region starts to shrink. The right peak correspondsto the flat-band voltage VFB that defines the onset of the accumula-tion channel [12]. Beyond flat-band voltage (VG > VFB � +1.1 V), anaccumulation channel forms at the InGaAs-BOX interface and addsto the volume conduction. We call these mechanisms ‘volume’conduction and ‘surface’ conduction.

The double-peakshape of the transconductance evolves to asingle-peak in very thin films where the contribution of the neutralvolume to drain current tends to vanish. For 25 nm thick film, thesecond peak of transconductance is hardly visible as shown inFig.7.

10010L (μm)

Fig. 10. Extracted volume mobility versus channel lengths in (a) 200 nm thick filmswith variable width and (b) narrow devices of 2.5 lm with different thickness. (c)Comparison of volume mobility values extracted from ID(VG) curves with Eq. (2) orby using Yvol-function method (Eq. (8)). W = 10 lm, tIII-V = 200 nm, VD = 200 mV.

4. Mobility extraction

4.1. Partial and full depletion

Before attempting to extract the mobility, we need to evaluatewhether the films are fully depleted or not. Given a doping level

-8 -6 -4 -2 00.0

5.0m

10.0m

15.0m

20.0m

25.0m

30.0m

Y-fu

nctio

n (A

/S0.

5 )

VG (V)

L = 200um L = 150um L = 100um L = 50um L = 20um L = 10um L = 5um

Fig. 9. Y-function in depletion regime Yvol(VG) for 200 nm thick InGaAs devices withdifferent gate lengths, W = 10 lm, VD = 200 mV.

-4 -3 -2 -1 00.0

500.0

1.0k

1.5k

2.0k

g m-1

/2 (S

-0.5)

VG (V)

L = 200um L = 150um L = 100um L = 50um L = 20um L = 10um L = 5um

Fig. 11. Plot of 1=ffiffiffiffiffiffiffi

gmp

versus VG in volume conduction (on right region). The dottedline shows the linear fit with Eq. (10) in order to determine coefficient h1 and theseries resistance. W = 10 lm, tIII-V = 200 nm.

100100

200

400

600

800

μ s (cm

2 /V.S

)

L (μm)

L (μm)

W = 2.5um W = 5um W = 10um W = 20um

100100

50

100

150

200

250

300

tIII-V = 50 nm tIII-V = 100 nm tIII-V = 200 nm

μ s (cm

2 /V.S

)

(a)

(b)

Fig. 13. Extracted surface mobility versus gate length in (a) 200 nm thick deviceswith different widths, and (b) narrow devices with variable thickness.

-8 -4 0 4 80.0

0.5

1.0

1.5

2.0

2.5T = 77 KT = 130 KT = 200 KT = 300 K

I D (μ

A)

T

(a)


ND, it is possible to compute the maximum width Wd_max of thedepletion region in the InGaAs film [24]:

Wd max ¼

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

4 � eIII�V � k � T � ln NDni

� �

q2 � ND

v

u

u

t ð1Þ

where eIII-V and ni are the InGaAs dielectric constant and the intrin-sic doping concentration. According to the film quality, eIII-V canvary between 13.1�e0 and 14.1�e0 [25], where e0 is the vacuumpermittivity.

Considering ni = 6.3 � 1011 cm�3 [25], the maximum depletionwidth is between 197 nm and 205 nm, which means that filmsthinner than 200 nm are definitely fully depleted. In contrast, the200 nm thick layer is at the boundary between partial and fulldepletion. Fig. 8 reports the measured ID(VG) curves in thick deviceswith same length (L = 200 lm) and different widths. Wide transis-tors are clearly partially depleted with large ID current flowing inthe undepleted region of the film. But, interestingly, the narrowerdevice (W = 2.5 lm) exhibits full depletion, suggesting a 2D mech-anism [26]: the lateral depletion, assisted by defects and chargeslocated on the sidewalls, reinforces the vertical depletion inducedby the gate.

4.2. Volume mobility

According to the approach developed by Liu et al. [27] for heav-ily doped Si layers, the drain current in volume conduction regimecan be written as:

ID ¼ WL� CBOX � lVol � VD � ðVG � V0Þ ð2Þ

where CBOX is the buried oxide capacitance [19] and V0 is a charac-teristic voltage which may enable full depletion of the channel [27]:

V0 ¼ VFB þ q �ND

CBOX� tIII � V ð3Þ

Nd is the active doping concentration. Eq. (2) accounts for the thick-ness variation of the neutral (undepleted) region with gate bias. Inhighly doped, partially depleted films, V0 is hypothetical, as it can-not be reached experimentally; it is extrapolated from the measure-ments. In principle, the volume mobility lVol is independent on gatebias unless the film has to be inhomogeneous with vertical profilesof mobility, defects and dopants. It may also depend on the verticalfield induced by surface charges, in particular when the neutralregion becomes very thin. The device ON-resistance includes thecontribution of the series source/drain resistance RSD:

0 2 4 6 80

1

2

3 L = 200 μm L = 150 μm L = 100 μm L = 50 μm

Y-fu

nctio

n (m

A/S

0.5 )

Gate Bias (V)

LSlope

Fig. 12. YS-function in accumulation regime YS (VG) for W = 20 lm, tIII-V = 200 nmthick InGaAs devices with different gate lengths.

VG (V)

(b)

Fig. 14. (a) Drain current as a function of gate bias measured at variabletemperature. (b) Associated variations of subthreshold swing S and flat-bandvoltage VFB with low temperature T. For tIII-V = 25 nm, W = 5 lm, and L = 100 lm ofInGaAs device.

Fig. 15. (a) Schematic of 3-point bending configuration used to apply uniaxialtensile strain on the sample. (b) Picture from the side of the 3-point bending setupshowing the semiconductor layer under tensile strain and the contact probes.

Fig. 16. Improvement rate of ION (at Vg = 8 V) versus uniaxial tensile strain fordifferent InGaAs-OI thicknesses.


RON ¼ VD

ID¼ RSD þ L

W � CBOX � lVol � ðVG � V0Þ ð4Þ

Rewriting ID, we obtain:

ID ¼ WL� CBOX � lVol

1þ h1ðVG � V0Þ � ðVG � V0Þ � VD ð5Þ

where

h1 ¼ RSD � lVol � CBOX �WL: ð6Þ

The transconductance is:

gm ¼ @ID@VG

¼ WL� CBOX � lVol

½1þ h1ðVG � V0Þ�2� VD ð7Þ

This equation explains the transconductance variation withgate voltage in volume conduction regime. Since the difference(VG � V0) can be very significant, especially for thick films, thetransconductance decay with VG is abrupt, as shown in Fig. 6(a).It follows that the volume mobility extracted from either Eq. (2)or transconductance peak is highly underestimated due to the ser-ies resistance effect. This problem can be circumvented by con-structing a Y-function:

YVol ¼ IVolffiffiffiffiffiffi

gmp ¼

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

WL� CBOX � lVol � VD

r

� ðVG � V0Þ ð8Þ

where the impact of RSD is erased.Drawing YVol versus VG results in a straight line region, more

pronounced in long devices (Fig. 9). The intercept with the horizon-tal axis yields V0, and the slope gives the volume mobility:

lVol ¼Slope2

WL � CBOX � VD

ð9Þ

This methodology is similar to the Y-function technique used ininversion-mode MOSFETs [28] except that lVol and V0 have differ-ent meaning.

The extracted lVol (Fig. 10(a)) is rather constant with the gatelength L. The volume mobility reaches 1200 cm2/V s in thick andwide devices (Fig. 10(a)). Net mobility degradation is noticed in25–50 nm thick films and also in narrow devices (Fig. 10(a) and (b)), where carrier scattering on the sidewalls comes intoplay. Fig. 10(c) compares the volume mobility extracted fromID(VG) curves with Eq. (2) and from YVol-function. The latter methodis not affected by source and drain series resistance and provides atleast 40% higher mobility. The series resistance is included incoefficient (see Eq. (6)) which can be determined from the slopeof 1/

pgm versus VG curve:

1ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

gmðVGÞp ¼ 1þ h1 � ðVG � V0Þ

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

CBOX � WL � lVol � VD

q ð10Þ

Fig. 11 confirms the linear variation of 1/ffiffiffiffiffiffiffi

gmp ðVGÞ curves in vol-

ume conduction mode. Using this method (Eq. (10)), the extractedcoefficient h1 is around 0.5 V�1 for all devices, which implies thatthe series resistance increases in longer channels.

4.3. Surface mobility

Surface conduction occurs for VG > VFB, when the accumulationchannel starts forming at the film-BOX interface and adding to thevolume current flowing in the whole neutral film. The surface cur-rent is given by the difference between the total current ID and themaximum volume current IVol,m measured at VG = VFB (see dashedline in Fig. 6(a)). The surface mobility lS at the film-BOX interfaceis obtained from another version of the Y-function (YS) adapted tothe accumulation current [28]:

YS ¼ ID � IVolffiffiffiffiffiffi

gmp ¼

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

WL� CBOX � ls � VD

r

� ðVG � VFBÞ ð11Þ

The curves YS(VG) are linear as shown in Fig. 12. The flat-bandvoltage VFB is determined from the intercept with the gate voltageaxis and the surface mobility in the accumulation channel from theslope, as indicated in Eq. (11).

Fig. 13 shows the surface mobility lS versus gate length. Thesurface mobility is systematically lower than the volume mobilitylVol by a factor of two due to stronger field-effect and additionalcarrier scattering at the interface film-BOX [7]. lS is superior inthick films (100–200 nm) where the coupling between top surfacedefects and bottom channel is attenuated. The quality of theInGaAs-BOX interface is assumed constant given the stability ofthe fabrication process. The lowest mobility is measured for25 nm thick devices and is attributed to the charged defects existin the top surface. The difference between the front-surface andback-surface potentials induces a vertical field, Eint = (WS1 �WS2)/tIII-V, that obviously increases in thinner films [29]. Even if the influ-ence of the gate-induced field is removed in Y-function, the mobil-ity is still affected by the intrinsic field. In other words, the genuinelow-field mobility is not accessible.


4.4. Low-temperature measurements

Fig. 14(a) shows the drain current versus gate bias characteris-tics measured at different temperatures T. As reported for junction-less devices [30], the drain current in accumulation regimeincreases at lower temperature primarily because the mobility isimproved (reduced phonon scattering). At the same time, theflat-band voltage (empty symbols in Fig. 14(b)) increases whichdelays the formation of the accumulation channel. Fig. 14(b) alsopresents the subthreshold swing S (plain symbols) versus T. A lin-ear decrease of S with temperature is found between 200 K and300 K, already documented for undoped MOSFETs [5]. The swingtends to saturate below 150 K, presumably due to the increase ofthe effective density of traps.

4.5. Strain effect

Samples are diced in 2 cm � 3 mm pieces and mounted in a 3-point bending setup (Fig. 15) where uniaxial tensile strain can beapplied up to 0.2% without breaking the samples. The ON-currentION benefits from tensile strain applied along the h1 1 0i transportdirection and increases at a rate of 10–15% per percent of strain(Fig. 16).

5. Conclusions

We have fabricated and characterized back-gated accumulationlayer MOSFETs on InGaAs-on-Insulator wafers. These simple teststructures are intended to provide a quick feedback for InGaAstechnology optimization. Detailed measurements point out thecoexistence of two conduction mechanisms (volume and interfaceaccumulation). The plateau present in ID(VG) curves and thedouble-peak transconductance reveal the transition from volumeconduction to surface-dominated conduction. A methodologywas proposed for the extraction of carrier mobility in the neutralvolume and at the film-BOX interface. The volume mobility isalways higher than the surface mobility and exceeds 1100 cm2/V s in 100–200 nm thick InGaAs films. The lowest mobility wasmeasured on very thin (25 nm) layers which suffer from strongcoupling between top interface defects and conduction channel.The InGaAs material properties were also investigated as a functionof aspect ratio and low-temperature operation. Finally, uniaxialtensile strain in the h1 1 0i transport direction highlighted theimprovement the on-current with a rate of 10–15% per percentof strain.

Acknowledgements

This work is supported by European Union through the projectsCOMPOSE3 (FP7-ICT-11-619325) and III-V-MOS (FP7-ICT-11-619326).

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[22] Cristoloveanu S, Bawedin M, Ionica I. A review of electrical characterizationtechniques for ultrathin FDSOI materials and devices. Solid-State Electron2016;117:10–36.

[23] Pirro L, Czornomaz L, Park HJ, Ionica I, Bawedin M, Djara V, et al. Volume andinterface conduction in InGaAs junctionless transistors. In: Ultimateintegration on silicon (EUROSOI-ULIS), 2016 Joint international EUROSOIworkshop and international conference.

[24] Sze SM, Ng KK. Physics of semiconductor devices. John Wiley & Sons; 2006.[25] Schubert EF. Doping in III–V semiconductors. Cambridge University Press;

2005.[26] Allibert F, Pretet J, Pananakakis G, Cristoloveanu S. Transition from partial to

full depletion in silicon-on-insulator transistors: impact of channel length.Appl Phys Lett 2004;84(7):1192–4.

[27] Liu FY, Diab A, Ionica I, Akarvardar K, Hobbs C, Ouisse T, et al. Characterizationof heavily doped SOI wafers under pseudo-MOSFET configuration. Solid-StateElectron 2013;90:65–72.

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[29] Hamaide G, Allibert F, Andrieu F, Romanjek K, Cristoloveanu S. Mobility inultrathin SOI MOSFET and pseudo-MOSFET: impact of the potential at bothinterfaces. Solid-State Electron 2011;57(1):83–6.

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DC and RF characterization of InGaAs replacement metal gate (RMG)nFETs on SiGe-OI FinFETs fabricated by 3D monolithic integration


⇑ Corresponding author.E-mail address: [email protected] (V. Deshpande).

V. Deshpande a,⇑, V. Djara a, E. O’Connor a, P. Hashemi b, K. Balakrishnan b, D. Caimi a, M. Sousa a,L. Czornomaz a, J. Fompeyrine a

a IBM Zurich Research Laboratory, Säumerstrasse 4, CH-8803 Rüschlikon, Switzerlandb IBM T.J. Watson Research Center, 1101 Kitchawan Rd., Route 134, Yorktown Heights, NY, USA




Keywords:3D monolithicInGaAsRMGHigh-frequencyFinFET

We report the first RF characterization of short-channel replacement metal gate (RMG) InGaAs-OI nFETsbuilt in a 3D monolithic (3DM) CMOS process. This process features RMG InGaAs-OI nFET top layer andSiGe-OI fin pFET bottom layer. We demonstrate state-of-the-art device integration on both levels. Thebottom layer SiGe-OI pFETs are fabricated with a Gate-First (GF) process with fins and featuring epitaxialraised source drain (RSD) as well as silicide contact layer. The top layer InGaAs nFETs are fabricated with aRMG process featuring a self-aligned epitaxial raised source drain (RSD). We show that the 3D monolithicintegration scheme does not degrade the performance of the bottom SiGe-OI pFETs owing to an opti-mized thermal budget for the top InGaAs nFETs. From the RF characterizations performed (post-3Dmonolithic process) on multifinger-gate InGaAs-OI nFETs, we extract a cut-off frequency (Ft) of16.4 GHz at a gate-length ðLgÞ of 120 nm. Measurements on various gate lengths shows increasing cut-off frequency with decreasing gate-length.


1. Introduction

3D monolithic (3DM) integration is attracting much attentionowing to density scaling benefits and the potential to stack inde-pendently optimized multifunctional layers at transistor level [1].However, due to the inherently high thermal budget of Si MOSFETprocess, Si(Ge)-on-Si 3DM integration scheme faces major chal-lenges in top layer optimization without degrading bottom layerperformance. This necessitates development of low temperaturetop layer Si/SiGe process which presents further challenges toobtaining high-performance MOSFETs on top layer. As the InGaAsMOSFET processing thermal budget is significantly lower, it iswell-suited to be used as the top layer channel material. Moreover,InGaAs also has higher mobility which enables high performanceat lower voltages [2,3] and is an excellent channel material forhigh-frequency devices enabling very high cut-off frequency[4,5]. This aspect is of great interest as it can enable a truly multi-functional 3D monolithic integration scheme. On one hand, InGaAsnFETs on top of Si/SiGe FETs can allow higher performance hybridCMOS [6] and on the other, high frequency InGaAs RF-FETs canbenefit from closely integrated CMOS circuits [7]. As a step towards

such a multi-functional 3D monolithic integration, here, we showDC and RF characteristics of InGaAs nFETs fabricated with RMGprocess on top of SiGe-OI finFETs. We perform RF characterizationof InGaAs-OI nFETs of various gate-lengths designed with opti-mized ‘multi-finger gate’ layout to enable efficient characteriza-tion. We demonstrate a cut-off frequency of 16.4 GHz for gatelength (Lg) of 120 nm. Also, cut-off frequency is shown to increasewith decreasing gate-lengths. We also demonstrate that the impactof 3DM integration on the bottom pFET performance is negligible,despite the top nFET RMG process featuring a self-aligned raisedsource drain epitaxy (with relatively high thermal budget). Thuswe demonstrate a robust InGaAs-on-SiGe 3DM integration schemethat can enable multifunctional circuits involving dense CMOS andhigh-frequency InGaAs nFETs.

2. Device fabrication

The steps involved in the InGaAs-on-SiGe 3D monolithic pro-cess flow are shown in Fig. 1.

Firstly, bottom layer SiGe-OI fin pFETs are fabricated with agate-first (GF) process as described in [8,9]. The process beginswith thinning of silicon layer of an 8 in. SOI wafer followed byGe condensation to obtain SiGe-OI layer (with 25% Ge content).Then active pFET areas are patterned. This is then followed by gate







Fig. 1. InGaAs-on-SiGe 3D monolithic integration process flow.

88 V. Deshpande et al. / Solid-State Electronics 128 (2017) 87–91

stack deposition as typical of a gate-first process flow. Thereafter,the gate lithography and gate etching is performed. After gate pat-terning, spacer deposition is carried out. Then the spacers areformed with anisotropic dry etching. After this step, in situ ‘p type’doped SiGe epitaxy is carried out to form self-aligned raised sourcedrain (RSD) regions. Then NiPt salicidation (self-aligned silicida-tion) is performed to obtain low contact resistivity on the pFETs.This silicide sets the thermal budget limit for the top nFET process-ing as high temperature can lead to degradation of silicide resistiv-ity impacting the bottom FET performance [10]. The top layer nFETfabrication starts after this silicidation step of SiGe-OI finFET pro-cess. It begins with InGaAs layer transfer on top of processed pFETsthrough direct wafer bonding [11]. To achieve this, first an inter-layer oxide (ILD0 in Fig. 2) is deposited and chemical-mechanical-polish (CMP) planarization is carried out. The InGaAslayer is transferred on to this oxide with direct wafer bonding from2 in. InP donor wafers [11]. The thickness of the transferred InGaAslayer is 20 nm. Owing to direct wafer bonding technique, a planarcontinuous InGaAs layer is obtained on top of the ILD0. Therefore,this layer can be patterned in any desired structures with samealignment accuracy of the lithographic process of the bottom pFETlayer. After transferring the InGaAs layer, the top InGaAs nFET fab-rication is performed with a replacement metal gate (RMG) process[12,13]. The process starts with the patterning of InGaAs layer toform active transistor mesa regions either as planar areas or

Fig. 2. Schematic of the InGaAs-on-SiGe 3DM stack showing multi-finger gatenFETs on top layer.

wide-fins (40–100 nm width). After forming the active areas, adummy gate stack deposition is done. The dummy gate is then pat-terned. Spacers are formed on either side of the dummy gate in asimilar way as in the bottom pFET process. It is then followed byself-aligned in situ ‘n type’ doped InGaAs epitaxy to form raisedsource-drain (RSD) regions. In general, this step is a relatively highthermal budget process and can be detrimental to bottom pFETperformance. Therefore, it has been optimized to minimize theprocess temperature while obtaining high doping in the layer [6].After the RSD process, the dummy gate replacement process stepsare carried out. An encapsulation oxide layer (ILD1) is first depos-ited and planarized with CMP process to expose the top of dummygate. Then the dummy gate stack is selectively etched out exposingthe InGaAs channel in the region where the dummy gate was pre-sent. An optimized high-k/metal gate (HKMG) stack featuring ascaled Al2O3/HfO2 dielectric [14] is then deposited. This stackforms the actual gate oxide and gate metal on top of the InGaAschannel. The HKMG stack is immediately capped with W metal.After this deposition, the gate metal (W) is planarized again withCMP process to the same level as the encapsulation oxide. Finally,another oxide encapsulation is deposited and contact holes areopened to both top nFET and bottom pFET source/drain and gateregions. Metallization is completed to create contact pads for bothlayers. After completion of the contacts and metallization, thedevices are annealed in H2/Ar ambient for optimizing the gatestack in terms of interface state density (Dit) [15]. The schematicof the so completed 3D monolithic stack is shown in Fig. 2 and across section STEM image of the 3D monolithic stack taken alongthe gate is shown in Fig. 3. The InGaAs fins with RMG can be seenon the top layer and SiGe-OI fins are visible on the bottom layer.

3. Electrical characterization

In this section, first the DC characteristics of the InGaAs nFETs isdiscussed, followed by the RF characteristics. The contact pads are

Fig. 3. STEM image of the InGaAs-on-SiGe 3DM stack showing nFETs on top of SiGefinFETs.

-0.2 0.0 0.2 0.4 0.6 0.8 1.010-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

Vds = 50 mV

Top layer InGaAs-OI planar nFETLg = 120 nm

I d (A)

Vg (V)

Vds = 500 mV

SSsat = 100 mV/decDIBL = 100 mV/V

Fig. 5. DC Id � Vg characteristics of top layer InGaAs-OI planar nFET withLg = 120 nm.

-0.2 0.0 0.2 0.4 0.6 0.8 1.00.0

0.5

1.0

1.5

2.0

2.5

Vds = 50 mV

Top layer InGaAs-OI planar nFETLg = 120 nm

Gm

(mS)

Vg (V)

Vds = 500 mV

Fig. 6. DC Gm � Vg characteristics of top layer InGaAs-OI planar nFET withLg = 120 nm.

1200

1600

Vg = 0 V to Vg = 1 V ΔVg = 0.2 V

Lg = 120 nm

V. Deshpande et al. / Solid-State Electronics 128 (2017) 87–91 89

designed in coplanar waveguide (CPW) structure and can be mea-sured with standard Ground-Signal-Ground (GSG) probes. The padlayout and the transistor layout featuring multi-finger gates isshown in Fig. 4.

The multi-finger gate design allows lowering the gate-resistance owing to multiple parallel gates. Furthermore, the nFETscharacterized in this work have dense features with gate-to-contact spacing of 100 nm. The DC Id � Vg characteristics of anInGaAs planar nFET with Lg = 120 nm are shown in Fig. 5.

This device features 10 finger gates in parallel. DC characteris-tics show competitive electrostatic control with drain-induced-barrier-lowering (DIBL) of 104 mV/V and SSsat = 100 mV/dec due ascaled high-k gate stack with a CET of 1.6 nm. Fig. 6 shows theDC Gm � Vg characteristics for the same device. A peak Gm of about1.7 mS is obtained at Vd = 0.5 V and Vg = 0.65 V. This value of Vg isused for the device for subsequent characterization to estimatecut-off frequency. Fig. 7 shows the Id � Vd characteristics for thesame device. Fig. 8 shows the DC Gds � Vg characteristics. Thedrain-induced-barrier-lowering (DIBL) vs. Lg and saturation sub-threshold slope (SSsat) vs. Lg curves are shown in Figs. 9 and 10respectively. Owing to low CET, competitive sub-threshold charac-teristics are observed on the nFETs. However, devices on the samechip with ‘single gate finger’ layout presented in Ref. [6] show rel-atively better electrostatics. This could be due to smaller spacerwidth in multi-finger gate devices, as the fabrication process isnot fully optimized for dense multi-finger layout. A comparisonof the Id � Vg characteristics bottom layer SiGe-OI finFET beforeand after top nFET fabrication is shown in Fig. 11. The figure showsthe Id � Vg characteristics of a SiGe-OI pFET with Lg = 36 nm and finwidth 15 nm, before (dash) and after (solid) top nFET fabrication.Due to the lower thermal budget of the top layer InGaAs process,very minimal impact is observed on the bottom pFET even for ascaled gate length. Nearly the same drain current (Id) is maintainedat both linear and saturation regime in the pFET indicating nodegradation of the bottom silicide. Therefore, it is seen that ourintegration scheme allows obtaining competitive DC performancefor top InGaAs nFETs without degrading the performance of thebottom pFETs.

Now, RF characterization of the top nFET is discussed. The RFcharacterization on nFETs is performed on devices with 10 parallelfinger gates, each with a width of 2 lm (= total device width of20 lm), and having a ground-signal-ground (GSG) pad configura-

Fig. 4. CPW pad structure (top) and multi-finger gate layout (bottom) of the InGaAsnFET used for RF characterization.

0.0 0.2 0.4 0.6 0.8 1.00

400

800

I d (A

)

Vd (V)

Fig. 7. DC Id � Vd characteristics of InGaAs-OI top layer planar nFET withLg = 120 nm.

tion. A LRRM calibration with a vector-network-analyzer (VNA) isfirst carried out on a commercial standard reference calibrationsubstrate, to move the reference plane to probe tips. Dedicatedon-chip ‘open’ pad structures are used to de-embed the device.The ‘open’ pad structures are similar to the pad layout shown inFig. 4, without the MOSFET in the center. S-parameters are mea-sured from 45 MHz to 40 GHz. First, S parameters of the deviceare measured at Vg which corresponds to the peak in DC transcon-ductance of the MOSFET. Then S parameters are converted to Yparameters (denoted YTOTAL). Then the S parameters of the ‘open’

0.0 0.2 0.4 0.6 0.8 1.00.0

0.5

1.0

1.5

2.0

2.5

3.0

Vg = 0 V to Vg = 1 V ΔVg = 0.2 V

Lg = 120 nmG

ds (m

S)

Vd (V)

Fig. 8. DC Gds � Vd characteristics of InGaAs-OI top layer planar nFET withLg = 120 nm.

0 100 200 300 400 5000

20

40

60

80

100

120

140

160

180

200Top LayerInGaAs-OIPlanar nFETs

Lg (nm)

DIB

L (m

V/V)

Fig. 9. DIBL� Lg characteristics of InGaAs-OI top layer planar nFETs.

0 100 200 300 400 50060

80

100

120

140 Top LayerInGaAs-OIPlanar nFETs

Lg (nm)

SS sa

t(mV/

dec)

Fig. 10. SSsat � Lg characteristics of InGaAs-OI top layer planar nFETs.

-0.8 -0.6 -0.4 -0.2 0.0 0.210-9

10-8

10-7

10-6

10-5

10-4

Bottom layerSiGe-OI pFET

Lg = 36 nmWfin ~ 15 nm

Vds = -50 mV

Blue solid - after nFET

Black dash line - before nFET

|I d| (A

)

Vg - Vt (V)

Vds = -800 mV

Fig. 11. Comparison of Id � Vg characteristics of bottom layer SiGe-OI pFET beforeand after top nFET fabrication.

1E8 1E9 1E100

10

20

30

40

Vds = 1V

|H21

| (dB

)

Frequency (Hz)

Ft = 16.4 GHz

Lg = 120 nm, width = 2 μm 10 gate fingers

Fig. 12. Measured current gain (jh21j) vs. frequency for a InGaAs nFET (top layer)with Lg = 120 nm and 10 parallel gate fingers. Cut-off frequency (Ft) of 16.4 GHz isobtained for Vds = 1 V.

1E8 1E9 1E100

10

20

30

U

Vds = 1V

Gai

n (d

B)

Frequency (Hz)

Fmax ~ 23 GHz

Lg = 120 nm, width = 2 μm10 gate fingers

Fig. 13. Measured unilateral gain (U) vs. frequency for a InGaAs nFET (top layer)with Lg = 120 nm and 10 parallel gate fingers. Fmax of 23 GHz is obtained forVds = 1 V.

90 V. Deshpande et al. / Solid-State Electronics 128 (2017) 87–91

pad structure are measured and converted to Y parameters(denoted YOPEN). For de-embedding, the Y parameters of ‘open’structure are subtracted from the Y parameters of the MOSFET.Then the current gain (jh21j) is calculated with equation below:

jh21j ¼ jY21MOSFET jjY11MOSFET j ð1Þ

where

YMOSFET ¼ YTOTAL � YOPEN ð2ÞThe current gain jh21j (dB) vs. frequency is shown in Fig. 12, for

a device with Lg = 120 nm. A cut-off frequency (Ft) of 16.4 GHz isobtained for Vds = 1 V. Lower Ft value is probably due to higher

100 200 300 400 5000

2

4

6

8

10

12

14

16F t

(GH

z)

Lg (nm)

Vds = 600 mV

Fig. 14. Cut-off frequency vs. gate length (Lg) for top InGaAs nFETs for Vds = 600 mV.

V. Deshpande et al. / Solid-State Electronics 128 (2017) 87–91 91

access resistance in the device which degrades the transconduc-tance and higher gate-source capacitance resulting from the over-lap of the source line with gate line. Fig. 13 shows the unilateralgain (U) vs. frequency. From the graph, maximum oscillation fre-quency (Fmax) is estimated to be 23 GHz. Cut-off frequency vs.Lgplotted in Fig. 14 shows and an increase in cut-off frequencies withdecreasing Lg . The solid line shows 1=Lg trend line indicating thatFt is inversely proportional to Lg . Hence, scaling down Lg further,along with improving access resistance and a relaxed gate-contact spacing could provide a way to significantly increase thecut-off frequency.

4. Conclusion

We show, for the first time, RF characterization of InGaAs RMGnFETs fabricated on top of SiGe-OI finFETs in 3D monolithic inte-gration. A cut-off frequency of 16.4 GHz is obtained forLg = 120 nm nFET with negligible impact on the bottom pFET per-formance. The InGaAs nFETs also feature a scaled gate stack andtight pitch design (gate-contact spacing = 100 nm). Thus wedemonstrate the benefit of InGaAs-on-SiGe 3D monolithic integra-tion, showing that independently optimized multi-functional lay-ers can be fabricated exploiting the advantages of both devicelayers.

Acknowledgment

Funding from the EU is acknowledged under the following EUand Marie-Curie projects: ICT-2013-11 COMPOSE3, ICT-2013-11

IIIVMOS, H2020-ICT-2015-688784-INSIGHT and PEOPLE-2013-IEFFACIT. Authors also acknowledge the IBM MRL and BRNC staff aswell as management support at both sites.

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[5] Zota CB, Roll G, Wernersson LE, Lind E. Radio-frequency characterization ofselectively regrown InGaAs lateral nanowire MOSFETs. IEEE Trans Electron Dev2014;61(12):4078–83.

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[12] Djara V, Deshpande V, Uccelli E, Daix N, Caimi D, Rossel C, et al. An InGaAs onSi-platform for CMOS with 200 mm InGaAs-OI substrate, gate-first,replacement gate planar and FinFETs down to 120 nm contact pitch. In:2015 Symposium on VLSI technology (VLSI technology). p. T176–7.

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Elimination of the channel current effect on the characterization ofMOSFET threshold voltage using junction capacitance measurements


⇑ Corresponding author.E-mail addresses: [email protected] (D. Tomaszewski), [email protected]

(G. Głuszko), [email protected] (L. Łukasiak), [email protected](K. Kucharski), [email protected] (J. Malesinska).

Daniel Tomaszewski a,⇑, Grzegorz Głuszko a, Lidia Łukasiak b, Krzysztof Kucharski a, Jolanta Malesinska a

aDivision of Silicon Microsystem and Nanostructure Technology, Instytut Technologii Elektronowej (ITE), ul. Okulickiego 5E, 05-500 Piaseczno, Polandb Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warsaw, Poland




Keywords:MOSFETCMOSThreshold voltageJunction capacitanceParameter extraction

a b s t r a c t

An alternative method for an extraction of the MOSFET threshold voltage has been proposed. It is basedon an analysis of the MOSFET source-bulk junction capacitance behavior as a function of the gate-sourcevoltage. The effect of the channel current on the threshold voltage extraction is fully eliminated. For thethreshold voltage and junction capacitance model parameters non-iterative methods have been used. Theproposed method has been demonstrated using a series of MOS transistors manufactured using a stan-dard CMOS technology.


1. Introduction

The threshold voltage is one of the first-order specifications ofCMOS technologies. It is used for the process development (e.g. set-ting doping profiles, if applicable), for the characterization of theprocess including its variability, and for the development of pro-cess design kits (PDK’s). Therefore, the MOSFET threshold voltageextraction is a mandatory step in the evaluation of CMOS pro-cesses, and in the sequences of parameter extractions leading tocomplete device-level compact models necessary for electricalsimulation, thus for a design of integrated circuits (ICs).

The standard definition of the large area MOSFET thresholdvoltage (Vth) results from the 1D electrostatic analysis, in whichthe channel current flow is neglected [1,2]. On the other handthe threshold voltage extraction methods, which are in commonuse, are based on the measured I–V characteristics [3,4]. Obviously,the theory and experiment are inconsistent in this case. Mobilitydegradation related to the electric field and a voltage drop acrossthe source and drain resistances in real devices affect Vth extrac-tion. Methods aimed at minimization of these effects have beenproposed, e.g. in [5,6]. However they do not eliminate fully thechannel current effect on Vth extraction. Extensive research on

the identification of the current flow effect (via mobility and lateralelectric field) on the extracted Vth was presented in [7,8]. Howeverthis approach is still based on I–V characteristics and requires thecalculation of higher order derivatives.

The Vth extraction using the current-based methods is disad-vantageous also with respect to the characterization of the processvariability, which becomes one of the main limitations of the MOS-FET scaling. The unambiguous Vth extraction is clearly needed todistinguish the device behavior variability linked to Vth itself, fromother variability sources such as mobility, interface roughness, orseries resistance, which lead to inaccurate Vth extraction whenusing strong inversion-based current-voltage methods and henceto unwanted artifacts and cross-correlations in process or variabil-ity analyses [9].

The same phenomena, which define the carrier concentrationdistribution in the channel and the MOSFET operation in steady-state conditions are responsible for the device small signal behav-ior. The MOSFET capacitances consist of intrinsic and extrinsicparts [1,2]. The intrinsic components are related to the areabetween the source and drain, whereas the extrinsic ones arerelated to the device peripheries. While the modeling of the mostof the intrinsic capacitances is difficult because of problems withthe channel charge sharing between the source and drain terminals(unless no current flow conditions are considered), the modeling ofthe parasitic extrinsic capacitances is much more straightforwardin terms of their interpretation. By definition the phenomena inthe areas associated with the extrinsic capacitances are of electro-











D. Tomaszewski et al. / Solid-State Electronics 128 (2017) 92–101 93

static nature. This has encouraged us to apply the MOSFET capac-itance measurements for the threshold voltage extraction. In thiswork we have explored first of all a method based on the measure-ments of the MOSFET source-bulk (SB) junction capacitance Cbs vsthe VGS and VBS voltages. The drain terminal remains open, there-fore the channel current effect is efficiently eliminated. It may beexpected that such an approach not only allows ambiguities inVth extraction to be avoided, but can be also helpful in eliminatingother variability sources affecting the threshold voltage via thechannel current flow (unavoidable in the I-V based methods) fromthe Vth variability. These are e.g. mobility variations and line edge/width roughness effects.

The paper is arranged as follows. In Section 2 the proposedmethod has been described and illustrated using numerical simu-lation results. In Section 3 the experiment details are discussed.Test devices, electrical measurement conditions and results aredescribed. In Section 4 the parameter extraction algorithms basedon the measurement data are presented. They allow for the effi-cient extraction of the threshold voltage, body effect factor andFermi level, as well as for extraction of the junction capacitance,its grading coefficient and built-in voltage. In Section 5 the consid-erations are summarized.

Fig. 1. Potential distribution in p-channel MOSFET for (a) VBS = 0 V, VGS = 0 V, (b)VBS = 0 V, VGS = �2 V; (c) Potential distributions along vertical dashed lines drawn in(a), (b) for VBS = 0, 1, 2 V, VGS = 0, �0.5, �1 V.

2. Description of the method

As a starting point let us begin with a short discussion of thep-channel MOSFET numerical simulation results obtained usingSilvaco Atlas, and shown in Fig. 1. It is visible, that the potentialdistribution in the space charge area of the SB junction below thegate behaves differently than in the area outside the gate. As thegate-source voltage VGS changes the potential distribution belowthe gate changes too, while that below the junction remains con-stant. In accumulation the potential distribution below the gateis rather insensitive to the gate bias, therefore it is expected thatthe Cbs capacitance does not change with VGS. However at the onsetof strong inversion a channel is induced. A capacitor is formed,which plates are the inversion layer connected with the sourceand the bulk area below the gate. Between these plates there is agate-induced depletion area. This mechanism should be reflectedby a steep increase of the Cbs capacitance. This observation is thebasis of the proposed method.

The simulated hole distributions in the pMOSFET calculated atthe accumulation and inversion below the gate are shown inFig. 2. Two simple capacitor networks represent the Cbs(VBS, VGS)characteristics behavior for these conditions. Cbs,J(VBS) capacitancein Fig. 2a and b denotes the capacitance of the junction includingits side-wall areas, whereas Cbs,G(VBS, VGS) in Fig. 2b denotes thecapacitance component induced by the inversion channel buildup.In Fig. 3 it has been shown that an increase of the Cbs capacitanceappears at the onset of the strong inversion below the gate, i.e. atthe threshold. As expected, below the threshold the Cbs capacitanceremains almost constant relative to the gate voltage. A small vari-ation of the Cbs with VGS noticeable for VBS = 0 V is due to a de-crease of the side-wall component, which occurs if the gate biasapproaches the threshold. This is because under such conditionsthe depletion area width at the surface increases. This effect isclearly visible in Fig. 1a and b. For completeness it should be added,that at this gate bias range the hole concentration beneath the gateincreases exponentially with VGS voltage.

The inversion onset is visible also in other AC characteristics ofthe MOSFETs. In Fig. 4 the Cbs(VGS) and Cgs(VGS) data sets are com-pared. In the latter characteristics even a more pronouncedincrease at the threshold is visible. However, it may be seen, thatin the considered case the Cgs capacitance is VGS-dependent bothabove and below the threshold, where the effect is much stronger

than for the Cbs capacitance. Such behavior is induced by the vari-ation of the so-called internal fringing component of the Cgs capac-itance predominant below the threshold and its smooth transitioninto the gate-channel capacitance Cgc prevalent above the thresh-old. This is why the threshold voltage cannot be unambiguously

Fig. 2. Hole distribution in the p-channel MOSFET for VBS = 0 V and for (a)depletion, (b) inversion below the gate; components of the Cbs capacitance areshown in order to illustrate the effect of the inversion layer formation.

Fig. 3. Cbs(VGS) characteristics (in black) in comparison with the curves illustratinghole concentration below the gate vs gate voltage (in red) for different substratebias values; blue lines indicate the adequacy between points of Cbs increase andinversion onset. (For interpretation of the references to colour in this figure legend,the reader is referred to the web version of this article.)

Fig. 4. A comparison of Cbs(VGS) and Cgs(VGS) characteristics showing a behavior ofboth characteristics families at the threshold.

94 D. Tomaszewski et al. / Solid-State Electronics 128 (2017) 92–101

extracted from the Cgs(VGS) characteristics as the gate voltage, atwhich Cgs starts to increase. Using the described approach is easierif the threshold is determined from the Cbs(VGS) characteristics. Onthe other hand wemust acknowledge that a reliable method for Vth

extraction based on the Cgs(VGS) data has been proposed in [10]. Inthis method Vth corresponds to the maximum of dCgc/dVGS, whichcan be easily determined. It should be added, though that in theorythe method is equivalent to the I-V based method presented in [6]which uses the maximum of d(gm/ID)/dVGS. Nevertheless, in thispaper we propose the threshold voltage extraction procedurebased on the less ‘‘dynamic” Cbs(VGS) characteristics. It will beshown that our method not only allows the threshold voltageand its parameters to be estimated, but also directly enables junc-tion capacitance modeling and provides an additional method forthe Fermi voltage extraction.

The proposed method consists in the measurement of theCbs(VGS) characteristics for a series of VBS voltages. It is expected,that on the Cbs(VGS) curves at the given VBS voltages and at theaccumulation/depletion conditions below the gate the Cbs capaci-tance is constant regardless of VGS variation. It corresponds tothe junction capacitance Cbs,J(VBS) (see Fig. 2) including the areaand side-wall components. The clearly visible transition pointsbetween the accumulation/depletion and inversion ranges definethe Vth(VBS) characteristics.


For the experimental validation of the method described in theprevious section, we have used the n- and p-channel MOSFETs fab-ricated in ITE using a single p-well, polysilicon gate CMOS processwith the following characteristics: 3 lm polysilicon line width,65 nm gate oxide thickness, 1.2�1016 and 6�1015 cm�3 substratedoping concentrations in the n- and pMOSFETs accordingly.Besides the standard devices of rectangular shape we have alsoused finger-type wide ones, originally designed for the characteri-zation of the gate overlap capacitances. In such devices signifi-cantly larger junction capacitances are expected. Layouts of twotypes of the pMOSFETs are shown in Fig. 5.

The MOSFET C–V characteristics have been measured using aKeithley 4200–SCS parametric analyzer equipped with a 4200–CVU unit. Its force and sense terminals have been connected withthe MOSFET source and bulk electrodes respectively. In this waythe DC bias of the SB junction has been provided by the CVU unit.The gate has been biased by a source-measure unit (SMU) included

Fig. 5. Layout of p-channel MOSFETs under test: left - a set of standards deviceswith the W(lm)/L(lm) ratio 50/50, 20/50, 10/50, 50/10, 50/5, right - a finger-typeMOSFET with W/L = 4800/10.

Fig. 6. (a) Cbs(VBS) characteristics of a p-channel MOSFET, W = 50 lm, L = 50 lm;VGS = �2.0 V; (b) the envelope of the Cbs(VBS) characteristics family.


in the analyzer. We have used a test signal of 100 kHz frequencyand 30 mV rms level. The measurements have been done at the10 pF range, for which the accuracy is approximately 0.02 pF. Inorder to minimize the effect of stray capacitances and parasiticresistances open and short corrections have been done.

Since the measurement set-up makes it easier to measure theCbs capacitance as a function of VBS than VGS, the proposed methodconsists in the measurement of the Cbs(VBS) characteristics for aseries of VGS voltages. Next, Cbs(VGS) characteristics with VBS as aparameter are constructed. The accuracy of the method is limitedby the gate voltage step size.

The Cbs(VBS) characteristics of a p-channel MOSFET withW = 50 lm and L = 50 lm measured at different VGS voltages areshown in Fig. 6a. As expected, a strong influence of the gate voltageis clearly visible. Enlarged bottom parts of these curves are shownin Fig. 6b. Though in the full-scale plot these parts appear to beconstant, a noticeable curvature is revealed in the enlarged plot.An ‘‘envelope” of the whole family corresponds to the accumula-tion/depletion conditions below the gate (�0.5 V 6 VGS 6 0 V).Each point of the ‘‘envelope” has been calculated as a mean valueof Cbs capacitances measured for a series of four VGS voltages.The ‘‘envelope” corresponds to the Cbs,J(VBS) characteristics of theSB junction including its edge.

The Cbs(VGS) characteristics are shown in Fig. 7a. As expected,three regions may be distinguished in these curves. In the firstregion the Cbs capacitance is the lowest and is gate voltage inde-pendent. In this gate bias range the area below the gate is accumu-lated or depleted and the Cbs capacitance is determined only by thespace charge of the SB junction. If the gate voltage becomes morenegative and exceeds the threshold voltage, a steep increase ofthe Cbs capacitance is observed. This effect is caused by the forma-tion of a highly conductive inversion layer. Similarly to the realsource area, below the gate-induced virtual source there is also adepletion region which separates the source plate from the bottomquasi-neutral substrate. In order to illustrate this mechanism fourCbs(VGS) curves are plotted in Fig. 7b after subtracting the ‘‘en-velope” value taken from Fig. 6. Points of the capacitance sharpincrease are clearly visible.

The Cbs(VGS) characteristics allow the Vth(VBS) characteristics ofthe MOSFETs to be derived. In [10] it has been shown, that thethreshold voltage corresponds to the maximum of dCgc/dVGS, thusto the maximum of dCgs/dVGS. There is no similar formal proof con-cerning the maximum of dCbs/dVGS. However, based on the inter-

pretation of the voltage effect on Cbs capacitance (see Section 2)we dare to say that the largest variation of Cbs corresponds to theonset of the inversion. Moreover, based on the numerical simula-tions shown in Fig. 4 the dCgs/dVGS and dCbs/dVGS curves may beconstructed (Fig. 8). It may be clearly noticed that the maxima ofthe corresponding derivative characteristics perfectly coincide. E.g. at VBS = 0 V their maximum is at VGS = �0.93 V, and at VBS = 3 Vthe maximum is at VGS = �1.23 V. Following this consideration, oneach Cbs(VGS) curve the threshold voltage is determined as the VGS

value, at which the dCbs/dVGS reaches maximum.In Fig. 9a the Vth(VBS) data obtained using the proposed method

are set together with the Vth(VBS) curves obtained using thestandard current-based methods, namely a linear extrapolationof ID-VGS characteristics at the transconductance maximum, anda linear extrapolation of ID/gm0.5-VGS characteristics [5]. The pro-posed C-V based approach gives results close to the method basedon the linear extrapolation of ID-VGS characteristics (Fig. 9b).

In Fig. 9a several points deviate slightly from the Vth(VBS) curvescorresponding to the C-V based method of Vth extraction. They aredue of the fact that the VGS step is too large. This effect is noticeablemainly for the relatively small values of the measured capacitance.However it makes further data processing more difficult and con-firms the need for the direct measurement of the Cbs(VGS) charac-teristics with VBS voltage stepped.

Fig. 7. (a) Cbs(VGS) characteristics for p-channel MOSFET obtained from the data inFig. 6; (b) Cbs(VGS) data after subtraction of the ‘‘envelope”; points of the stronginversion onset are clearly visible.

Fig. 8. Derivatives of the Cgs(VGS) (in black) and Cbs(VGS) (in red) characteristics forp-channel MOSFET simulated using Slvaco ATLAS and shown in Fig. 4. (Forinterpretation of the references to colour in this figure legend, the reader is referredto the web version of this article.)

Fig. 9. Threshold voltage extracted with three methods: (a) dependence on VBS

voltage, (b) extraction of Vth based on I-V characteristics.


The proposed method for the threshold voltage characterizationhas been also applied to the wide, finger-type MOSFETs (Fig. 5). Inthese devices much larger junction capacitances are expected. InFigs. 10 and 11 the appropriate C-V and the resulting Vth(VBS) datafor the p- and n-channel MOSFETs, W = 4800 lm, L = 10 lm areshown. In the Cbs(VBS) characteristics of the large area devicestwo ‘‘envelopes” are visible. The bottom one represents the Cbs,J

component of the total Cbs capacitance, whereas the top one repre-sents the sum of Cbs,J and Cbs,G components. The Cbs,G at the top Cbs

‘‘envelope” corresponds to the maximum depletion width belowthe gate, which appears at the strong inversion conditions. Accord-ingly, in the Cbs(VGS) characteristics at any VBS voltage two flatregions are visible. They are more pronounced than in the case ofthe device with W = L = 50 lm considered earlier and are suitablefor the parameter extraction. It should be added that the thresholdvoltages extracted using the Cbs-VGS-based method are lower thanthose determined using the I-V-based methods. This remains inagreement with the results presented in [6].

Fig. 10. Extraction of the threshold voltage for p-channel MOSFET, W = 4800 lm,L = 10 lm: (a) Cbs(VBS) data, (b) Cbs(VGS) data obtained from Cbs(VBS) data, (c)Vth(VBS) curves determined with C-V- and I-V-based methods.

Fig. 11. Extraction of the threshold voltage for n-channel MOSFET, W = 4800 lm,L = 10 lm: (a) Cbs(VBS) data, (b) Cbs(VGS) data, (c) Vth(VBS) curves determined with C-V- and I-V-based methods.


Fig. 12. Linear fits (2) corresponding to the (a) p- and (b) n-channel MOSFETVth(VBS) data extracted using I-V and Cbs-VGS based methods; each method has beenused for the non-filtered and filtered data; solid lines represent regression based onCbs-VGS data; dashed lines represent regression based on I-V data.


4. Parameter extraction

4.1. Threshold voltage

In the case of the long-channel enhancement-mode MOSFETsthe threshold voltage Vth is given by a well-known formula (1).

Vth ¼ Vth;0 þ t � c �ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

2 � /F � t � VBS

p

�ffiffiffiffiffiffiffiffiffiffiffiffi

2 � /F

p

� �

ð1Þ

where Vth,0 – threshold voltage at VBS = 0 V, c – body factor,2/F – double Fermi voltage. The variable t is equal to +1 for then-channel MOSFETs and to �1 for the p-channel MOSFETs. Typicallyc and 2/F parameters in (1) are extracted iteratively starting from agiven approximation of 2/F. However, using a non-iterative methoddescribed in [11,12] for Vth(VBS) data, the parameters of Vth in (1)may be determined with (2a) and (2b) using a linear regressionbetween terms Vth–Vth,0 and (dVth/dVBS)�1.

Vth;0 ¼ Vthð0Þ ð2aÞ

Vth � Vth;0 ¼ �0:5 � t � c2 � 1dVthdVBS

� t � c �ffiffiffiffiffiffiffiffiffiffiffiffi

2 � /F

p

ð2bÞ

The regressions for the Vth(VBS) data extracted using the I–Vbased and Cbs-VGS methods are illustrated in Fig. 12. In each charttwo types of fitting are visible. The four regressions based on theVth(VBS) data obtained directly from the measurement data areplotted in black. A large spread of the points subject to regressionis visible, in particular in the case of the n-channel MOSFET(Fig. 12b), Other four regressions based on the Vth(VBS) data filteredusing Savitzky-Golay method are plotted in red1.

The expected values of the body factor are approximately1.2 V0.5 (nMOSFET), and 0.7 V0.5 (pMOSFET). The expected Fermivoltage values ore 0.75 V nMOSFET) and 0.65 V (PMOSFET). Theextracted threshold voltage parameter values are listed in Table 1.The difference between the c values for the p-channel and n–chan-nel MOSFETs results from the fact, that CMOS technology with asingle p-well has been used. The c values extracted based on theraw data are far below the expected ones. The same situation iswith the 2/F values. This effect may be attributed to the noisy databeing subject to the linear fit. A significant spread of the datapoints in Fig. 12 strongly affects the slope and the intersection ofthe regression line with the horizontal axis, via the (dVth/dVBS)�1

term used in (2b). The slope determines the body factor value,whereas the intersection point determines the Fermi voltage. Thefiltering procedure has improved the extraction of c and 2/F inthe case of the nMOSFET, In the case of the pMOSFET the filteringhas not helped much, because the Vth(VBS) data quality is betterthan in the case of the n-channel device. Following the above dis-cussion it may be stated, that retrieving the smooth Vth(VBS) char-acteristics both from the I-V and C-V measurement data is relevantfor the reliable extraction. In practice it may be a non-trivial task,but in such a case data filtering may be helpful.

4.2. Junction capacitance

The proposed characterization method allows for a deeper anal-ysis of the Cbs capacitance in MOSFETs. The bottom ‘‘envelope” ofthe Cbs(VBS) characteristics family measured for different VGS volt-ages (Figs. 6b, 9a, 10a) represents the total Cbs capacitance of theMOSFET SB junction including its planar and sidewall components.Modeling of such a characteristics is based on the well-knownformula (3).

1 For interpretation of color in Fig. 12, the reader is referred to the web version ofthis article.

Cbs;J ¼ CJ

1� t�VBSVbi

� �MJ ð3Þ

where CJ is the capacitance at VBS = 0 V, Vbi is the built-in voltage,and MJ is a grading coefficient, which is theoretically 1/2 for an idealabrupt junction and 1/3 for an ideal linearly graded junction. The CJ

parameter is easily determined as Cbs(VBS = 0 V). The remaining twoparameters are typically extracted using an iterative procedure.Here, we propose a non-iterative approach, which is based on (4).

dCbs;J

dVBS¼ CJ � t � MJ

Vbi� 1� t � VBS

Vbi

� ��MJ�1

¼ Cbs;J � t � MJ

Vbi� 1� t � VBS

Vbi

� ��1

ð4Þ

After a simple transformation of (4) the method (5) for the junc-tion capacitance parameter extraction may be formulated. (5b) issubject to The linear regression (5b) between VBS and Cbs,J/(dCbs,J/dVBS) terms is used for extraction of MJ and Vbi.

Table 1Threshold voltage parameters of 4800 � 10 lm MOSFETs extracted from Vth(VBS) characteristics obtained from the non-filtered and filtered measurements.

Param NMOS PMOSMethod Method

ID-VG Cbs-VG ID-VG Cbs-VG

Vth,0 (V) 0.582 0.532 �0.792 �0.763c (V0.5) 0.649 0.669 0.434 0.4472/F (V) 0.33 0.31 0.29 0.37

After filtering of Vth(VBS) data obtained from ID-VG Cbs-VG measc (V0.5) 0.740 0.743 0.428 0.4652/F (V) 0.69 0.59 0.29 0.48

Fig. 13. Extraction of the junction capacitance parameters according to (5) for then- and p-channel MOSFETs, W = 4800 lm, L = 10 lm.

Table 2Junction capacitance parameters for 4800 � 10 lm MOSFETs.

Param NMOS PMOS

CJ (F) 9.9�10�12 3.7�10�12

MJ (–) 0.555 0.364Vbi (V) 0.869 0.543

Fig. 14. Gate-induced components of the junction capacitances under stronginversion conditions for the n- and p-channel MOSFETs, W = 4800 lm, L = 10 lm.


CJ ¼ Cbs;Jð0Þ ð5aÞ

VBS ¼ t � Vbi �MJ � Cbs;JdCbs;J

dVBS

ð5bÞ

The linear fits regarding the bottom ‘‘envelopes” of the Cbs(VBS)characteristics of the p- and n-channel MOSFETs are shown inFig. 13. Good quality of these fits is beneficial for the parameterextraction. The calculated values of the parameters are listed inTable 2.

As expected, in the case of the nMOSFET the capacitance CJ andthe built-in voltage Vbi are larger than in the pMOSFET, because ofthe substrate doping concentration levels in both device types.There is also a significant difference between the grading coeffi-cients MJ. In the nMOSFET a step junction has been revealed,whereas in the pMOSFET the junction is rather linear. However itshould be mentioned, that the Cbs capacitance comprises the planeand sidewall components. In the finger-type device the side-wallcapacitance component is large because of the large perimeter/area ratio. On the other hand the sidewall capacitance is less sen-sitive to VBS voltage, than the plane one. Following this we mayexpect that the parameter extraction results are affected by thetest structure non-ideality.

4.3. Gate-induced component of junction capacitance

In the previous section the bottom ‘‘envelopes” Cbs,J(VBS) of theCbs(VBS, VGS) characteristics corresponding to the lower plateaus inFigs. 10b and 11b have been used for the junction capacitanceparameter extraction. In this section the top ‘‘envelopes” are con-sidered. According to the interpretation given in Section 3 the junc-tion capacitance in excess of Cbs,J capacitance under the stronginversion conditions is attributed to the gate-induced depletionarea. In Fig. 14 the differences between top and bottom ‘‘en-velopes” are shown. These curves may be described with (6).

Cbs � Cbs;J ¼ AG;eff � eSi=xd;max

¼ AG;eff � eSi=ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

2 � eSiq � Nsub

� ð2/F � t � VBSÞs

ð6Þ

where AG,eff is the effective gate area, and eSi/xd,max is the gate-induced depletion region capacitance per unit area in the stronginversion conditions below the gate. Other parameters have theusual meaning. After a simple transformation we arrive at (7).

ðCbs � Cbs;JÞ�2 ¼ 1

A2G;eff

� �2tq � eSi � Nsub

ðVBS � t � 2/FÞ ð7Þ

Eq. (7) is suitable for the extraction of the Fermi voltage and ofthe substrate doping concentration. It is a favorable situationbecause the 2/F values for the n- and pMOSFETs calculated inthe Section 4.1 based on the Vth(VBS) characteristics are far fromthe expected values probably due to the data noise. The linearregressions (7) are shown in Fig. 15. A very good linear fit is notice-

Fig. 15. Extraction of the Fermi voltage and substrate doping concentration for then- and p-channel MOSFETs, W = 4800 lm, L = 10 lm.

Table 3Threshold voltage parameters and doping concentrations determined with (7) for4800 � 10 lm MOSFETs.

Param NMOS PMOS

Nsub (cm�3) 1.2�1016 7�10152/F (V) 0.71 0.94c (V0.5) 1.25 0.92


able. The extraction results are summarized in Table 3. The bodyfactor c has been calculated using the nominal gate oxide thickness65 nm.

The calculated doping concentrations remain in a good agree-ment with the CMOS process specification given at the beginningof Section 3. On the other hand a large discrepancy between theFermi voltages and body factors obtained based on Vth(VBS) andCbs–Cbs,J = f(VBS) data is clearly visible. As it has been discussed ear-lier, the first data set is saddled with the large spread of data pointsoriginating from the raw Vth(VBS) characteristics and shown inFig. 12. The spread may affect the validity of the parameters inTable 1. The second data set is smooth. This can be a convincingargument for the reliability of the second data set.

Another issue visible in particular in Table 3 is that the Fermivoltage for the nMOSFETs is lower than for the pMOSFETs irrespec-tive of the extracted doping concentration levels. Such an effect isnot observed in the built-in voltages Vbi calculated based on thejunction capacitance characteristics and shown in Table 2. A possi-ble explanation for this observation is that due to boron segrega-tion during the gate oxidation (partially compensated by theboron correction implantation) the acceptor concentration belowthe nMOSFET gate is lower than below the nMOSFET source junc-tion. The situation for the pMOSFETs is opposite.

Finally, it is worth mentioning that the two data sets used forthe parameter extraction, i.e. Vth(VBS) and Cbs–Cbs,J = f(VBS), havebeen obtained using different characteristics and for different mea-surement conditions. The Vth(VBS) characteristics obtained eitherfrom ID(VGS) or from Cbs(VGS) data and used in (2), correspond tothe onset of inversion. On the other hand, the Cbs–Cbs,J = f(VBS) dataused in (7) correspond to strong inversion conditions. Therefore, bydefinition the Fermi voltage extracted based on (7) should be largerthan the one determined based on (2).

5. Summary

Based on the numerical simulation results the methodology fora combined extraction of the MOSFET threshold voltage (including

body factor and Fermi voltage) and junction capacitance from theCbs(VGS) characteristics has been introduced. During the measure-ments the drain terminal of the device under test remains opento eliminate the effect of the channel current flow (via mobilityor series resistances) on the threshold voltage extraction. Accord-ing to the numerical simulations the Cbs-based method of thethreshold extraction should be equivalent to the method basedon gate capacitance measurements. It is worth mentioning thatthe proposed measurements may be done using gate-controlleddiodes as well.

Based on the nonlinear models of the threshold voltage Vth(VBS)and of the junction capacitance Cbs(VBS) three simple algorithmsfor the threshold voltage and junction capacitance parameterextraction have been proposed. Using simple arithmetic transfor-mations the closed-form, non-iterative formulae for the parameterextraction have been derived. They may be useful for automaticmeasurements combined with on the fly parameter extraction.There is no risk of a potential negative term in (1) or (3) breakingthe automated measurement/extraction procedure.

Two of the proposed extraction methods concern the thresholdvoltage characterization. The first one, relying on Vth(VBS) charac-teristics extracted from the Cbs(VGS) data corresponds to the onsetof inversion. It allows for a full characterization of the Vth of largearea MOSFETs. The second one, based on Cbs(VGS) data, is comple-mentary. It has been derived under the assumption of strong inver-sion conditions below gate. It provides more reliable values of theFermi voltage and body factor.

There are important conditions and limitations for using theproposed methods. First, for the measurements of the Cbs(VBS,VGS) characteristics we need the MOSFETs or gate-controlleddiodes with the junction area not smaller than approximately1500 lm2. Such a large junction is necessary in order to have reli-able Cbs measurements (range of 0.5 pF) of the devices manufac-tured using our process. Furthermore, we need also devices witha large gate area not smaller than approximately 1500 lm2. Sucha large gate is needed for the measurement of the gate-inducedCbs component in the strong inversion conditions. The reliablecapacitance measurements are necessary to obtain smooth Vth(VBS)and Cbs(VBS) data, used in fitting procedures (2) and (7). The pro-posed methods have been tested using the standard CMOS devicesmanufactured in ITE.

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http://dx.doi.org/10.1109/16.69923

http://www.mos-ak.org/edinburgh/posters/P10_Tomaszewski_MOS-AK_08.pdf

http://www.mos-ak.org/edinburgh/posters/P10_Tomaszewski_MOS-AK_08.pdf

http://dx.doi.org/10.1109/MIXDES.2015.7208514





Low frequency noise assessment in n- and p-channel sub-10 nmtriple-gate FinFETs: Part I: Theory and methodology


⇑ Corresponding author.E-mail address: [email protected] (D. Boudier).

D. Boudier a,⇑, B. Cretu b, E. Simoen c, R. Carin a, A. Veloso c, N. Collaert c, A. Thean c

aUniversity of Caen Normandie, UMR6072 GREYC, F-14050 Caen, Franceb ENSICAEN, UMR6072 GREYC, F-14050 Caen, Francec Imec, Kapeldreef 75, B-3001 Leuven, Belgium




Keywords:Triple-gateFinFETLow frequency noise1/f noiseGeneration-recombinationTraps

The transfer characteristic at room temperature of FinFETs processed for sub-10 nm technologies couldalways be explained by solving Poisson equation throughout the channel – dielectric interface. Variousmethods for the MOSFET parameters estimation are proposed in the literature. In this paper, the electricalparameters extraction technique based on the Y-function methodology is reminded.Low frequency noise is presented considering three major noise sources: 1/f noise associated to carrier

trapping-detrapping in the gate oxide, channel carrier mobility fluctuations and generation-recombination noise related to traps located in the depletion zone of the device. Theory and methodologyin order to identify the 1/f noise mechanism and to have information of the process induced traps in thesilicon film using the noise spectroscopy technique are revisited.


1. Introduction

Low frequency noise measurements can be used as a non-destructive diagnostic tool that leads to the identification of trapsin the Si and the gate oxide, thus giving informations on the qualityof the transistors fabrication. The study of the 1/f noise level withrespect to the gate overdrive voltage VGT leads to the identificationof the 1/f noise origin. The study of the generation-recombinationnoise, if performed as a function of the temperature at fixed draincurrents, gives access to information on the traps that are locatedin the depletion region of the transistor [1].

This paper summarizes the extraction methods and techniquesthat have been used in order to investigate triple-gate FinFETsissued from a sub-10 nm technological node.

Based on the expression of the drain current which takes intoaccount surface roughness scattering impact on the effective car-rier mobility, simple and accurate method for parameter extractionis based on the Y ¼ ID=

ffiffiffiffiffiffi

gmp

function. Indeed, the Y function exhi-bits a linear variation on the applied gate voltage and does notdepend on the access resistance through the first mobility attenu-ation factor. Special attention is given for the threshold voltage,

low field carrier mobility and access resistance estimation whichare needfully for 1/f low frequency noise modeling.

Then the low frequency noise theory is discussed, 1/f noisecharacterisation is described as it leads to the identification ofthe 1/f noise mechanism and an estimation of the gate oxide trapdensity. Finally the study of the depletion region traps is explainedusing a low frequency noise spectroscopy as a function oftemperature.

2. Static parameters extraction

2.1. MOSFET model in linear operation region

MOSFETs are composed from three resistive regions: the source,the channel and the drain, as seen in Fig. 1. In the linear region ofoperation, the MOSFET drain current ID in strong inversion can beexpressed by [2]

ID ¼ WLleff jQijVD0S0 ð1Þ

W and L are the gate effective width and length, respectively, VD0S0

is the voltage across the channel (between the points S0 and D0

of Fig. 1), and the inversion charge is usually taken as Qi = Cox(VGS0 � Vth � VD0S0/2), where VGS0 is the gate-source voltage, Vth is







Fig. 1. MOSFET resistive model. The source (between nodes S and S0), the channel(between S0 and D0) and the drain (between D0 and D) are the three resistive regionsthat compose the MOSFET.

D. Boudier et al. / Solid-State Electronics 128 (2017) 102–108 103

the threshold voltage, and Cox is the gate oxide capacitance perunit area.

The carrier mobility can be altered by several phenomena suchas phonon scattering (thermal vibrations of the crystal lattice),Coulomb scattering (ionized impurities that deviates carriers)and surface roughness scattering. The mobility limited by the pho-non scattering lph, by the Coulomb scattering lC and by the surfaceroughness scattering lsr lead to the effective carrier mobilityaccording to Matthiessen’s rule [2]

1leff

¼ 1lph

þ 1lC

þ 1lsr

ð2Þ

In strong inversion (i.e. for strong transversal electric field) theCoulomb scattering is negligible, leading to l�1

eff � l�1ph þ l�1

sr . Theeffective carrier mobility of the inversion channel carriers leff

depends of the low-field mobility l0, as seen in [3]

leff ¼l0

1þ h10 VGS0 � Vth � VD0S02

� �

þ h2 VGS0 � Vth � VD0S02

� �2 ð3Þ

h10 is called the intrinsic mobility attenuation factor and is dueto phonon scattering, while h2 is the second order mobility atten-uation factor, which is due to surface roughness scattering. Assum-ing that RS ¼ RD ¼ Raccess=2, the drain current expression in thelinear operation regime can be obtained by replacing Qi and leff

in (1)

ID ¼ GMVDS VGS � Vth � VDS2

� �

1þ ðh10 þ GMRaccessÞ VGS � Vth � VDS2

� �þ h2 VGS � Vth � VDS2

� �2

ð4Þwhere GM ¼ l0CoxW=L is the transconductance parameter. Theextrinsic mobility attenuation factor is defined byh1 ¼ h10 þ GMRaccess and takes into account the drain current attenu-ation due to the phonon scattering and the access resistance. Thetransistor transconductance is defined as the variation of the draincurrent with respect to the gate voltage gm ¼ @ID=@VGS and yields

gm ¼ GMVDS1� h2 VGS � Vth � VDS

2

� �2

1þ h1 VGS � Vth � VDS2

� �þ h2 VGS � Vth � VDS2

� �2h i2 ð5Þ

2.2. Y function method

The Y function has two main advantages: it does not depend onthe extrinsic mobility attenuation factor h1 and thus is indepen-dent on the access resistance Raccess, and does not use the drain cur-rent second derivative, in opposition to some other methods.However, it assumes that the low-field mobility l0 is independentof the gate length L. The Y function is based on the drain currentand transconductance equations as [3–5]

YðVGSÞ ¼ IDffiffiffiffiffiffi

gmp ¼

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

GMVDS

1� h2 VGS � Vth � VDS2

� �2

v

u

u

t VGS � Vth � VDS

2

� �

ð6Þ

In moderate inversion, when h2 VGS � Vth � VDS2

� �2 � 1, Y(VGS)should be linear and a linear fitting gives access to GM and Vth fromthe slope and the x-intercept, respectively. These estimations allowbuilding the effective mobility attenuation factor heff and thusdetermining the values of h1 and h2 from

heff ðVGSÞ ¼ GMVDS

ID� 1VGS � Vth � VDS

2

¼ h1 þ h2 VGS � Vth � VDS

2

� �

ð7ÞThis function should be linear and h1 and h2 can be extracted

from the y-intercept and the slope, respectively. The following stepconsists in extracting the access resistance Raccess and the intrinsicmobility attenuation factor h10 from the h1 and GM values linearplot, as

h1 ¼ h10 þ GMRaccess ð8ÞOnce the parameters GM, Vth, h1 and h2 have been extracted,

another iteration of the Yn function method can be performed witha new Yn+1 function as written in

Ynþ1ðVGSÞ ¼ YnðVGSÞffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

1� h2 VGS � Vth � VDS

2

� �2s

ð9Þ

This should eliminate the influence of h2 in (5) and new valuesof GM, Vth, h1 and h2 can be extracted, until the values converge.Examples of drain current and transconductance concordancebetween the experimental data and models of the drain currentand of the transconductance described by Eqs. (4) and (5) areshown in Fig. 2. The right y-axis indicates that the absolute relativeerror is less than 0.1% for the drain, which reflects the good preci-sion of this extraction procedure.

Several parameters can be extracted once the Y functionmethod has been applied to devices with different gate dimensions[3]. The effective gate dimensions L andW can be determined usingGM and the mask gate dimensions Lm and Wm, as

GM ¼ l0CoxWL

¼ l0Cox

LðWm � DWÞ ð10:aÞ

1GM

¼ Ll0CoxW

¼ 1l0CoxW

ðLm � DLÞ ð10:bÞ

Assuming l0 is constant, both equations lead to a straight line,where the slope and the x-intercept of GM(Wm) or GM

�1(Lm) lead tol0 and DW or DL, respectively.

The extrinsic mobility attenuation factor h1 depends of the gatedimensions W and L, and on the access resistance Raccess accordingto (7). Consequently a h1(GM) function will give access to the intrin-sic mobility attenuation factor h10 and the drain-source resistanceRaccess.

The channel length reduction DL can also be determined withanother method that consists in tracing the evolution of the total

Fig. 2. MOSFET drain current (a) and transconductance (b). The Y function methodleads to a model for both characteristics in strong inversion (in red). The relativeerror (in blue) in strong inversion remains below 5% for the transconductance. (Forinterpretation of the references to colour in this figure legend, the reader is referredto the web version of this article.)

Fig. 3. MOSFET static parameters extraction. The access resistance Raccess and thechannel length reduction DL are obtained from the intercept of Rtot(Lm) lines atdifferent VGT.

Fig. 4. MOSFET noise model with a representation of the three noisy region, whichare the drain region (between nodes D and D0), the inversion channel (betweennodes D0 and S0) and the source region (between nodes S0 and S).

104 D. Boudier et al. / Solid-State Electronics 128 (2017) 102–108

resistance (i.e. of ID/VDS) at different gate voltages VGS for differentgate mask lengths, using the channel resistivity qch in the relation

Rtot ¼ LW

qch þ Raccess ¼ Lm � DLW

qch þ Raccess ð11Þ

All lines should intercept at the same point, which coordinatesare DL and Raccess, as seen in Fig. 3.

3. Low frequency noise

3.1. Low frequency noise in MOSFETs

The characterization of the low frequency noise in field-effecttransistors is performed from measurements of the noise powerspectral density (PSD), which is usually referred either to the draincurrent (SID in A2/Hz) or to the gate voltage (SVG in V2/Hz). Bothquantities are linked together by the MOSFET transconductanceas SVG � gm2 = SID.

The noise mainly originates from the resistive parts of the tran-sistors, which are the source region (rS), the drain region (rD) andthe channel (rch). The low frequency noise equivalent circuit isgiven in Fig. 4, where the resistive (noisy) parts have been modeledby uncorrelated current noise sources. The drain region is betweenthe points D and D0, the channel is between D0 and S0 and the sourceregion is between S0 and S. From this schematic we can write thetotal drain current noise iD,tot as

iD;tot ¼ gm � vGS0 þ gch � vD0S0 þ ich ð12Þ

where gch = rch�1 is the channel conductance. The vGS0 and vD0S0 volt-

ages are

vGS0 ¼ �vS0S ¼ �rSðiD;tot � irSÞ ð13:aÞ

vD0S0 ¼ �vDD0 � vS0S ¼ �rDðiD;tot � irD Þ � rSðiD;tot � irS Þ ð13:bÞFrom (12) and (13) the total current noise in MOSFETs can be

expressed by

iD;tot ¼ ich þ irD � gchrD þ irS � rSðgm þ gchÞ1þ gmrS þ gchðrS þ rDÞ ð14Þ

The total current noise PSD SID;tot can be written as a function ofthe channel current noise PSD SIch , the drain region noise PSD SIrDand the source region noise PSD SIrS

SID;tot ¼SIch þ SIrD ðgchrDÞ2 þ SIrS ½rSðgm þ gchÞ�2

½1þ gmrS þ gchðrS þ rDÞ�2ð15Þ


It is convenient to assume that the source and the drain regionbehave the same way, so that rD = rS = raccess/2 and SIrD ¼ SIrS . In lin-ear operation can be considered gm � gch, then (15) yields

SID;tot ¼ SIchðrtot � raccessÞ2

r2totþ SIR

r2access2r2tot

ð16Þ

where rtot is the transistor total dynamic resistance (between thepoints D and S in Fig. 3).

3.2. White noise

The white noise is characterized by its level Kw, which is con-stant in the frequency domain, and has two main origins. The firstone is the thermal noise (Johnson noise [6] or Nyquist noise [7]),which is due to the thermal motions of the electrons in the crystallattice. Its voltage noise PSD is equal to SVG = 4 k � T � R, k being theBoltzmann constant, T the temperature and R the resistance of thepiece of material.

The second one is the shot noise and has been described bySchottky in 1918 [8]. It is due to the random number of charge car-riers that flows across a potential barrier at a given time. For anaverage current I flowing through a potential barrier, the currentnoise PSD is SID = 2 q � I.

3.3. Generation-recombination noise

The generation-recombination (GR) noise is represented in thefrequency domain by a Lorentzian shape, which consists in a pla-teau of level A followed by a 1/f2 decrease starting at the character-istic frequency f0. The latter parameter is linked to thecharacteristic time constant s. GR noise is due to traps (in the gateoxide and in the depletion region) that randomly capture andrelease channel carriers, resulting in fluctuations of the availablecarriers for the current flow. Those traps may also induce changesin the carrier mobility, the scattering coefficient, the electric fieldand the potential barrier. It becomes significant when the Fermienergy level is close to the trap energy level, meaning that it is verysensitive to temperature [9].

Several Lorentzians can appear in the frequency spectrum, eachhaving different values of Ai and f0,i (and si) following (17) [10]. Ifthe trap characteristic time constants are distributed in a preciseway, the sum of the Lorentzians can have a 1/f shape over severaldecades of frequency.

SVG;lori¼ Ai

1þ ff 0;i

� �2 ¼ Ai

1þ ð2pfsiÞ2ð17Þ

If the gate surface is small enough (usually below 1 lm2) only afew traps are involved in the generation-recombination noise,meaning that the number of channel carriers being captured andreleased at a given time is also small. Thus the drain current dis-plays a typical behavior in the time domain as a burst noise (alsocalled Random-Telegraph-Signal, or RTS noise) appears superposedon the ‘‘classical” noise.

From [11] the trap characteristic time constant s of ageneration-recombination process is given by

s ¼ 1Cnðn1 þ nÞ þ Cpðp1 þ pÞ ð18Þ

with Cn and Cp the electrons and holes capture coefficients, respec-tively, n and p the free electrons and holes concentrations, respec-tively, n1 and p1 the concentrations of free electrons and holesunder when the Fermi level coincides with the noisy trap level. Inany case n, p, n1 and p1 vary with the temperature following anexponential dependency, which means that Lorentzians character-

istic time constants are temperature dependent. Nevertheless thevariation of the characteristic time constants on the gate voltagedepends on the localization of the traps in the transistor (either inthe depletion film or at the Si-SiO2 interface).

For Lorentzians that are related to interface traps, the Fermilevel always coincides with the traps energy level [12] and n = n1and p = p1, then s = [2(Cn � n1 + Cp � p1)]�1. As the gate voltage |VGS|increases, the distance between the Fermi level and the edge ofthe majority carrier band increases, which leads to an increase ofs. However for a further increase of |VGS| the Fermi levelapproaches the minority carrier band and s then decreases.

In the depletion region, free electrons and holes are practicallyabsent, so the approximation n = p = 0 can be used in (18) andyields s = (Cn � n1 + Cp � p1)�1. Traps close to the midgap have a con-centration of n1 � p1 � ni, where ni is the intrinsic carrier concen-tration. This leads to a value of s = [ni � (Cn + Cp)]�1, which isindependent of the gate voltage |VGS|.

3.4. 1/f noise

Several models have been proposed in order to explain 1/f noisein the inversion layer. The carrier number fluctuations model (DN)was first described by McWhorter in 1957 and it suggests that car-rier tunneling into the oxide is the origin of the 1/f noise [13]. Car-rier mobility fluctuations model (Dl) described by Hooge in 1969explains that the 1/f noise is due to phonon scattering [14]. A car-rier number fluctuations correlated to mobility fluctuations model(DN +Dl) has been suggested in 1990 [15,16]. It states that oxidetraps that capture and release channel carriers change the numberof available carriers, which leads to surface mobility fluctuations.

In the case of carrier mobility fluctuations model, the gate volt-age noise PSD of the channel can be written as [3]

SVG ¼ qaH

f W LCoxðVGS � VthÞ½1þ h1ðVGS � VthÞ�2 ð19Þ

where aH is the Hooge parameter and depends of the crystal quality.In weak inversion, the normalized drain current noise PSD SID=I

2D is

inversely proportional to VGS � Vth.For the DN + Dl model, the gate voltage noise PSD can be

expressed by [17]

SVG ¼ SVfbð1� aCleff CoxVGTÞ2 ð20Þ

where SVfb is the flat-band spectral density and aC is the Coulombscattering coefficient. The + and the � signs apply for donor andacceptor traps, respectively. This equation requires no assumptionabout the mechanism behind the fluctuations in the flat-band volt-age [18]. However if aCleff CoxVGT � 1, then SVG ¼ SVfb

and only car-rier number fluctuations noise is observed.

As the noise of the access resistance can be modeled by the for-mula SID ;access ¼ Kr

f I2D [19], with Kr being the access resistance noise

parameter, we can write from (16), (19) and (20) the total gatevoltage spectral density in ohmic region operation

SVG ¼ ðrtot � raccessÞ2r2tot

qaH

f W LCoxðVGS � VthÞ½1þ h1ðVGS � VthÞ�2

þ Kr

fr2access2r2tot

I2Dg2m

ð21:aÞ


SVfbð1þ aCleff CoxVGTÞ2 þ Kr

fr2access2r2tot

I2Dg2m

ð21:bÞ

The first term of (21.a) and (21.b) corresponds to the Dl modeland the DN + Dl model, respectively. The second term corre-sponds to the access resistance noise, usually observed in stronginversion.

Fig. 6. Total noise PSD model (in black). The total noise PSD is the sum of the whitenoise, the 1/f noise and one Lorentzian.


4. Methodology

4.1. Experimental bench

The device under test (DUT) is placed into a Lakeshore TTP4cryogenic probe station. The low frequency noise experimentalbench uses home-made electronics and a HP 3562A dynamic signalanalyzer. A simplified schematic of these electronics is shown inFig. 5. The transistor is biased with VDS and VGS voltage sources,the resulting drain current ID flows through the retroaction resis-tance of the transimpedance amplifier and the voltage measuredby the voltmeter allows checking the bias point, asVOUT ¼ VDS þ R � ID.

The drain noise current iD is converted into a voltage after thetransimpedance stage, then this voltage passes through the high-pass filter (cut-off frequency of 0.08 Hz) and is amplified by aninstrumentation amplifier. The spectrum analyzer finally providesthe output voltage noise PSD SVout from 1 Hz to 100 kHz.

In order to get the input-referred noise PSD (i.e. the gate voltagenoise PSD), white noise is injected into the gate (vgs voltage sourcein Fig. 5) after the output PSD measurements. The ratio betweenthe output voltage and the white noise voltage gives the whole sys-tem gain, which allows to get the gate voltage noise PSD as

SVG ¼ SVout=gain2 and to get rid of the system bandwidth limitation.

4.2. Noise model

The low frequency noise is generally due to the contributions ofthree distinct noises, which are the white noise (of a constant levelKw), the 1/f noise (of level Kf) and the generation-recombinationnoise. The latter can present several Lorentzians (of plateau levelAi and characteristic frequency f0,i) in the noise PSD. The gate volt-age noise PSD SVG can be seen as the sum of these three noisesources and is written

SVG ðf Þ ¼ Kw þ Kf

f cþX

N

i¼1

Ai

1þ ðf=f 0; iÞ2ð22Þ

Fig. 5. Simplified schematic of the low fr

A value of c = 1 means that the traps are uniformly distributedin the gate oxide depth. Fig. 6 shows a gate voltage noise PSDmodel and its different components using (11).

However, in order to better extract the noise parameters, onecan use a noise PSD normalized by the frequency, as displayed inFig. 7. The 1/f noise is then represented by a constant value whilethe Lorentzians correspond to bumps centered around their char-acteristic frequency f0,i. As it is more convenient to find f0,i, itreduces the estimation errors on the plateau levels Ai. Conse-quently using the model described by (22) leads to the white noiselevel Kw, the 1/f noise level Kf and the Lorentzians parameters Ai

and f0,i.

4.3. 1/f noise mechanism and oxide trap density

In order to determine the 1/f noise mechanism, one has toperform noise measurements as a function of the gate voltage

equency noise measurements bench.

Fig. 7. Frequency-normalized gate voltage noise PSD. The noise model (20) allowedto extract the noise parameters (white noise level Kw, 1/f noise level Kf andcharacterization of three Lorentzians).


VGS (or drain current ID). For each noise PSD, a noise modelmust be performed using (21), which leads to the 1/f noiselevel Kf. The evolution of Kf as a function of VGS (or ID) leadsto the 1/f noise mechanism, according to (21.a) and (21.b).Table 1 summarizes the evolution of SVG and SID=I

2D using (21.

a) and (21.b).As the values of the effective mobility leff, the mobility attenu-

ation factor h1 and the access resistance raccess have been extractedwith static measurements, the coulomb scattering coefficient aCand the flat-band voltage PSD SVfb (for DN +Dl model) or theHooge parameter aH (for Dlmodel) can be determined. In the caseof number fluctuations correlated to mobility fluctuations, the flat-band voltage PSD leads to an estimation of the oxide trap densityNT, according to the formula

SVfb¼ q2kT kNT

f cWLCoxð23Þ

where k is the tunneling attenuation length in the gate oxide (�1 Åfor Si/SiO2).

4.4. Silicon film traps: noise spectroscopy

As for studying the 1/f noise, the Lorentzian parameters (pla-teau level Ai and characteristic frequency f0,i) are obtained fromnoise PSD modelling at different values of VGS and at fixed tem-perature, using (22). As explained above, Lorentzians with acharacteristic frequency that is independent of the gate voltageare considered to be related to traps in the depletion regionwhereas Lorentzians with a characteristic frequency thatdepends on VGS are located in the gate oxide. However theircharacteristic frequency should vary with the temperature inboth cases. Lorentzians with fixed f0,i as a function of VGS havebeen studied in order to identify the physical nature of the Sifilm traps. To do so, one must perform noise spectroscopy, i.e.

Table 1Evolution of the 1/f noise PSD (SVG and SID) with respect to the gate overdrive voltage VGT

(Dl), and the access resistance noise model.

Channel noise: DN + Dl fluctuations

aCleff CoxVGT � 1 aCleff CoxVGT 1

SVG / Constant1� aCleff CoxVGT

� �2

SIDI2D

/ gmID

� �2 gmID

� �21� aCleff CoxVGT

h i2

noise measurements at different temperatures and at constantdrain current ID.

The characteristic time constant si of a single trap varies withtemperature, according to the expression [1]

lnðsiT2Þ ¼ ðEC � ETÞ qkT

þ lnh3

4k2rn

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

6p2Mcm�1=2e m�3=2

h

q

0

B

@

1

C

A

ð24Þ

where rn is the trap capture cross section and EC � ET is thedifference between the conduction band energy level and the trapenergy level. k is the Boltzmann constant, h is the Planckconstant, me

⁄ and mh⁄ are the effective mass of electrons and

holes, respectively, and Mc is the number of conduction bandenergy minima.

From the characteristic time constant si and the tempera-ture, one can trace the evolution of ln(siT2) with respect toq/kT, which is an Arrhenius diagram and should give a straightline. By using (23) the estimated capture cross section rn andenergy difference EC � ET can be determined and comparedwith data in the literature. Indeed Arrhenius diagrams of com-mon traps are known from other methods, like Deep LevelTransient Spectroscopy. If experimental points fit one particularline, then the associated Lorentzians correspond to the sameparticular trap.

Once traps have been identified, the associated plateau levels Ai

should be traced against the characteristic time constants si. Thisshould give a straight line and lead to the surface (effective) trapdensity Neff for each trap, according to

Ai ¼ q2Neff

W LC2ox

si ¼ q2WdNT

W LC2oxB

si ð25Þ

where q is the elementary charge, NT is the volume trap density, Wd

is the depletion depth and B is a coefficient. B is usually predicted tobe 1/3 for planar devices [19], however this does not apply well formulti-gate devices [20]. Consequently, even though siliconfilm traps are related to a volume phenomenon, the surface trapdensity Neff will be extracted as it requires no assumption of thecoefficient B.

5. Conclusion

This paper has presented the main noise parameters that canbe extracted, either from the 1/f noise or the generation-recombination noise. First static characteristics need to beperformed in order to extract DC parameters that will be usedfor noise characterization, such as the threshold voltage Vth, thelow-field mobility l0, the mobility attenuation factor h and theaccess resistance raccess. Then gate voltage noise measurementscan be performed in order to determine the 1/f noisemechanism and the gate oxide trap density NT. Finally a lowfrequency noise spectroscopy leads to the identification ofdepletion region traps and an estimation of their effectivedensities Neff.

or the drain current ID, according the McWhorter model (DN + Dl), the Hooge model

Channel noise: Dl fluctuations Access resist. noise

VGT ½1þ h1VGT �2 I2Dðrtot gmÞ2

1VGS�Vth

1r2tot


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[18] Talmat R et al. Low frequency noise characterization in n-channel FinFETs.Solid-State Electron 2012;70:20–6.

[19] Hooge FN. 1/f noise sources. IEEE Trans Electron Dev 1994;41:1926–35.[20] Achour H et al. Identification of Si film traps in p-channel SOI FinFETs

using low temperature noise spectroscopy. Solid-State Electron2015;112:1–6.


















































Low frequency noise assessment in n- and p-channel sub-10 nmtriple-gate FinFETs: Part II: Measurements and results


⇑ Corresponding author.E-mail address: [email protected] (D. Boudier).

D. Boudier a,⇑, B. Cretu b, E. Simoen c, R. Carin a, A. Veloso c, N. Collaert c, A. Thean c

aUniversity of Caen Normandie, UMR6072 GREYC, F-14050 Caen, Franceb ENSICAEN, UMR6072 GREYC, F-14050 Caen, Francec Imec, Kapeldreef 75, B-3001 Leuven, Belgium




Keywords:Triple-gateFinFETLow frequency noise1/f noiseGeneration recombinationTraps

Low frequency noise measurements are used as a non-destructive diagnostic tool in order to evaluate thequality of the gate oxide and the silicon film of sub-10 nm triple-gate Silicon-on-Insulator (SOI) FinFETs.It was found that the carrier number fluctuations explain the 1/f noise in moderate inversion for n- and p-FinFETs, which allows estimating the gate oxide trap densities. The noise spectroscopy with respect totemperature (study of the generation-recombination noise) led to the identification of the traps locatedin the transistors silicon film.


1. Introduction

In order to meet the ITRS specifications in terms of CMOS down-scaling, new materials, designs and structures are necessary [1].Triple-gate FinFETs are known for their good electrostatic perfor-mances and their compatibility with CMOS processes as a contin-uation of Moore’s law [2].

Low-frequency noise measurements can be used as a non-destructive diagnostic tool that leads to the identification of trapsin the Si film and the gate oxide, thus giving information on thequality of the transistors fabrication. The study of the 1/f noiselevel with respect to the gate overdrive voltage VGT leads to theidentification of the 1/f noise origin. The study of the generationrecombination (GR) noise is performed as a function of the temper-ature at fixed drain current. This low frequency noise spectroscopycan give access to information on the traps located in the depletionregion of the transistor [3].

In this work, static and dynamic parameters have beenextracted in n- and p-channel triple-gate Silicon-on-Insulator(SOI) FinFETs. Low-frequency noise has been investigated in orderto determine the quality of those devices. First the main staticparameters of the devices have been extracted at 300 K, then the

1/f noise level has been studied as a function of the gate voltageand, finally, the generation-recombination noise has been investi-gated in function of temperature. The theory and methodology thatare useful for the parameters extraction are explained in an accom-panying Part I paper [4].

2. Devices and experimental

The tested devices have been processed at imec (Belgium) forsub-10 nm technological nodes, in the framework of a comparativestudy between triple-gate FinFETs and gate-all-around (GAA)nanowire (NW) FETs, fabricated on SOI substrates [5]. The gatestack consists of a high-j dielectric (HfO2) on top of a SiO2 interfa-cial layer. Each layer is 1.5 nm wide, which leads to an equivalentoxide thickness EOT = 1.9 nm. The gate stack is followed by EWF(TiN) andW-fill metal depositions. All tested transistors have 5 fin-gers of 22–23 nm height; the finger width varies from Wfin = 5 nmto 40 nm, which gives a total gate width going from Wm = 245 nmto 420 nm. The finger pitch is 200 nm and the gate length variesfrom Lm = 45 nm to 10 lm. The transistors are built on a buriedoxide (BOX).

The static and noise measurements have been performed onchip using a Lakeshore TTP4 prober. The DC characteristics havebeen obtained with a HP 4156B. Output noise power spectral den-sities (PSDs) have been measured using a home-made set-up,








which includes a low-noise transimpedance amplifier and a HP3562A dynamic signal analyzer. This set-up allows to bias transis-tors by choosing the VGS, VDS and VBS voltages. The noise spectraldensities are measured from 1 Hz to 100 kHz. The input referredgate voltage noise PSD SVG is obtained by dividing the measurednoise voltage by the square of the measured voltage gain betweenthe gate and the system output. This cancels the set-up bandwidthlimitation.

The static parameters extraction has been performed usingID(VGS) characteristics at 300 K. The drain voltage has been set toVDS = 20 mV so the transistors works in the linear operation regimeand the bulk has been connected to the source VBS = 0 V. The lowfrequency noise has been measured as a function of temperaturefrom 220 K to 300 K by steps of 20 K at fixed drain current ID. Asfor static measurement the linear operation regime is reached withVDS = 20 mV and VBS = 0 V, then the gate voltage VGS was adjusted inorder to set the fixed drain current from ID = 1 lA to 5 lA by 0.5 lAsteps. This paper shows the results obtained for n-channel andp-channel FinFETs with a finger width of Wfin = 20 nm and 30 nm.

3. Static parameters extraction

The transistors have been studied in linear operation (VDS =20 mV) at room temperature. Good behavior of the transfer DCcharacteristics ID(VGS) and gm(VGS) is observed for both n- andp-channels, as shown in Fig. 1.

Static parameters extraction has been further processed usingthe Y function method (Y ¼ ID=

ffiffiffiffiffiffi

gmp

[3]), which gives access tothe threshold voltage Vth and the transconductance parameterGM = l0 Cox W/L. The values that will be discussed in this paperhave been obtained for two iterations of the Y function method.

Fig. 1. Typical ID(VGS) and gm(VGS) characteristics

Once the basic DC parameters have been determined with the Yfunction method for different gate lengths Lm, the low-field mobil-ity l0 and the access resistances Raccess can also be extracted from aset of transistors with different gate lengths [4]. As the transcon-ductance parameter GM is defined by GM = l0 Cox W/L, one can write

1GM

¼ Ll0CoxW

¼ 1l0CoxW

ðLm � DLÞ ð1Þ

The low-field mobility l0 and the channel length reduction DLvalues can be determined from the slope and the y-intercept ofGM

�1(Lm), respectively. The points corresponding to different gatelengths are shown in Fig. 2, on which a linear regression has beenperformed in order to estimate l0 andDL. For these n-FinFETs withWfin = 30 nm, we have found that l0 = 259 cm2/(V�s) andDL = 4.8 nm.

The effective (extrinsic) mobility attenuation factor h1 is definedby

h1 ¼ h10 þ GMRaccess ð2Þ

thus the plot of h1(GM) should give a straight line where the slope isequal to Raccess and the y-intercept is equal to h10, as shown in Fig. 3.For the same n-FinFETs (Wfin = 30 nm), values of Raccess = 370X andh10 = 707 mV have been recorded.

The values of the access resistances have been confirmed usingthe linear variations of the total resistance for various gate over-drive voltage VGT against the gate mask length Lm. The value ofthe access resistance is determined at the common intersectionof all lines, as shown in Fig. 4. In this case values of Raccess = 375Xand DL = 5.5 nm have been derived, which confirms the resultsthat have been obtained with the previously explained method.

of n- and p-FinFET for various gate lengths.

Fig. 2. Extraction of the low-field mobility l0 and gate length reductionDL from thelinearisation of GM

�1(Lm).

Fig. 3. Extraction of the intrinsic mobility attenuation factor h10 and accessresistance Raccess from the linearisation of h1(GM

�).

Fig. 4. Example of DC parameters extraction, giving the value of the accessresistance Raccess.


A synthesis of the estimated static parameters is showed inTable 1. It can be observed that the threshold voltage Vth is higher(in absolute value) for n-channel transistors than for p-channeltransistors. The charge sharing effect is more pronounced for p-channel devices, in particular for smaller finger widths. Higher val-ues of the low-field mobility l0 can be observed for thinner fingersin both n- and p-channel transistors; this could be related to theeffective values of the gate width and to the relative contributionof the sidewall versus top surface conduction. The access resis-tances are higher for p-channel FinFETs compared to the n-channel ones. The increase of the access resistance with the fingerwidth decrease from 30 nm to 20 nm, observed for p-FinFETs,could be related to the effective values of the gate width.

4. 1/f noise

All the noise PSDs can be modeled using a combination of threenoise sources: white noise (of level Kw), 1/f noise (or flicker noise,of level Kf) and generation-recombination (GR) noise (of plateau Ai

and characteristic frequency f0,i). Assuming that the three noisesources are uncorrelated, the total noise PSD follows the equation

SVG ðf Þ ¼ Kw þ Kf

fþX

N

i¼1

Ai

1þ ðf=f 0;iÞ2ð3Þ

As seen in [4], the 1/f noise contribution of the total gate voltagespectral density SVG in ohmic operation can be expressed by


SVfbð1þ aCleff CoxVGTÞ2 þ Kr

fr2access2r2tot

I2Dgm

ð4Þ

where rtot is the total dynamic resistance of the transistor betweensource and drain, raccess is the dynamic access resistance for bothsource and drain regions, SVfb is the flat-band voltage power spectraldensity, aC is the Coulomb scattering coefficient, leff is the carriereffective mobility and Kr is an access resistance coefficient. The firstterm of (4) corresponds to the carrier number fluctuations corre-lated to mobility fluctuations model (DN + Dl) in the inversionlayer while the second term corresponds to the access resistancenoise, usually observed in strong inversion.

From the gate voltage noise power spectral density SVG one candetermine the 1/f noise level Kf with the model described in (3). Byperforming measurements at different values of gate voltage VGS

(thus at different fixed values of drain current ID) at fixed temper-ature, one can study the variations of the flicker noise level as afunction of the gate voltage in order to determine the 1/f noisemechanism.

The evolution of the 1/f noise level Kf with the gate overdrivevoltage leads to the identification of the 1/f noise origin. Fig. 5shows the evolution of Kf for both n- and p-channel devices andcompares them to models given by (4). One can observe thatn-FinFETs follow the carrier number fluctuations correlated tomobility fluctuations model (DN + Dl). However, p-channel tran-sistors trend to follow the number fluctuations model DN in mod-erate inversion while the total 1/f noise in strong inversion seemsto originate from the access resistance noise contribution [6].

The extraction of the flat-band voltage spectral densities SVfbleads to an estimation of the oxide trap densities NT, according tothe formula

SVfb¼ q2kTkNT

fWLCoxð5Þ

where k is the tunneling attenuation length in the gate oxide (�1 Åfor Si/SiO2). Trap density values from 6.5 � 1018 to 12 � 1018 eV�1�cm�3

for n-channel and from 0.8 � 1018 to 4.6 � 1018 eV�1�cm�3 forp-channel FinFETs have been obtained, as shown in Table 2. These

Table 1Synthesis of DC parameters of several n-FinFETs and p-FinFETs.

Wfin/Wm (nm/nm) Lm (nm) Vt (mV) l0 (cm2/V�s) Raccess (X)

n-channel FinFETs 20/320 70 732 338 37520/320 250 79320/320 1000 75230/370 70 727 256 44130/370 250 72630/370 1000 740

p-channel FinFETs 20/320 70 �69 190 121020/320 250 �13120/320 1000 �23530/370 70 �144 169 59430/370 250 �23230/370 1000 �295

Fig. 5. Evolution of the 1/f noise level Kf with respect to VGT, for a n- and a p-channelFinFET with the same gate dimensions. The red line corresponds to the DN + Dlmodel in moderate inversion for the n-FinFET (with l0 = 256 cm2/Vs), the pink linecorresponds to the DN model in moderate inversion for the p-FinFET and the greenline represents the access resistance noise contribution in strong inversion for thep-FinFET. (For interpretation of the references to color in this figure legend, thereader is referred to the web version of this article.)


values show a small difference between n- and p-channel devices,the latter being slightly less impacted by 1/f noise. However, valuesof the oxide trap density around 1018 eV�1�cm�3 show a good qual-ity of the gate stack deposition process for both types.

Fig. 6. Evolution of the Lorentzians characteristic frequency f0,i with respect to thegate overdrive voltage VGT.

5. Generation-recombination noise

The Lorentzians parameters can be studied once the gate volt-age noise PSDs have been modeled using (3). Lorentzians with acharacteristic frequency that is independent of the gate voltage

Table 2Summary of flat-band voltage spectral densities SVfb and oxide trap densities NT of severa

Wfin/Wm (nm/nm) Lm

n-channel FinFETs 20/320 7020/320 2530/370 7030/370 25

p-channel FinFETs 20/320 7020/320 2530/370 7030/370 25

are considered to be related to traps in the depletion region; how-ever their characteristic frequency should vary with the tempera-ture. Examples of the Lorentzians characteristic frequency f0,ievolution with respect to the gate overdrive voltage VGT is shownin Fig. 6. For this n-FinFET at a fixed temperature, one can observethat the characteristic frequency of some Lorentzians increaseswith VGT (may be related to traps located in the gate oxide), whilethe characteristic frequency of the other Lorentzians is constantwith the applied gate voltage (may be related to traps in the deple-tion film) [7]. Only the latter have been studied for the noise spec-troscopy, as shown in Fig. 7.

These Lorentzians have been studied in order to identify thephysical nature of the Si film traps, by using [3]

l N- and P-FinFETs.

(nm) SVfb (V2/Hz) NT (eV�1�cm�3)

6 � 10�9 6.5 � 10180 8 � 10�9 10 � 1018

3 � 10�9 12 � 10180 2 � 10�9 8.9 � 1018

2.2 � 10�9 2.4 � 10180 0.6 � 10�9 0.75 � 1018

1.2 � 10�9 4.6 � 10180 0.7 � 10�9 3.1 � 1018

Fig. 7. Example of the gate noise PSD normalized by the frequency measured atdifferent temperatures and at VDS = 20 mV, ID = 2 lA. The variation of theLorentzians characteristic frequency (associated to Si fin traps) with temperatureis represented by the arrows.

Fig. 8. Example of Arrhenius plot for a n-channel FinFET, leading to the identifi-cation of the Si fin traps.

Table 3Summary of parameters of the identified traps.

EC – ET (eV) rn (cm2) T (K) Neff (cm�2)

V2H 0.45 1.4 � 10�16 260–300 4.32 � 1010V2(0/�) 0.42 3.8 � 10�16 220–260 0.862 � 1010V-P 0.44 7.5 � 10�15 240–260 –VOH 0.32 1.3 � 10�15 220–260 12.8 � 1010

Fig. 9. Estimation of the effective trap densities Neff from the linear variation of theLorentzians plateau level Ai against the characteristic time constant si (associated tothe same trap).


lnðsiT2Þ ¼ ðEC � ETÞ qkT

þ lnh3

4k2rn

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

6p2Mcm�1=2e m�3=2

h

q

0

B

@

1

C

A

ð6Þ

and comparing the estimated capture cross section rn and energydifference EC ET with data in the literature. The Lorentzians charac-teristic frequency evolution with the temperature leads to a typicalArrhenius plot, as shown of Fig. 8, for a n-channel FinFET withWm/Lm = 10 nm/70 nm. The physical nature of these traps can beidentified by comparing the energy and capture cross section ofthe traps with data in the literature. There are traps related to

hydrogen (V2H and VOH) [8–10], the single negatively chargedacceptor state (0/�) of the divacancy (V2) [9,11] and thephosphorus-vacancy complex (VP) [10]. The presence of trapsrelated to hydrogen could be explained by the hydrogen incorpo-rated during the selective epitaxial growth of the raised source/drains from the SiH4 precursors used in the chemical vapor deposi-tion. Divacancies may be due to the recombination or the evolutionto a stable state of the unstable defects like Frenkel pairs, whichcould be generated during the implantation [12]. The identifiedtraps are shown in Table 3, which gives the energy differencebetween the conduction band and the trap level, the electron cap-ture cross section and the temperature range of the traps.

Finally one can extract the surface trap density Neff of the iden-tified traps by plotting the Lorentzian plateau level against its char-acteristic frequency, according to

Ai ¼ q2Neff

WLC2ox

si ð7Þ

The plateau levels Ai of Lorentzians corresponding to the identi-fied traps have been traced against their characteristic time con-stant si, as shown in Fig. 9. Using (7), the slope of the linearregressions leads to the effective surface trap density Neff, whichhas been extracted for the V2H, V2 and VOH related traps. The esti-mated values of the effective surface trap densities are4.32 � 1010 cm�2, 0.862 � 1010 cm�2 and 12.8 � 1010 cm�2 for V2H,V2 (0/�) and VOH, respectively.

6. Conclusion

Low frequency noise studies showed that the 1/f noise mainlyoriginates from the carrier number fluctuations. The study of theevolution of the 1/f noise level Kf with the gate overdrive voltageVGT led to an estimation of the gate oxide trap density for n- andp-channel FinFETs. The estimated trap densities vary aroundNT � 1018 eV�1�cm�3, which reflects a good quality of the gate stackprocessing as a comparison to 32-nm technology FinFETs [13].

The low frequency noise spectroscopy allowed studying theevolution of the generation-recombination noise as a function ofthe temperature. The evolution of the Lorentzians characteristicfrequency led to the identification and the effective density ofthe Si film traps, which are either related to hydrogen or divacan-cies. From the nature of the traps, it can be suggested that theimplantation and the use of selective epitaxial growth in the sourceand drain regions are mainly responsible for the observed traps.


References

[1] International Technology Roadmap for Semiconductors. <http://www.itrs.net>.

[2] Natarajan S et al. A 14nm logic technology featuring 2nd generation FinFETtransistors, air-gapped interconnects, self-aligned double patterning and a0.0588lm2 SRAM cell size. IEDM Tech Dig 2014:71–3.

[3] Grassi V, Colombo CF, Camin DV. Low frequency noise versus temperaturespectroscopy of recently designed Ge JFETs. IEEE Trans Electron Dev2001;48:2899–905.

[4] Boudier D, et al. Low frequency noise assessment in n- and p-channel sub-10nm triple-gate FinFETs: Part I: Theory and methodology. Solid-State Electron2017;128:102–108.

[5] Veloso A et al. Gate-all-around NWFETs vs. triple-gate FinFETs: junctionless vs.extensionless and conventional junction devices with controlled EWFmodulation for multi-VT CMOS. VLSI Technol 2015:T138–9.

[6] Lukyanchikova N. Sources of the Lorentzian components in the low-frequency noise spectra of submicron metal-oxide-semiconductor field-effect transistors. In: Baladin A, editor. Noise and fluctuations control in

electronic devices. Riverside (CA): American Scientific Publishers; 2001. p.201–33.

[7] Ghibaudo G. Critical MOSFETs operation for low voltage/low power IC’s: idealcharacteristics, parameter extraction, electrical noise and RTS fluctuations. JAppl Phys 1997;39:31–57.

[8] Tokuda Y, Shimizu, Usami A. Studies of neutron-produced defects insilicon by deep-level transient spectroscopy. Jpn J Appl Phys 1979;18(2):309–15.

[9] Hallen A, Keskitalo N, Masszi F, Nagl V. Lifetime in proton irradiated silicon. JAppl Phys 1996;79(8):3906–14.

[10] Claeys C, Simoen E. Radiation effects in advanced semiconductor material anddevices. Springer Verlag; 2002.

[11] Bains SK, Banbury PC. AC hopping conductivity and DLTS studies on electron-irradiated boron-doped silicon. Semicond Sci Technol 1978;2(1):20–9.

[12] Agullo-Lopez F, Catlow CRA, Townsend PD. Point defects inmaterials. Academic Press; 1988.

[13] Talmat R et al. Low frequency noise characterization in n-channel FinFETs.Solid-State Electron 2012;70:20–6.

http://www.itrs.net

http://www.itrs.net




































Systematic method for electrical characterization of random telegraphnoise in MOSFETs


⇑ Corresponding author.E-mail address: [email protected] (C. Marquez).

Carlos Marquez a,⇑, Noel Rodriguez a, Francisco Gamiz a, Akiko Ohata b

aDepartment of Electronics, CITIC-University of Granada, 18071 Granada, SpainbCollaboration Center for Research and Development, Utsunomiya University, Japan




Keywords:Random telegraph noiseMOSFET reliabilityLow frequency noise (LFN)

a b s t r a c t

This work introduces a new protocol which aims to facilitate massive on-wafer characterization ofRandom Telegraph Noise (RTN) in MOS transistors. The methodology combines the noise spectral densityscanning by gate bias assisted with a modified Weighted Time Lag Plot algorithm to identify unequivo-cally the single-trap RTN signals in optimum bias conditions for their electrical characterization. Thestrength of the method is demonstrated by its application for monitoring the distribution of traps overthe transistors of a SOI wafer. The influence of the back-gate bias on the RTN characteristics of the SOIdevices with coupled front- and back-interfaces has revealed unusual characteristics compatible withthe carrier emission to the gate metal contact.


1. Introduction

Random Telegraph Noise (RTN) prevails as a major constrainwhen the characteristic dimensions of the semiconductor devicesare downscaled to the decananometer range [1,2]. Paired withthe decrease of the signal levels, the introduction of new technolo-gies, such as high-k metal-gate stacks and ultrathin Silicon-On-Insulator substrates, entails the appearance of additional contribu-tions to the RTN, related with the quality of the new materials orthe electrostatic coupling between the top-channel and the Si-film/BOX interface [3,4]. These new effects also require powerfulcharacterization tools to cope with the massive monitoring of thetransistors over the wafer, aiming to extract useful statistical infor-mation to nourish the optimization of the fabrication processflows. The systematic characterization protocol that we areproposing allows the detection of transistors with a single activetrap, identifying the best operation region to characterize theRTN signature. This method is based on the Spectral Scanning byGate Bias (SSGB) combined with a modified Weighted Time LagPlot (w-TLP) approach.

On the following pages, Section 2 describes the methodologyand the experimental setup on which this work is based. Section 3introduces the Spectrum Scanning by Gate bias to easily trace theRTN in the time-domain, whereas in Section 4, we apply theWeighted Time Lag Plot to analyze the number of traps of the

devices over the wafer. Finally, in Section 5, we implement thetechnique to study the role of the substrate bias on the RTN char-acteristics of SOI transistors.

2. Methodology and experimental setup

The experimental method is summarized in the schematic ofFig. 1. At first, we characterize low frequency noise (LFN) of thedevice for different gate biases introducing the Spectral Scanningby Gate Bias approach. The output of this first stage, provides theoptimum bias condition where the device is affected by RTN. Oncethe RTN signal is identified, the transient monitoring of the draincurrent, together with the application of the Weighted Time LagPlot method, determine the number of active traps in the device.This selection of the suitable bias condition and the single-trapdevice identification, permit us to obtain the optimum RTN charac-terization of single-trap devices in an unambiguous protocol forthe implementation in automatic testers.

All the experiments presented in this work are based on an adhoc characterization setup consisting of:

� An Agilent B1517A high resolution Source-Measurement-Unit(SMU) monitoring repeatedly the drain current during periodsof 400 s at a 2 ms sampling-rate (the schematic is shown inFig. 2a). The acquisition periods were repeated until a minimumnumber of 100 transitions in the current signal were capturedto guarantee the significance of the statistics.







Fig. 1. Scheme of the experimental method proposed for the single-trap randomtelegraph characterization in transistors. The method permits the optimum RTNcharacterization of single-trap devices combining the Spectral Scanning by GateBias technique and the Time Lag Plot method.

Fig. 2. (a) Schematic of the experimental setup developed for the RTN measure-ments. Each terminal of the transistor is monitored by an Agilent B1517A SMU at arate of 500 samples per second. Automatic measurements around the wafer areimplemented through a Süss semiautomatic probe station. (b) Schematic of themeasurement setup used to extract the spectral noise power of the drain currentbased on a programmable low-noise amplifier.

116 C. Marquez et al. / Solid-State Electronics 128 (2017) 115–120

� A Süss PA-300PS semiautomatic probe station GPIB-controlledby the Agilent SMU. This tool allows the fast location and scan-ning of all the devices over the wafer to extract informationabout the distribution of traps and the variability.

� A low-noise current amplifier connected to a software-basedspectrum analyzer through a high resolution A/D converter(Fig. 2b). The system is used for the noise spectral densitymonitoring.

The devices used to tune the method (as well as for the subse-quent experiments) were high-k metal-gate SOI nMOSFETs, fabri-cated at CEA-LETI in a 22 nm process [5]. The transistors featurean ultrathin body of tSi ¼ 7 nm, Buried-OXide (BOX) thickness oftBOX ¼ 145 nm, gate length of L ¼ 100 nm and gate width ofW ¼ 80 nm. The hafnium-based gate oxide has an equivalent oxidethickness (EOT) of tEOT ¼ 1:3 nm.

3. Determination of the optimum bias condition for the RTNapperance

The time-domain characterization of the electrical noiserequires large time windows due to the extensive quantity ofevents needed to obtain meaningful statistics [6]. In addition,due to the dependence of the capture time (sc: average time atthe high current level) and emission time (se: average time atthe low current level) of a trap with the carrier concentration ofthe channel [7], random telegraph noise is not easily observablein all the bias range of the transistor (see Fig. 3a). Therefore, RTNmust be characterized at a bias point where the characteristictimes, se and sc , of the trap differ at most in three orders of mag-nitude. In this way, the transition events between states can beobserved in a reasonable time frame.

This task can be facilitated by the first method that we are intro-ducing in this work: Spectral Scanning by Gate Bias (SSGB). Initiallythe spectral noise density of the drain current (SI) is obtained for agiven bias (preferentially close to the threshold voltage, Fig. 3b).The corner frequency of the noise spectrum is determined by thesum of the inverse of the characteristic times (f c ¼ 1=se þ 1=sc)[8]. Once the corner frequency is located (f c ¼ 3:75 Hz for the caseof Fig. 3b), the spectral density of the current noise, SI , is measuredwhile VG is swept leading to the SI � VG curve shown in Fig. 3c(SSGB). The bell shaped characteristic of Fig. 3c identifies the biasrange where the RTN will be easily observable (VG 2 [0.4 V,0.55 V] for this particular case). The reader can notice that thisresult is consistent with the drain current signals shown inFig. 3a where the fluctuations are visible in the same voltage rangegiven by the SSGB plot of Fig. 3c.

4. Identifying the number of traps involved in the RTN signals

Once the bias range for the experiments is unequivocally deter-mined, identifying the RTN signals corresponding to a single-trap isone of the most challenging tasks during its electrical characteriza-tion. Examples of the intricate drain current signature of multiple-trap RTN are shown in Fig. 4. The current transients are obtainedfor different transistors for the same value of the gate bias.

Despite from the time domain representation of Fig. 4 is diffi-cult to discern the contribution of a single-trap, this can be carriedout unambiguously by a modified version of the Time Lag Plotmethod (TLP) partially based on the approach described in [9,10].Each point of the TLP space (events) is given by the sample ofthe current at a specific moment, and the immediately next sample(ðIDðiÞ; IDðiþ 1ÞÞ). Then, the TLP space event is weighted by theappearance function, AðIDðiÞ; IDðiþ 1ÞÞ, which accounts for thenumber of events inside a certain circle of the TLP space anddefined by:

AðIDðiÞ; IDðiþ 1ÞÞ ¼X

N�1

j¼1

nðIDðjÞ; IDðjþ 1ÞÞ ð1Þ

where n is a function that eliminates the samples outside theappearance radius,

1 For interpretation of color in Fig. 6, the reader is referred to the web version ofthis article.

Fig. 3. (a) Drain current traces as a function of the time from a transistor affected by random telegraph noise for different gate voltages. (b) Normalized current noise power(SI=I

2) dependence with frequency for different gate voltages (VG). (c) Normalized current noise spectral density dependence with gate voltage (SSGB) for the transistor offigure (b).

Fig. 4. Drain current traces of different devices presenting multi-trap RTN.

C. Marquez et al. / Solid-State Electronics 128 (2017) 115–120 117

nðIDðjÞ; IDðjþ 1ÞÞ ¼ 1 if df½IDðjÞ; IDðjþ 1Þ�; ½IDðiÞ; IDðiþ 1Þ�g 6 r

0 if df½IDðjÞ; IDðjþ 1Þ�; ½IDðiÞ; IDðiþ 1Þ�g > r

�

ð2ÞN is the total number of samples inside the time frame ana-

lyzed; df:; :g, is the Euclidean distance function; and r is theappearance radius, r ¼ 10�6r ðAÞ (with r the standard deviationof the samples within the time frame).

This sample-weighted approach of the conventional TLPmethod allows to identify the RTN levels clearly as populatedregions in the diagonal of the TLP space, while populated regionsoutside the diagonal are related to the transitions between states.We show results of the application of the method in Fig. 5. Whenthe device is not affected by traps (Fig. 5a), a single cloud appearsin the TLP space; the appearance of a constellation with two lobesindicates the presence of a single-trap (Fig. 5b); a three-lobes con-stellation, reveals the existence of three predominant currentlevels (two traps, Fig. 5c); and when multiple current levels appear,a spread lobe indicates a multi-trap situation (Fig. 5d).

The strength of the method is fully exploited when it is com-bined with an automatic probe-station. The distribution of trapsover the transistors of the wafer can be determined by the auto-

matic monitoring of the drain current of specific transistors andthe simultaneous application of the w-TLP method described pre-viously. Fig. 6 shows the map of traps for a 100 nm-length and80 nm-width transistor fabricated in each die of the wafer (336transistors in total) when the bias point is close to the thresholdvoltage (VD ¼ 0:1 V; VG ¼ 0:5 V). The map represents the numberof traps detected in each transistor: failed transistors, for whichthe automatic contact was missed or simply because they werefaulty (black); transistors with only one drain current level, i.e.transistor without trap (green1); transistors with two current levels,i.e. single-trap devices (blue); transistors with three current levels,i.e. two-traps devices (red); and transistors with more than twoactive traps (pink). Examples of the current level for each type oftransistor are shown in the annexed time domain representationsof Fig. 6.

Fig. 7 presents the histogram summarizing the trap count overthe wafer. From this result, and for the specific transistor studied(one L ¼ 80 nm; W ¼ 100 nm transistor per die), we can concludethat one out of three of the transistors are affected by one trap,and virtually the same number of transistors are not affected bytraps leading to RTN. The case of devices with three current levels,i.e. two traps, represents the 7.5% of the devices characterized onthe wafer. Finally, the case of multi-trap devices (transistors withmore of three current levels), involves 12.5% of the devices.

The previous result demonstrates the large presence of single-trap devices within this wafer run. This information constitutesan useful feedback for process engineers in the path of the opti-mization of the technology.

5. Application to substrate bias influence on the RTN

Finally, the whole methodology is applied to study the effect ofthe substrate bias on the RTN characteristics of SOI transistors:SSGB, for RTN detection, and w-TLP, for the location of single-trap devices. Fig. 8 shows typical sc/se ratios used to extract thephysical parameters of the traps [11] for two different sampleswhen a substrate bias is applied to the SOI wafer; the range of

Fig. 5. Traps constellations in the weighted TLP space of drain current signals: (a) cloud: transistor lacking of RTN signature (only thermal noise is reflected). (b) Transistorwith two lobes (states) in the TLP constellation result of the single active trap. (c) Transistor with a three-lobes constellation identifying the characteristic signature of twotraps. (d) Spread cloud corresponding with a transistor with multi-trap events.

Fig. 6. Distribution of the number of current levels detected in the transistors over the wafer at VD ¼ 0:1 V and VG ¼ 0:5 V. (Left) Examples of transistors with two and threecurrent levels (top and down respectively). (Right) Examples of multi-current level (>3) and RTN-free transistors (top and down respectively).


the front gate overdrive voltage is selected with the SSGB proce-dure, previously described in Section 3. As observed, althoughthe curves are presented as a function of the overdrive voltage(note that VT will be modified by VSUB when the back interface isin depletion) [12], the sc/se ratio depends on the particular valueof VSUB (even though the inversion charge is the same in all cases).Note also that this dependence on VSUB, for a given inversioncharge, is different for the particular trap considered (Fig. 8a vs. b).

Fig. 9 shows the values of sc and se as a function of the overdrivevoltage for the previous devices. From the analysis of this plot wecan appreciate that for a given overdrive voltage, the capture time(sc) decreases whereas the emission time (se) increases as VSUB

increases. From Fig. 9 one may also notice that this behavior isobserved both for attractive (linear dependence of sc and se withthe gate bias, Fig. 9a) or neutral traps (linear dependence of scand constant value se with the gate bias, Fig. 9b) [13]. This effect

Fig. 7. Histogram of the number of dice presenting a determined number of traps inthe device under study detected from the RTN characterization(L ¼ 100 nm; W ¼ 80 nm, one transistor per die). Same bias than in Fig. 6.

Fig. 8. sc/se ratios as a function of the gate overdrive bias for different negative andpositive substrate biases. Results from two different devices (a) and (b) and thesame physical dimensions.

Fig. 9. sc and se ratios as a function of the gate overdrive voltage for differentsubstrates biases in the same devices than in Fig. 8.

C. Marquez et al. / Solid-State Electronics 128 (2017) 115–120 119

is contrary from what we may expect considering classical RTNmodels relying on the inversion charge and the decrease of theelectric field in the Si-film while increasing the substrate bias[12]. In contrast, these results are compatible with the fact thatthe carrier is emitted to the metal gate contact since, for this mech-anism, the lower the gate-oxide electric field intensity, the largerthe probability of the trap to be filled [14].

6. Conclusion

We have introduced an exhaustive method to identify, experi-mentally, single-trap Random Telegraph Noise by combining thenoise Spectral Scanning by Gate Bias technique (SSGB) with a mod-ifiedWeighted Time Lag Plot method (w-TLP). The characterizationprotocol has been implemented in an automatic probe-station andapplied for the massive test of the devices all over a wafer provid-ing information about the distribution of traps. Finally, the proce-dure has been implemented for the study of the impact of thesubstrate bias on the RTN characteristics of ultrathin SOI transis-tors. The results show a non-intuitive trend leading to an increaseof the emission time (decrease of capture time) when the electric

field in the film is relaxed by increasing the substrate bias, for agiven inversion charge. However, this behavior could be explainedby the carrier emission to the gate metal contact.

Acknowledgment

The authors would like to thank Dr. O. Faynot and Dr. F. Andrieufrom CEA-LETI for sample supplying. This work has been partiallyfunded by Spanish Government through project TEC-2014-59730,regional government through P12-TIC-1996, the BBVA-Spain Foun-dation for the ‘‘Ayudas para Investigadores y Creadores Culturales”program and the European Union under project WAYTOGO FAST.

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RF SOI CMOS technology on 1st and 2nd generation trap-rich highresistivity SOI wafers


⇑ Corresponding author.E-mail address: [email protected] (B. Kazemi Esfeh).

B. Kazemi Esfeh a,⇑, S. Makovejev b, Didier Basso c, Eric Desbonnets c, V. Kilchytska a, D. Flandre a, J.-P. Raskin a

a ICTEAM, Université catholique de Louvain, 1348 Louvain-la-Neuve, Belgiumb Incize, Louvain-la-Neuve, Belgiumc Soitec, Parc Technologique des Fontaines, 38190 Bernin, France




Keywords:High-resistivity (HR) SOI substrateTrap-rich high-resistivity siliconEnhanced signal integrity silicon-on-insulator (eSI HR-SOI)Substrate effective resistivitySilicon-on-insulatorDC and RF performancePartially-depleted (PD) SOI MOSFETsCrosstalkDigital substrate noise

In this work three different types of UNIBONDTM Silicon-on-Insulator (SOI) wafers including one standardHR-SOI and two types of trap-rich high resistivity HR-SOI substrates named enhanced signal integrityhigh resistivity silicon-on-insulator (eSI HR-SOI) provided by SOITEC are studied and compared. TheDC and RF performances of these wafers are compared by means of passive and active devices such ascoplanar waveguide (CPW) lines, crosstalk- and noise injection-structures as well as partially-depleted(PD) SOI MOSFETs. It is demonstrated that by employing enhanced signal integrity high resistivitysilicon-on-insulator (eSI HR-SOI) compared to HR-SOI wafer, a reduction of 24 dB is measured on bothgenerations of trap-rich HR-SOI for 2nd harmonics. Furthermore, it is shown that in eSI HR-SOI, digitalsubstrate noise is effectively reduced compared with HR-SOI. Purely capacitive behavior of eSI HR-SOIis demonstrated by crosstalk structure. Reduction of self-heating effect in the trap-rich HR-SOI with thin-ner BOX is finally studied.


1. Introduction

During last decades, CMOS technology scaling-down hasenabled millimeter wavelength operation and low-cost integrationof digital, analog and RF systems on the same wafer for system-on-chip or system-in-package applications [1–3]. In this context, themost special advantage of SOI CMOS compared to bulk Si is theavailability of high-resistivity silicon (HR-Si) substrate to achievelow crosstalk between passive and active devices and high-quality passive elements thanks to effective reduction of substratecoupling and losses in RF circuits [4,5]. However, HR-SOI substratesuffers from resistivity degradation due to the formation of para-sitic surface conduction (PSC) beneath the buried oxide layer(BOX) [6–9] due to fixed oxide charges (Qox) within the oxide.One of the most efficient techniques to overcome this problem isto introduce a trap-rich layer at the Si/SiO2 interface compatiblewith industrial SOI wafer production and thermal budget of stan-dard CMOS process [8]. Such layer aims at capturing the free carri-ers forming the PSC and thus retaining the substrate nominal high

resistivity. In this work two types of trap-rich HR-SOI wafersnamed 1st and 2nd generation of enhanced signal integrity (eSIHR-SOI) substrate having respectively a BOX thickness of 400 nmand 200 nm developed by Soitec are studied and compared withthe classical HR-SOI substrate with a BOX thickness of 1 lm. Oneof the motivations of using trap-rich HR-SOI substrates with thin-ner BOX is the reduction of self-heating effect. Moreover, it createsa pathway for further ultimate BOX thinning used in advancednano-scaled ultra-thin body and BOX (UTBB) fully depleted MOS-FETs which allows threshold voltage control by means of back-gate biasing voltage Vbg [10]. Therefore, trap-rich HR-SOI withthinner BOX could be considered as a promising candidate.

2. Device description

In this work two types of trap-rich HR-SOI substrates denotedeSI Gen1 and eSI Gen2 as 1st and 2nd generations with 400 nmand 200 nm-thick BOX respectively and one standard HR-SOI with1 lm BOX (all provided by Soitec) are characterized and comparedfor non-linearity effects, crosstalk, noise coupling, DC/RF figures ofmerit and self-heating. The test structure devices include







Fig. 2. Normalized Id-Vg (linear and logarithmic) and gm-Vg characteristics in linear

122 B. Kazemi Esfeh et al. / Solid-State Electronics 128 (2017) 121–128

0.52 lm-thick CPW lines and PD SOI nMOSFETs fabricated usingTowerJazz 0.18 lm SOI CMOS process (Fig. 1).

The lateral dimensions of the CPW lines are 20, 18 and 100 lmfor the central conductor, slot space and ground plane, respec-tively. The PD SOI nMOSFETs have 145 nm-thick active silicon filmwith a nominal operating voltage of 2.5 V. The studied RF body-tiedMOSFET has a gate length (Lg) of 0.24 lm with 16 gate fingers of2 lm each (Wf). The studied single-finger DC nMOSFET has a gatelength (Lg) of 0.26 lm with 1.5 lm width (Wf). To investigate sub-strate coupling we used a passive crosstalk structure consisting oftwo identical metallic pads embedded into RF pads for probe mea-surement. Active crosstalk structure is used to study the propaga-tion of a digital noise signal through the substrate [11]. Thischaracterization is performed by measuring the frequency spectraat the nMOSFETs drain as the output port when a square noise sig-nal is injected in the vicinity of the nMOSFET via a metallic RF padwith a certain distance from the transistor.

regime (VDS = 50 mV) of DC transistor for 3 different wafers of 1st generation oftrap-rich high resistivity SOI (eSI Gen1), 2nd generation of trap-rich high resistivitySOI (eSI Gen2) and high resistivity SOI (HR).

Fig. 3. gm/Id ratio versus Id/(W/L) DC transistor in linear regime (VDS = 50 mV) on 3different wafers of 1st generation of trap-rich high resistivity SOI (eSI Gen1), 2ndgeneration of trap-rich high resistivity SOI (eSI Gen2) and high resistivity SOI (HR).

3. Transistor characteristics

3.1. DC and RF performance

The DC on-wafer measurements have been done using an Agi-lent B1500. As shown in Fig. 2, the drain current versus gate volt-age (ID-VG) and transconductance vs gate voltage (gm-VG) curves inlinear regime are almost identical for the DC transistor on the 3 dif-ferent wafers. To eliminate the threshold voltage variations effectand fairly compare these results, gm/ID ratio versus ID/(W/L) curvesfor the same transistors are plotted in Fig. 3.

Fig. 3 shows that similar values of maximum gm/ID � 31 V�1 areobtained for all substrate types, as well as similar characteristics instrong inversion, with very slight deviations in weak inversionwhich could be related to CMOS process and measurements vari-ability. From Figs. 2 and 3 it can be seen that neither the existenceof trap-rich layer nor the BOX thickness affects the DC characteris-tics of the PD SOI MOSFETs.

High-frequency measurement of studied RF body-tied nMOS-FET is performed to extract the current gain cutoff frequency (fT)as one of the major RF figures of merit. fT is known as unity currentgain frequency at which the short circuit current gain (H21)becomes unity (0 dB) [12–14]. RF measurements are done in thefrequency range from 40 MHz up to 40 GHz using Anristu37369A in combination with HP4145 semiconductor-parameteranalyzer. By using the off-wafer line-reflect-match (LRM) calibra-

Fig. 1. Cross-section details of 4-metal layer 0.18 lm SOI CMOS process by TowerJazz on top of high resistivity SOI substrates having different BOX thickness (TBOX)provided by SOITEC.

tion technique, the reference planes at the probe tips are deter-mined. Then by means of on-wafer dedicated de-embeddingstructures, the unwanted parasitic effects introduced by the RFpads are removed. H21 is extracted from the measured S-parameters of the transistor in saturation regime at Vg bias corre-sponding to the maximum of gm [15,16]. As shown in Fig. 4, cut-offfrequencies fT on all 3 wafers are almost the same.

According to the MOSFET small-signal equivalent circuit fT canbe in a first order expressed as [13,14,16]

f T � gm

2pCggð1Þ

where Cgg is the total gate capacitance (i.e. Cgs + Cgd). From Eq. (1),Fig. 4 and the results of DC measurements, it can be also concludedthat total gate capacitances of PD MOSFETs fabricated on three dif-ferent wafers are identical.

3.2. Self-heating and coupling through the substrate

Self-heating in SOI devices becomes a critical issue because ofdevice downscaling and use of materials with low thermal conduc-tivity like SiO2 [17]. Thermal conductivity of SiO2 (1.4 W�m�1�K�1)

Fig. 4. Current gain cutoff frequency fT at VDS = 1.2 V and VGS at which gm(transconductance) is maximum for body-tied RF transistor for 3 different wafers of1st generation of trap-rich high resistivity SOI (eSI Gen1), 2nd generation of trap-rich high resistivity SOI (eSI Gen2) and high resistivity SOI (HR).

Fig. 5. Output conductance (gds) variation with frequency at Vgs = Vds = 1.4 V.

Fig. 6. Average temperature rise (DT), thermal resistance (Rth) and outputconductance transition amplitude due to self-heating (Dgds) in studied body-tiedRF transistors biased at VGS = VDS = 1.4 V for 3 different wafers of 1st generation oftrap-rich high resistivity SOI (eSI Gen1), 2nd generation of trap-rich high resistivitySOI (eSI Gen2) and high resistivity SOI (HR).

B. Kazemi Esfeh et al. / Solid-State Electronics 128 (2017) 121–128 123

is two orders of magnitude lower than that of Si (148W�m�1�K�1)[18]. Consequently, the thicker the buried oxide layer (BOX) thehigher the thermal resistance (Rth) of the device. In [19] it is shownthat the thermal resistance is proportional to the square root of theBOX thickness. Therefore, BOX thinning is seen as a good solutionfor thermal properties improvement. Moreover, thin BOX enablesother useful features in some advanced technology such as ultra-thin body ultra-thin BOX (UTBB) devices, notably threshold voltagecontrol from the backgate [20–22] and better control of short chan-nel effects [23].

In this section, the self-heating effect of studied RF body-tied PDnMOSFET is investigated by applying the RF technique [24]. In thistechnique, S-parameters are measured over a frequency rangefrom 40 kHz up to 3 GHz at room temperature (25 �C), de-embedded using dedicated open structures and converted to Y-parameters. The output conductance gds is obtained from the realpart of the Y22 parameter. In order to extract device thermal impe-dance from gds variation with frequency, hot chuck DC measure-ments are required. The output characteristics (Id/Vds) fordifferent gate voltages (Vgs) at different temperatures were mea-sured. The thermal resistance Rth is proportional to the gds transi-tion amplitude and inversely proportional to the drain currenttemperature dependence [19,24]:

Rth ¼ Dgds

ðVdsgdT þ IdÞ@Id=@TAð2Þ

where Dgds is the gds difference at low and high frequency(�50 MHz) and gdT is gds at high frequency. oId/oTA is the depen-dence of drain current Id on the ambient/chuck temperature TAand can be extracted from Id/Vgs or Id/Vds measurements at differenttemperatures. The average temperature rise DT is obtained from

DT ¼ RthIdVds ð3ÞThe studied devices are body-tied to prevent the floating-body

or kink effect as a common feature in PD SOI devices causing thehistory effect [25]. Moreover, body-tied devices do not feature fre-quency variation of output conductance related to the floating-body and thus allow for more straightforward interpretation ofoutput conductance frequency response in terms of self-heatingand substrate effect and corresponding parameters extraction.

Fig. 5 shows gds variation with frequency when the transistor isbiased in saturation regime (Vgs = Vds = 1.4 V). DC output conduc-tance values extracted from the IdVd measurements are alsopointed. As discussed in [26–31], transitions in gds versus fre-

quency curve are caused by various effects. The gds transition intens of kHz to hundreds of MHz range is generally considered tobe caused by self-heating [19,24,26–28]. As the frequencyincreases, device temperature stops following electrical oscilla-tions and isothermal condition is reached [26]. As can be seen inFig. 5, transistors on different substrates exhibit similar gds valuesat �50 MHz where dynamic self-heating is removed, whereas atDC and low frequencies, HR substrate shows the lowest outputconductance. This lowest output conductance in HR substrate casecan be misleadingly interpreted as the better performance ofdevices on HR substrates. However, just contrarily, lower DC gdsvalues obtained for the devices on HR substrate is a result of stron-ger self-heating caused by thicker BOX employed and thus worseperformance can be expected.

Values of Rth, the average temperature rise DT in the device andthe magnitude of gds transitions are plotted in Fig. 6. Rth and DTvalues are in line with previously measured values for other PDSOI devices [19,24]. As expected, Rth and DT are larger in deviceswith thicker BOX. In Fig. 5, the transition manifested in the GHzrange (fsub) is related to the substrate effect, which appears as aresult of source and drain coupling through the substrate underthe BOX [28]. As discussed in more details in [28,29,31], this


transition at high frequency can in a first order be modeled by theSi substrate resistance RSi and its capacitance CSi, when it can beconsidered as dielectric.

f sub �1

ðRSi � CSiÞ ð4Þ

It can be seen that the substrate-related transition (GHz range)shifts progressively to lower frequencies when HR substrate isreplaced by eSI Gen1 and then by the eSI Gen2. This trend corre-lates with higher resistivity of eSI Gen1 and Gen2 discussed in nextsection (see Fig. 7). Indeed, characteristic frequency of this sub-strate transition was previously shown to be inversely proportionalto the Si substrate resistance and capacitance [5,28,29,31] (see Eq.(4)). Furthermore, one can see that amplitude of substrate transi-tion slightly increases in the case of eSI substrates Gen1 andGen2. This is due to a stronger effect of parasitic source and draincoupling via the substrate in eSI Gen2/Gen1 devices due to thethinner BOX.

4. Substrate effective resistivity and harmonic distortion

The effective resistivity (qeff) and total loss (a) on the 3 differenttypes of substrate have been extracted by means of a 2100 lm-long CPW line S-parameters measurements [32]. On-wafer small-and large-signal measurements on CPW line are done based on a

Fig. 7. (a) Effective resistivity. (b) Total Loss (Conductor and substrate) of 3different substrates of 1st generation of trap-rich high resistivity SOI (eSI Gen1),2nd generation of trap-rich high resistivity SOI (eSI Gen2) and high resistivity SOI(HR).

Fig. 8. (a) 2nd and (b) 3rd harmonic distortion measured at zero bias by CPW lineson 3 different wafers: 1st generation of trap-rich high resistivity SOI (eSI Gen1), 2ndgeneration of trap-rich high resistivity SOI (eSI Gen2) and high resistivity SOI (HR).

special setup [9] using an Agilent 4-port PNA-X vector networkanalyzer in the frequency range of 10 MHz up to 26.5 GHz. Fig. 7shows that as stated before, due to the formation of PSC, the stan-dard HR SOI substrate loses its nominal high resistivity and showsan effective resistivity of only 200X�cm, whereas in 1st and 2ndgenerations of trap-rich eSI HR-SOI the substrate has kept its highresistivity of more than 2 kX�cm and 3 kX�cm, respectively, up to5 GHz after CMOS processing. Another point that can be seen inthis figure is that despite its thinner BOX, the eSI Gen2 HR-SOI sub-strate still shows a slightly higher qeff and lower a compared to eSIGen1 HR-SOI which could be explained by the higher nominal sub-strate resistivity in 2nd generation.

Fig. 8 illustrates the 2nd and 3rd harmonics distortion at theoutput of the CPW line on different wafers fed by a 900 MHz inputRF signal for a power level ramp of �25 dBm up to 25 dBm andzero bias applied on the substrate. Compared to HR-SOI wafer, areduction of 24 and 35 dB is measured on both generations oftrap-rich eSI HR-SOI for 2nd and 3rd harmonics, respectively. FromFigs. 8 and 7 it can be clearly seen that the level of the harmonics isinversely proportional to the substrate resistivity. This non-linearbehavior can be explained by the PSC layer which changes the dis-tribution of free carriers inside the substrate generating a modu-lated charge density at the Si/SiO2 interface [33]. Consequently,the wafer becomes highly bias voltage dependent [34].

Fig. 10. Crosstalk structure in 0.18 lm TowerJazz CMOS process: (a) schematic; (b)top layout view.

S = 50 µm

20 dB/dec

Fig. 11. Measured crosstalk versus frequency on HR-SOI, eSI Gen1 and eSI Gen2 HR-SOI substrates for a crosstalk structure with a pad distance of S = 50 lm and zerosubstrate bias.


Fig. 9 demonstrates RF performance insensitivity of trap-richeSI HR-SOI substrates to the applied bias voltages on CPW lines.It can be seen that under different bias conditions, the maximumvariation of 2nd and 3rd harmonics distortion in HR-SOI wafer ismuch higher compared to trap-rich substrates.

5. Crosstalk analysis

For the RF system-on-chip (SoC) applications, less couplingthrough the substrate between devices fabricated on the same sub-strate, and therefore a good isolation between them, is desired [6].In mixed-mode high-frequency integrated circuit in which RF ana-log circuits are integrated with baseband digital circuitry, thecrosstalk coupling through the substrate is an important limitingfactor especially for the analog part of the chip which is very sen-sitive to voltage variations on the power supply and substrateground rails [5]. The strength of the coupling between differentdevices depends on device type (active or passive) and the charac-teristics of the substrate like effective resistivity, effective permit-tivity, BOX thickness, etc. [35]. Various methods are proposed inliterature for reducing the coupling mechanisms between digitaland analog parts through the common substrate like metal Faradaycages, guard ring, etc. [5,36–38]. In this work we use enhanced sig-nal integrity high resistivity silicon on insulator substrates for thispurpose. Indeed, a trap-rich layer at the SiO2/Si-substrate willreduce the coupling between devices through the substrate andhence makes better isolation between them [6].

In this section the substrate crosstalk performances of differentSilicon-On-Insulator (SOI) technologies including standard HR andtwo generations of trap-rich high resistivity eSI Gen1 and eSI Gen2are comparatively investigated and compared. By this comparisonthe influence of substrate effective resistivity and buried oxidethickness (BOX) are analyzed. The study of crosstalk is demon-strated by two types of test structures: passive crosstalk structuresand noise to active devices. The test structures have been designedand fabricated using TowerJazz 0.18 lm SOI CMOS process as sta-ted in Section 2 on 3 different SOI wafers provided by Soitec.

The test structure is composed by two rectangles of metal 1 asthe closest metal to the substrate with a length of 150 lm (L) and awidth of 50 lm (W) representing the noise injector and the sensi-tive node as shown in Fig. 10. The two ports are separated by a dis-tance S of 50 lm considered as the nominal structure for which the

Fig. 9. The variation of 2nd harmonic distortion (HD2) and 3rd harmonic distortion(HD3) with bias changing from �60 V to +60 V at input power Pin = 20 dBm for 3different wafers: 1st generation of trap-rich high resistivity SOI (eSI Gen1), 2ndgeneration of trap-rich high resistivity SOI (eSI Gen2) and high resistivity SOI (HR).

measurements and comparison between the 3 different substratesare shown.

By means of S-parameters measurements (S21) of crosstalkstructure shown in Fig. 10(b) with S = 50 lm in the frequencyrange of 1 kHz up to 3 GHz, the crosstalk level of different wafersis assessed and plotted in Fig. 11. As can be seen, a pure capacitivecoupling is observed for both eSI Gen1 and Gen2 with a typical 20-dB/decade slope over the frequency range of 150 MHz-to-3 GHz.This behavior highlights the lossless property of the eSI HR-SOIsubstrates. Also a reduction of 15 dB of crosstalk is observed at200 MHz for trap-rich HR-SOI wafers compared with conventionalHR-SOI counterpart. From Fig. 11 it can be clearly seen that HR-SOIsubstrate suffers from higher crosstalk level (slope >20 dB/dec) dueto the parasitic surface conduction (PSC) effect which is suppressedin eSI HR-SOI wafers [8,22,39,40].

The large-signal characterization of the crosstalk structure isillustrated in Fig. 12. It shows the 2nd (HD2) and 3rd (HD3) har-monics of 3 different wafers. The 2nd and 3rd harmonics are mea-sured at the output of a crosstalk structure with a pad distance ofS = 50 lm fed by an input RF signal at 900 MHz and for a powerlevel ramp from �25 dBm up to 25 dBm. Fig. 12 illustrates thatharmonics level of signals coupled through the substrate isreduced by 30 dB when HR-SOI substrate is replaced by an innova-tive trap-rich HR-SOI (eSI HR-SOI) one. This low harmonics level of�100 dB is comparable with insulating substrates like quartz[41,42].

S = 50 µm

30 dB30 dB

Fig. 12. Measured 2nd (HD2) and 3rd (HD3) harmonic distortions of a crosstalkstructure with a pad distance of S = 50 lm and zero DC substrate bias.

(a)

(b)

(10 MHz, -67.41 dBm)

(10 MHz, -86.66 dBm)


Next to that, we study the harmful effect of the digital switchingnoise emulated by a clock signal, on the performance of an nMOS-FET representing the analog/RF part in an RF SoC application [11].To simulate such an environment, the test structure shown inFig. 13 is implemented.

The test structure consists of a PD SOI nMOSFET located at afixed distance of 350 lm from an RF metal pad used for injectinga digital noise signal to the structure. The PD SOI nMOSFET has agate length, gate finger width and number of the finger of0.24 lm, 2 lm and 64, respectively. It is biased in saturation(VGS = 1.2 V and VDS = 1.2 V). A fundamental input signal at900 MHz is applied at the gate. A 5 V peak-to-peak digital noisesource with selected frequencies of 50 kHz, 100 kHz, and500 kHz, 1 MHz, 10 MHz, 50 MHz and 80 MHz is connected tothe RF noise pad. Fig. 14 shows the coupled noise spectra at theMOSFET drain port for the three different substrates for the10 MHz clock frequency when gate RF input signal is off. InHR-SOI substrate despite a thicker BOX of 1 lm compared to eSIHR-SOI wafers, the output peak noise level is 19.25 dB and

Fig. 13. Cross-section of PD SOI nMOSFET with a noise pad at a distance of 350 lm(center to center) lying on either eSI HR-SOI or HR-SOI wafers when a trap-richlayer exits or not respectively.

(c)

(10 MHz, -76.76 dBm)

Fig. 14. Frequency spectrum of measured noise signal at the drain port of the PDnMOSFET having a gate length (Lg), gate finger width (Wf) and number of the finger(Nf) of 0.24 lm, 2 lm and 64 respectively biased in saturation with no fundamentalRF signal at the gate. A digital noise signal (5 V peak-to-peaks at 10 MHz) is injectedto the RF noise pad on (a) HR-SOI, (b) eSI Gen1 HR-SOI and (c) eSI Gen2 HR_SOIsubstrates.

9.35 dB higher than eSI Gen1 and eSI Gen2, respectively. This isdue to the presence of highly parasitic conductive surface layer(PSC) at the BOX/HR-SOI interface by which a strong couplingand propagation of the noise signal is observed at the output.However, comparing Fig. 14(b) and (c), eSI Gen1 shows a noisecoupling reduction of 10 dB compared to eSI Gen2 because of

∆ (Pfc-Pfc+fnoise) = 74.83 dB

∆ (Pfc-Pfc+fnoise) = 102.5 dB

∆ (Pfc-Pfc+fnoise) = 99 dB

(a)

(b)

(c)

Fig. 15. Output spectrum of measured fundamental and noise signal at the drainport of the PD nMOSFET having a gate length (Lg), gate finger width (Wf) andnumber of the finger (Nf) of 0.24 lm, 2 lm and 64 respectively biased in saturationwith a 900 MHz fundamental RF signal at the gate. A digital noise signal (5 V peak-to-peaks at 10 MHz) is injected to the RF noise pad on (a) HR-SOI, (b) eSI Gen1 HR-SOI and (c) eSI Gen2 HR_SOI substrates.

Fig. 16. Power level difference between 900 MHz fundamental RF input (AFund) anddigital noise signal (ANoise) on HR-SOI and eSI Gen1 substrates.


having a thicker BOX. Therefore, the 1st generation of trap-rich HR-SOI (eSI Gen1) shows a very good performance thanks to a goodtrade-off between substrate resistivity, from one side and a rela-tively ‘‘thick” BOX from another side.

When a fundamental RF signal with amplitude of AFund at thefrequency of fc is applied to the gate of the transistor, the digital

noise signal (ANoise, fnoise) induces a mixing product and generates2 N harmonics at fc � fnoise and fc + fnoise. In this work, as illustratedin Fig. 15, the fundamental 900 MHz input signal and the squaredigital noise signal of 5 V peak-to-peak at fnoise = 10 MHz result intwo harmonics at 890 MHz and 910 MHz. Fig. 15 evaluates thesubstrate performance through the parameter D defined as thepower difference between the fundamental output signal and theharmonic (Pfc � Pfc+fnoise). The higher the D the better isolation willbe achieved.

Fig. 15 shows an increase of D by 27.6 dB for eSI Gen1 and24.2 dB on eSI Gen2 wafers compared with their HR-SOI substratecounterpart. Fig. 15 evidences that trap-rich eSI HR-SOI substratesfilter well the digital noise signal from the output spectrum andshow smoother response thanks to eliminating the effect of PSCat the BOX/HR-SOI interface, even though they have thinner BOXthan HR-SOI. From Fig. 15(b) and (c), it can be clearly seen that1st generation of trap-rich HR-SOI (eSI Gen1) shows a bettertrade-off between substrate resistivity and BOX thickness sincemost of the noise signals are suppressed. Fig. 16 demonstratesD = Afund � Anoise measured at the drain pad of the transistor asthe output when the injected digital noise signal changes from50 kHz up to 80 MHz on HR-SOI and eSI-Gen1 (as the best sub-strate in our comparison).

A dc bias voltage of either 0 V or �10 V is also applied to thenoise signal pad. By applying a negative dc bias voltage, the nega-tive charges in PSC layer are repelled and a deep depletion will beformed. Therefore, it is expected that under these conditions, thecoupled noise decreases and D increases. In Fig. 16 it can indeedbe seen that application of negative dc bias voltage (�10 V) causesD increase by 11 dB at 10 MHz comparing to its level at 0 V bias inthe case of HR-SOI substrate, whereas in the case of eSI Gen 1 itstays unchanged thanks to the traps that have frozen the free car-riers in PSC. Moreover, from Fig. 16, one can see that in the lowerfrequency range below 1 MHz, since the carriers have enough timeto relax, both HR-SOI and eSI HR-SOI substrates show similarbehavior. In the frequency range higher than 1 MHz the effect ofthe traps is evident leading to almost constant high (w.r.t. HR-SOI) levels of D.

6. Conclusion

Use of a trap-rich layer underneath the BOX in HR SOI wafersallows the substrate to recover its high-resistivity properties andthus results in higher effective resistivity, lower losses, lower


crosstalk, lower harmonics level and hence higher linearity, allconserved after CMOS processing. It was shown that the presenceof a trap-rich layer does not change the DC and RF characteristics ofthe MOSFET transistors. Moreover, with enhanced 2nd generationtrap-rich eSI HR SOI substrate featuring thinner BOX of 200 nm,improved thermal properties can be achieved. Therefore, this tech-nology is considered as a good candidate for SoC applications.

Acknowledgments

The authors acknowledge SOITEC for providing the wafers andTowerJazz for the fabrication of CPW lines and PD SOI CMOSdevices.

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Numerical investigation of plasma effects in silicon MOSFETs forTHz-wave detectionq


q This article is an extended version of a paper presented at EUROSOI-ULIS 2016[1].⇑ Corresponding author.

E-mail address: [email protected] (C. Jungemann).

C. Jungemann a,⇑, T. Linn a, K. Bittner b, H.-G. Brachtendorf b

a Institute of Electromagnetic Theory, RWTH Aachen University, 52056 Aachen, Germanyb Embedded Systems Research Group, University of Applied Sciences of Upper Austria, Austria




Keywords:Drift-diffusion modelResistive mixerPlasma wavesTHz detectors

a b s t r a c t

Conventional silicon MOSFETs are used for THz detectors in order to facilitate fabrication of cost-efficientcircuits with high integration density. Resistive mixers based on NMOSFETs are investigated by drift-diffusion simulations, which include the time derivative of the current densities usually neglected inTCAD codes. Different time-integration schemes are investigated for transient simulations and the mod-ified backward differentiation formula is found to be the most CPU-efficient method for the periodicsteady-state. By comparison with the Boltzmann transport equation it is shown that the drift-diffusionmodel can capture the salient aspects of transport in the THz range. The features of the device simulatorare demonstrated by investigation of the current and voltage responsivity together with the noise-equivalent-power for a resistive mixer based on a quarter-micron NMOSFET.


1. Introduction

Electromagnetic waves with a frequency in the range from 0.1to 10 THz are referred to as THz waves [2]. Their strong absorptionin air due to water vapor limits them to near-range applications.They are used in many fields (e.g. security, spectroscopy, medicine,biology, chemistry, communications, etc. [3]), but they are difficultto generate, because their frequencies are too high for efficientoperation of solid-state devices and too low for optical generators(e.g. quantum cascade lasers) [4]. This is called the THz gap. Inorder to keep the price of the sources down, generators fabricatedin standard semiconductor technologies are preferred. A goodexample is the versatile source with a single SiGe BiCMOS chip,which produces an output power of 1 mW at 0.525 THz [5]. TheSiGe HBTs are operated below their maximum frequency of oscil-lation at 175 GHz and the periodic signal of the Colpitts oscillatoris designed to be square-wave like, where the third harmonic at525 GHz is extracted. Since this frequency is beyond their maxi-mum frequency of oscillation, the HBTs show no power gain andthe power efficiency is low. This has led to the proposal of a newkind of solid-state devices based on plasma waves in quasi-2Delectron gases, where the THz signal is generated directly within

the device [6,7]. In analogy to an organ pipe the constant flow ofelectrons in these devices results in oscillations of the electrondensity and plasma waves are excited [6]. Yet no devices basedon this effect have been demonstrated that work efficiently atroom temperature. The best performance is obtained with III-VRF devices [2], albeit at very high cost. The above mentionedsilicon-based RF devices are currently the best option for massmarket applications. The same holds true for detectors. Cost-efficient detectors for THz waves, which can be integrated in a sil-icon technology, have been developed (e.g. [8]). Recently, a fullyintegrated 1 k-pixel CMOS camera for THz waves was demon-strated [9], where the detector is based on a resistive mixer, whichcontains silicon MOSFETs. In this work we restrict our investigationto silicon MOSFETs used in detector circuits for THz signals.

Typically, device operation is analyzed based on a 1D approach,where the Euler equation in various forms is solved in the small-signal regime together with the continuity equation under thegradual channel approximation leading to formulas similar to theTelegrapher’s equations [7,10]. The Telegrapher’s equations aresolved under the assumption of piecewise homogeneity in thelateral direction and for every homogeneous part of the device a2-port description similar to a transmission line is obtained. These2-ports are then connected in series and a model for the totaldevice results. These transmission line models fail to captureimportant effects due to the at least 2D nature of the devices. Forexample, important parasitic effects at the interfaces betweenthe homogeneous device parts are neglected. Another drawback







Fig. 1. 2D tensor-product grid. The box volume is shown in grey. The scalar

130 C. Jungemann et al. / Solid-State Electronics 128 (2017) 129–134

of this approach is that it fails to account for the inhomogeneity ofthe electron channel in the FET structure. Furthermore, realisticmodeling of the contacts is of the utmost importance for plasmawaves, because the boundary conditions have a very strong impacton device performance [11]. In a FET the channel is bounded by thesource/drain regions, which are inherently 2D. For accurate predic-tion of the device performance an approach beyond the transmis-sion line models is therefore required. A first step in this directionwas published in Ref. [12], where a 2D Poisson equation was solvedwith a 1D transport model in conjunction with still ideal boundaryconditions. A fully 2D approach based on the Monte-Carlo methodwas presented in Ref. [13], but its CPU times are prohibitive for thistype of investigation [14].

In this work we will present a deterministic approach for thesimulation of silicon devices based on a CPU-efficient 2D drift-diffusion (DD) model, where the time-derivative of the currentdensity is included in the constitutive equation for the current den-sity [1]. In the next section the model and its numerical implemen-tation are discussed, in the third the resistive mixer and in thefourth the model is applied to the simulation of THz signals inMOSFETs.

quantities are evaluated on the direct grid nodes (solid circles) and the vectorcomponents on the adjoint points (crosses).

2. Numerical approach

The simulation model comprises the DD model [15]

@n@t

¼ 1qr J

!n ð1Þ

@p@t

¼ �1qr J

!p ð2Þ

@ J!n

@t¼ � J

!n

sn� q2

mnnru� VTrnð Þ ð3Þ

@ J!p

@t¼ � J

!p

sp� q2

mppruþ VTrpð Þ ð4Þ

and the Poisson equation for the quasi-static potential

r � eruð Þ ¼ �q p� nþ ND � NAð Þ; ð5Þ

where n is the electron density, q the positive electron charge, J!n

the electron current density, sn the macroscopic relaxation timeof the electron momentum, mn the electron conductivity mass(mn ¼ 0:286m0 and mp ¼ 0:372m0 for silicon), u the quasi-staticpotential, VT the thermal voltage, e the permittivity, and ND thedonor concentration. The electron mobility is given byln ¼ qsn=mn. Corresponding hole quantities are labeled by p andNA is the acceptor concentration.

Eqs. (3) and (4) contain the time derivatives of the current den-sities, which are necessary to simulate plasma waves. In TCADimplementations of the DD model these derivatives are usuallyneglected, because the plasma waves cause numerical problemsand increase the CPU time of transient simulations very muchdue to the required time steps in the order of femtoseconds. In sil-icon the macroscopic relaxation times for electrons and holes areshorter than a picosecond and the derivatives can be savelyneglected for frequencies below 100 GHz [16,17], but not necessar-ily above.

Eqs. (1)–(5) are discretized on a 2D tensor-product grid with thefinite-volume method and dimensional splitting (Fig. 1) [15,18].The scalar quantities ðn; p;uÞ are evaluated on the nodes of thedirect grid and the Cartesian components of the current densitiesðJn;x; Jp;x; Jn;y; Jp;yÞ on the nodes of the adjoint grid. Due to thedimensional splitting the nodes of the adjoint grid are placed onthe edges of the grid primitives between two nodes of the directgrid. Since the time derivatives are not neglected, the current den-

sities can no longer be eliminated from the set of equations and thenumber of unknown variables increases from three to seven pergrid node. The second term on the right-hand side of (3) and (4)is stabilized by the Scharfetter-Gummel scheme [19], such that

in the slowly varying case ðj@ J!=@tj � j J

!=sjÞ the usual formulation

of the DD model is obtained. The terminal currents are evaluatedby the extended Ramo-Shockley theorem [20].

Stationary solutions of the DD model are obtained with theusual methods (Gummel loop [21] and Newton-Raphson method[15]). For the sinusoidal steady-state a small-signal analysis isimplemented and for the periodic steady-state (large-signal) thesingle-tone harmonic balance (HB) method [22]. In addition, theDD model can be solved in the time domain by a transientapproach. In this case Eqs. (1)–(4) are of the form

@u@t

¼ f ðu; tÞ: ð6Þ

Three different methods for time integration are used. Theimplicit (backward) Euler scheme (BE), the second-order backwarddifferentiation formula based on polynomials (BDF2) [23,24] andthe modified BDF2 scheme based on trigonometric functions(MBDF2) [25]. In all three cases the time derivative is approxi-mated for a constant time step Dt by

@u@t

�

�

�

�

iDt

� a0ui þ a1ui�1 þ a2ui�2

Dt¼ f i ð7Þ

with uðiDtÞ � ui and f ðuðiDtÞ; iDtÞ � f i. The coefficients are for the BEscheme

a0 ¼ 1; a1 ¼ �1; a2 ¼ 0; ð8ÞBDF2 scheme

a0 ¼ 1:5; a1 ¼ �2; a2 ¼ 0:5; ð9Þand MBDF2 scheme

a0 ¼ z cosð2zÞ � z cosðzÞsinð2zÞ � 2 sinðzÞ ; ð10Þ

a1 ¼ z sinðzÞcosðzÞ � 1

; ð11Þ

a2 ¼ z2 sinðzÞ ð12Þ

-0.20 -0.15 -0.10 -0.05 0.000 0.05 0.10 0.15 0.20

0.000

0.05

0.10

0.15

0.20

0.25

0.30

Source Gate Drain

Bulk

p-silicon

n-silicon n-silicon OX G

Fig. 3. 2D structure of the silicon NMOSFET. The ticks indicate the grid lines and thedashed thick lines are the metallurgical junctions. Numerical values are in lm.

C. Jungemann et al. / Solid-State Electronics 128 (2017) 129–134 131

with z ¼ 2p=nT . The MBDF2 scheme is used only for the periodicsteady-state and nT is the number of time steps used per period,where nT must be larger or equal to eight. All three formulas areA-stable, but show quite different spurious damping behavior inthe case of plasma waves.

The dopant-dependent low-field mobility in silicon is modeledaccording to Caughey and Thomas [26] and the channel mobilityin MOSFETs according to Lombardi et al. [27]. In all cases the resul-tant linear system of equations is solved by the direct sparsematrix solver PARDISO [28].

It is worth noting that without the time derivatives in (3) and(4) the particle densities will always be positive in the stationaryand transient case for the above mentioned discrete system. Assoon as the time derivatives of the current densities are included,second-order time derivatives of the particle densities occurimplicitly and positive particle densities are no longer ensured byconstruction of the discrete system. If negative particle densitiesare encountered, the simulation is terminated. At small AC ampli-tudes this problem does usually not occur.

3. Mixer model

An NMOSFET is used as a passive mixer in Ref. [8] and we use ananalogous circuit (Fig. 2). Due to the large externally added capac-itance CGD;ext gate and drain are effectively short-circuited at highfrequencies [8]. To capture this effect, the AC signal is applied tothe source terminal, and the gate and drain are AC-wise grounded[1]. The applied DC drain/source bias is zero. The MOSFET is oper-ated as a diode and it rectifies the AC signal, which leads to the DCdrain current. The responsivity of the mixer is given by the ratio ofthe DC drain current and AC input power at the source

RI ¼ IDCDPACS

; ð13Þ

where the AC input power is given by

PACS ¼ 1

T

Z T

0VSðtÞISðtÞdt: ð14Þ

The integral runs over one period with the duration T of theperiodic input signal, and the input power is proportional to thesquare of the AC voltage amplitude VAC similar to the DC drain cur-rent. The responsivity is thus constant over a wide range of ACinput power. Only for very large AC voltages the responsivitydepends on the AC power.

A similar responsivity can be defined for the drain voltage, if thedrain is kept DC-wise open (i.e. by a very large resistance in serieswith the drain inductance in Fig. 2). If the resultant DC drain volt-

VAC

Cblock

CGD,ext

VG

G

S DID

Fig. 2. Resistive mixer for AC power detection [8].

age is small, the device response is linear and at zero frequency andzero drain/source bias the channel conductance is given by thedrain self-admittance (GDS ¼ 1=RDS ¼ RfYDDg). The correspondingchannel current, which compensates the DC drain current due torectification, induces a DC drain voltage of VDC

D ¼ RDSIDCD . The volt-

age responsivity is thus given by [8]

RV ¼ VDCD

PACS

¼ RDSRI: ð15Þ

Simulation of the two different mixer configurations confirmsthis relation for the AC voltage amplitudes used in this study. Sincethe device structures are 2D, the voltage responsivity has to bedivided by the width of the device in the third dimension (theinput power is proportional to the device width). In the case ofthe current responsivity the DC current and input power are bothdependent on the width and it cancels in the responsivity.

In addition to the responsivity of a detector its noise-equivalent-power (NEP) is of importance and it should be as smallas possible. It is defined as the input power, for which the signal-to-noise ratio at the output is one for a bandwidth of 1 Hz [8]

NEPI ¼ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

4KBT0GDSp

RI¼

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

4KBT0RDSp

RV¼ NEPV ð16Þ

with the ambient temperature T0. At zero frequency and zerodrain/source bias the NMOSFET can be replaced by the channel con-ductance GDS, and the drain noise is given by the Johnson-Nyquistformula. In this calculation down-conversion of noise and 1/f-noise are neglected. Since our simulations are performed for 2Ddevice structures, the NEP has to be multiplied with the square rootof the width of the device in the third dimension.

4. Results

In Ref. [8] quarter-micron silicon NMOSFETs are used to detectTHz radiation and we use therefore a similar device (Fig. 3). Thegrid for real space, which is indicated by tick marks, is non-equidistant to better resolve the junctions and the channel area.The length of the gate is 250 nm, the oxide thickness 3 nm andthe threshold voltage 0:56 V. The 2D structure captures the mostimportant parasitics (e.g. the overlap capacitances between gateand source/drain). The artificial boundary conditions often usedin simulations for the channel (Dirichlet and inhomogeneousvon-Neumann type, e.g. [12]) are avoided by this approach andthe channel is realistically terminated by the highly-dopedsource/drain regions, into which plasma waves can enter fromthe channel. In addition, the channel is inhomogeneous, a fact

Fig. 5. Current responsivity at VG ¼ 1:0 V;VD ¼ 0:0 V;VAC ¼ 1 mV and room tem-perature for a 0:25 lm NMOSFET with a constant electron mobilityln ¼ 10;000 cm2=Vs for 1 THz evaluated by transient simulations (BE, BDF2,MBDF2) and harmonic-balance calculations (HB).

Fig. 6. Current responsivity at VD ¼ 0:0 V; VAC ¼ 0:1 mV and room temperature forthe NMOSFET as a function of the gate bias for selected frequencies.


not easily included in 1D transmission line models. The interfacebetween the oxide and silicon is assumed to contain no traps andcorresponding effects (e.g. 1/f noise) are neglected.

The Boltzmann Transport Equation (BTE) yields the most funda-mental description of semiclassical transport in semiconductordevices [29]. The more CPU-efficient DDmodel can be derived fromthe BTE by projection on certain moments, but this processinvolves approximations of unknown quality [30]. It is not clearhow accurately the DD model can describe transport at frequen-cies, where plasma effects occur. In Fig. 4 the real part of thedrain/gate admittance is shown as a function of the frequency forthe NMOSFET. This small-signal result is calculated by the DDmodel with and without the time derivative of the current densi-ties and by a spherical harmonics expansion of the BTE [31]. In thiscase the electron and hole mobilities are given by their respectivebulk values [26] neglecting interface effects to facilitate a simplercomparison of the two models. Below 150 GHz the real part ofthe admittance is positive and all three models yield similarresults. Above 1 THz differences occur. The impact of the plasmaoscillations is manifested in the non-monotonic behavior of theresults of the BTE and the DD model including the time derivativeof the current densities. The DD model and the BTE show reason-able agreement even at very high frequencies. Thus, the DD modelwith the time derivative of the current densities is able to capturethe most salient aspects of the plasma oscillations.

The responsivity is an inherently nonlinear effect and requires alarge-signal simulation, which can be performed in the time or fre-quency domain for the periodic steady-state. The transient simula-tions in the time domain are based on the time-integrationschemes presented in Section 2 and a sufficient number of periodsis used to reach the periodic steady-state. The responsivity is calcu-lated by integrating the drain current and the input power at thesource over the last simulated period. In Fig. 5 the current respon-sivity of the NMOSFET is shown for the different time integrationschemes as a function of the number of time steps per period fora very large electron mobility in order to emphasize the plasmaeffects. While the dependence of the MBDF2 result on the numberof time steps is negligible, the other two schemes show a strongdependence and the responsivity is underestimated. This is dueto the strong over-damping of these schemes, which decreaseswith increasing number of time steps [25]. For the periodicsteady-state the MBDF2 scheme is the by far most efficient oneand its results are in excellent agreement with the HB approach.This is due to the fact that the MBDF2 scheme is based on trigono-metric functions similar to the HB method. Depending on the

Fig. 4. Real part of the small-signal drain/gate admittance at VG ¼ 2:0 V;VD ¼ 0:1 Vand room temperature for the NMOSFET.

problem, either HB or MBDF2 simulations are more CPU efficient,where the MBDF2 simulations are often numerically more robust.This result also shows that the MBDF2 scheme should be superiorto the BDF2 scheme in the case of active devices, where usuallytransient simulations with the BDF2 scheme are used (e.g. [12])and the over-damping could suppress or delay the onset of activedevice behavior.

The current responsivity is shown in Fig. 6 for the NMOSFET fordifferent frequencies as a function of the DC gate bias. For a givenfrequency the responsivity has a maximum in the sub-thresholdregion, where the channel resistance is very large and the relativeresistive mixing strongest. The peak responsivity rapidly dropswith increasing frequency and moves to higher gate voltages. InFig. 7 the current responsivity is shown as a function of the fre-quency up to 10 THz for zero gate overdrive with and withoutthe time derivatives of the current densities. In both cases itstrongly drops with frequency and the differences are rather smalldue to the strong over-damping of the plasma waves by the lowelectron momentum relaxation time in silicon. Only weakenhancement of the responsivity at high frequencies due to plasmaoscillations is found similar to Ref. [17].

Fig. 7. Current responsivity at VG ¼ 0:56 V;VD ¼ 0:0 V;VAC ¼ 0:1 mV and roomtemperature for the NMOSFET as a function of frequency with and without thetime derivative of the current density.

Fig. 8. Voltage responsivity at VD ¼ 0:0 V;VAC ¼ 0:1 mV and room temperature forthe NMOSFET as a function of the gate bias for selected frequencies.

Fig. 9. Noise-equivalent-power at VD ¼ 0:0 V;VAC ¼ 0:1 mV and room temperaturefor the NMOSFET.

Fig. 10. DC shift of the electric potential along the oxide/silicon interface of theNMOSFET due to the AC signal at VG ¼ 0:56 V;VD ¼ 0:0 V;VAC ¼ 0:1 mV and roomtemperature for two frequencies and current (CS) and voltage (VS) sensing.

C. Jungemann et al. / Solid-State Electronics 128 (2017) 129–134 133

The voltage responsivity (Fig. 8) shows a similar behavior as thecurrent one (Fig. 6), where peak values are shifted to lower gatevoltages due to the multiplication with the zero-frequency channelresistance (15). Since the channel resistance is evaluated for zerofrequency, the frequency dependence of the voltage and currentresponsivities are the same.

The noise-equivalent-power (Fig. 9) has distinct minima, whichare found for gate biases below the gate voltages for peak currentresponsivity (Fig. 6), because it is proportional to the ratio of thesquare root of the zero-frequency channel conductance and cur-rent responsivity (16). The frequency dependence is thereforeinversely proportional to the one of the responsivity and thenoise-equivalent-power strongly increases with frequency.

The response of the DC component of the electric potentialwithin the NMOSFET due to the AC signal is shown in Fig. 10 forthe case of current and voltage sensing along the interface betweenthe oxide and silicon bulk (the line with zero vertical coordinate inFig. 3). At 1 GHz the potential response for current sensing DuDC

CS isalmost symmetric, whereas at 1 THz the maximum of the absolutevalue of the potential response moves towards the source. In thecase of voltage sensing the induced DC drain voltage results in aroughly linearly varying potential in the channel region, whichhas to be added to the potential response

DuDCVS ¼ DuDC

CS þ @u@VD

VDCD ; ð17Þ

where @u=@VD is the derivative of the potential w.r.t. the drain volt-age for zero frequency and zero drainsource bias. The built-up of theDC response of the potential therefore occurs in this case mostly inthe channel near the source.

5. Conclusions

The developed drift-diffusion model goes beyond the state-of-the-art, because it is 2D in real space and includes the time deriva-tives of the current densities. It is thus possible to capture manyeffects neglected by the usual quasi-1D approaches. We havedemonstrated that the drift-diffusion model can be used to simu-late NMOSFETs in the THz range and we have assessed its accuracyby comparison with the more fundamental Boltzmann transportequation. It appears that the backward-differentiation formula ofthe second order based on trigonometric functions is a very CPU-efficient time-integration scheme for the periodic steady-state.

The current and voltage responsivities have been investigatedand the highest values are found for gate voltages below thethreshold voltage even at one THz. Up to this frequency the impact


of plasma waves seems to be small due to the strong damping bythe low electron momentum relaxation time in silicon.

References

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Anisotropic interpolation method of silicon carbide oxidation growthrates for three-dimensional simulation


⇑ Corresponding author at: Christian Doppler Laboratory for High PerformanceTCAD at the Institute for Microelectronics, TU Wien, Gußhausstr. 27-29/E360, 1040Wien, Austria.

E-mail address: [email protected] (V. Šimonka).

Vito Šimonka a,b,⇑, Georg Nawratil c, Andreas Hössinger d, Josef Weinbub a,b, Siegfried Selberherr b

aChristian Doppler Laboratory for High Performance TCAD at the Institute for Microelectronics, TU Wien, Gußhausstr. 27-29/E360, 1040 Wien, Austriab Institute for Microelectronics, TU Wien, Gußhausstr. 27-29/E360, 1040 Wien, Austriac Institute of Discrete Mathematics and Geometry, TU Wien, Wiedner Hauptstraße 8-10, 1040 Wien, Austriad Silvaco Europe Ltd., Compass Point, St Ives, Cambridge PE27 5JL, United Kingdom




Keywords:Silicon carbideOxidationGrowth ratesAnisotropyInterpolation

a b s t r a c t

We investigate anisotropical and geometrical aspects of hexagonal structures of Silicon Carbide and pro-pose a direction dependent interpolation method for oxidation growth rates. We compute three-dimensional oxidation rates and perform one-, two-, and three-dimensional simulations for 4H- and6H-Silicon Carbide thermal oxidation. The rates of oxidation are computed according to the four knowngrowth rate values for the Si- ð0001Þ, a- ð11 �20Þ, m- ð1 �100Þ, and C-face ð000 �1Þ. The simulations arebased on the proposed interpolation method together with available thermal oxidation models. We addi-tionally analyze the temperature dependence of Silicon Carbide oxidation rates for different crystal facesusing Arrhenius plots. The proposed interpolation method is an essential step towards highly accuratethree-dimensional oxide growth simulations which help to better understand the anisotropic natureand oxidation mechanism of Silicon Carbide.


1. Introduction

Silicon Carbide (SiC) has excellent physical properties and hasreceived significant attention in recent years as a Silicon (Si)replacement material for power device applications due to a highelectrical breakdown voltage and a high thermal conductivity.Compared to Si, SiC has approximately a three times wider bandgap, ten times larger electrical breakdown voltage, and three timeshigher thermal conductivity [1–3]. Taking advantages of theseproperties, the on-state resistance for unipolar devices such asmetal-oxide-semiconductor field-effect-transistors (MOSFET) canbe reduced by a factor of a few hundreds when replacing Si withSiC [4,5]. Aside from the theoretical advantages in SiC devices,the need for numerical simulation based on accurate models isindispensable to further the success of modern power electronics.

Among the numerous polytypes of SiC, most popular for deviceapplications are 3C-SiC, 4H-SiC, 6H-SiC, and 15R-SiC. These poly-types are characterized by the stacking sequence of the bi-atomlayers of the SiC structure. Changing the stacking sequence has aprofound effect on the electrical properties. See Fig. 1a for an

atomic view of a 4H-SiC. In this work, we focus on 4H- and 6H-SiC as they have been recognized as the most promising polytypesand are currently commercially available for high power, high fre-quency, and high temperature applications [6,7].

Thermally grown oxide layers (SiO2) play a unique role in devicefabrication, e.g., lateral structures in planar technology and passi-vation of device surfaces. Therefore, it is necessary to have a solidunderstanding of oxidation growth rates and the dependence onthe crystallographic planes of SiC. Among the wide bandgap semi-conductors, SiC is the only compound semiconductor which can bethermally oxidized in the form of SiO2, similar to conventional Sisubstrate. This is seen as one of the most important technologicalproperties of SiC and has motivated considerable effort in its devel-opment. The following reaction governs the oxidation of SiC [1]:

SiCþ 32O2 $ SiO2 þ CO: ð1Þ

As opposed to the relatively simple oxidation of Si, the thermaloxidation of SiC includes five steps [2] (discussed in the following)and is about one order of magnitude slower under the same condi-tions [8,9]:

1. Transport of molecular oxygen gas to the oxide surface.2. In-diffusion of oxygen through the oxide film.3. Reaction with SiC at the SiO2/SiC interface.







(a)

a

a

c

a

c

(b)

z

x

y

Fig. 1. (a) A schematic illustration of an atomic view of a 4H-SiC polytype withsequence ABAC. Yellow (big) spheres show the Si atoms, gray (small) spheres Catoms, a is the crystal dimension, and c is the crystal height. The ratio between c anda for 4H-SiC is approximately three and for 6H-SiC approximately five. (b) Aschematic illustration of common faces of a hexagonal structure. Green (top), blue(diagonal), red (right), and orange (bottom) shapes show the Si-, a-, m-, and C-face,respectively. (For interpretation of the references to colour in this figure legend, thereader is referred to the web version of this article.)

136 V. Šimonka et al. / Solid-State Electronics 128 (2017) 135–140

4. Out-diffusion of product gases through the oxide film.5. Removal of product gases away from the oxide surface.

The last two steps are not involved in the oxidation of Si. Thefirst and the last steps are relatively fast and are not rate-controlling steps.

Another unique phenomenon has been observed: The oxidationof SiC is a face-terminated oxidation, i.e., the top and the bottomface have different oxidation rates [10–12]. Additionally, the oxida-tion of SiC varies also with other crystallographic planes asreported in [7,13,14], see Fig. 1b for common faces of 4H-SiC. Thedependence of the oxidation rates on crystal orientation has signif-icant consequences for a non-planar device structure, e.g., thetrench design of a U-groove MOSFET, where the oxide is locatedon all crystallographic planes [7].

In Section 2 we discuss the thermal oxidation process and phys-ical models of Si and SiC, in Section 3 we introduce the temperaturedependence of the oxidation growth rates with Arrhenius plots, inSection 4 we discuss anisotropical and geometrical aspects of 4H-and 6H-SiC as well as our proposed interpolation method, and inSection 5 one-, two-, and three-dimensional simulations and calcu-lations for initial and linear growth rates of SiC thermal oxidationare discussed.

2. SiC oxidation models

Thermal oxidation of SiC can be mathematically described withthe Deal-Grove model [15], which has been originally proposed toexplain the Si oxidation process. According to this model, the oxi-dation occurs by diffusion of the oxidant to the SiO2/Si interface,where it reacts with Si. The relation between the oxide thicknessX and oxidation time t is thus expressed by the following equation:

X2 þ AX ¼ Bðt þ sÞ; ð2Þwhere B=A; B, and s are the linear rate constant, parabolic rate con-stant, and the constant related to the initial oxide thickness, respec-tively. Eq. (2) can be rewritten as ordinary differential equation:

dXdt

¼ BAþ 2X

ð3Þ

In the Deal-Grove model, the linear rate constant B=A is the oxi-dation rate when 2X � A, in which the interface reaction is therate-controlling step [15]. The parabolic rate constant B is the oxi-dation rate when 2X � A, in which the diffusion of oxygen throughthe oxide film SiO2 is the rate-controlling step [15].

The oxidation process cannot be characterized by the Deal-Grove model for the thin oxide region in Si and SiC, hence Massoudet al. [16] have proposed an empirical relation to describe thegrowth rate enhancement in a thin oxide regime. This modelincludes an additional exponential term [16],

dXdt

¼ BAþ 2X

þ C exp �XL

� �

; ð4Þ

where C and L are the exponential prefactor and the characteristiclength, respectively.

It has been reported that the linear rate constant B=A and initialgrowth rate B=Aþ C highly depend on the crystal orientation of SiC[1,6,7,14], i.e., the growth rate values are different for the surfaceoxidation on different faces of the crystal. On the other hand, theparabolic rate constant B does not depend on the crystal orienta-tion [1].

The Deal-Grove model and Massoud’s empirical relation wereoriginally proposed for Si oxidation, but can be applied in a modi-fied form to SiC oxidation [2]. For SiC oxidation the Massoudempirical relation can reproduce the oxide growth better thanDeal-Grove model [17,18]. However, due to the one-dimensionalnature both models fail to correctly predict the oxide growth forthree-dimensional SiC structures. Our approach extends thesemodels by incorporating the crystal direction dependence intothe oxidation growth rates, thus enabling accurate three-dimensional modeling.

3. Temperature dependencies

Rates of chemical reactions depend on various physical quanti-ties, e.g., temperature and pressure. The collision theory and tran-sition state theory implies that chemical reactions typicallyproceed faster at higher temperature and pressure, and slower atlower temperature and pressure. The molecules move faster asthe temperature increases and therefore collide more frequently,which changes the properties of the involved chemical reactions.

The relation between the absolute temperature T and the rateconstant k is given via an Arrhenius equation [3,19]:

k ¼ Z exp � Ea

kBT

� �

ð5Þ

Z is the pre-exponential factor discussed below, Ea is the activa-tion energy of the chemical reaction, and kB is the Boltzmann con-stant. Recalling that kT is the average kinetic energy, it becomesapparent that the exponent is the ratio of the activation energyEa to the average energy of colliding molecules. The larger the ratio,the smaller the reaction rate. This means that high temperatureand low activation energy favor larger rate constants, and thusspeed up the reaction. The pre-exponential factor Z is known asthe frequency or collision factor and can be calculated from kineticmolecular theory. In other words, Z is equal to the fraction of mole-cules which are involved in a chemical reaction, if (1) the activationenergy Ea ¼ 0 or (2) the kinetic energy of all molecules exceeds Ea

[20,21].The Arrhenius equation can be used to determine the activation

energy of the oxidation growth rates [1]. The equation can be writ-ten in a non-exponential form by applying the natural logarithmon both sides of the equation:

lnðkÞ ¼ � Ea

kB

1Tþ lnðZÞ ð6Þ

In this form, the Arrhenius equation is more convenient to useand to interpret graphically, as it appears as a linear function

w ¼ mvþ n; ð7Þ

0.60 0.65 0.70 0.75 0.80 0.85 0.901

10

100

1000B/

A+C

[nm

/h]

1000/T [K-1]

C-facea-facem-faceSi-face

1000 1200 14000

100

200

B/A+

C [n

m/h

]

T [K]

Fig. 2. Arrhenius plot for initial growth rates B=Aþ C for the Si- (green), m- (red), a-(blue), and C-face (orange) of dry thermal oxidation of 4H-SiC. Experimental datafor the Si-, a-, and C-face (symbols) are obtained from [1] and the data for the m-face (solid red lines) are approximated from [14]. (For interpretation of thereferences to colour in this figure legend, the reader is referred to the web version ofthis article.)

(a)

y

x

(b)

z

x

Fig. 3. Schematic representation of the proposed interpolation method in the (a) x-y and (b) x-z plane. A linear (black dotted) and a non-linear (dark blue line)interpolation is calculated according to four known growth rate values (blackcrosses) of Si- (green), m- (red), a- (blue), and C-face (orange square). Coloredarrows represent crystal directions towards the corresponding faces. The arrowlengths are proportional to the oxidation growth rates. (For interpretation of thereferences to colour in this figure legend, the reader is referred to the web version ofthis article.)

V. Šimonka et al. / Solid-State Electronics 128 (2017) 135–140 137

where w ¼ lnðkÞ is the dependent variable, v ¼ 1=T is the indepen-dent variable, m ¼ �Ea=R is the slope, and n ¼ lnðZÞ is the intercept.The activation energy is thus determined from the growth rate val-ues at different temperatures by plotting lnðkÞ as a function of 1=T.

Fig. 2 shows an exemplary Arrhenius plot for initial growthrates of 4H-SiC dry thermal oxidation. The data points are mea-sured values, the dashed lines are fits using Massoud’s empiricalrelation (4), and the solid lines are approximated values. We haveobtained the growth rates and activation energies of the Si-, a-, andC-face from experimentally measured data [1] and approximatedthe growth rate and activation energy for the m-face based on pub-lished oxide thicknesses [14], as there are no experimental dataavailable. We use these data sets to analyze the effect of tempera-ture on oxidation and to obtain the fixed growth rate values for theproposed interpolation method.

4. Interpolation method

With respect to the interpolation method, the geometricalaspects of SiC are mathematically described according to basiccrystallography and experimental findings [14,22]. A unit cell ofthe hexagonal crystal structure includes six ð1 �100Þ and sixð11 �20Þ crystallographic faces symmetric with respect to the z axis,while there is only one ð0001Þ face on the top and one ð000 �1Þ faceon the bottom of the crystal (see Fig. 1b).

We propose a direction dependent interpolation method [23] toconvert an arbitrary crystal direction into a growth rate for oxida-tion, according to a set of known growth rate values. For fixedpoints of oxidation growth rates we use growth rates of experi-mentally examined crystallographic faces of SiC [1,6,13]: Si-, m-,a-, and C-face, which correspond to the ð0001Þ; ð1 �100Þ; ð11 �20Þ,and ð000 �1Þ crystal directions, respectively.

The proposed interpolation method consists of a symmetric starshape in the x-y plane and a tangent-continuous union of two half-ellipses in z direction. See Fig. 3 for a schematic representation ofthe method in the x-y and x-z plane. Dark blue lines show the pro-posed interpolation between fixed points, which takes the symme-try of the hexagonal structure of SiC into account. Arrow directionsand lengths represent crystal directions toward SiC faces and oxi-dation growth rate values, respectively. We could also consider aless accurate linear interpolation (shown with dotted black lines)with sharp edges, which would also fit the geometry of SiC, butthe non-linear method offers considerable higher accuracy and isthus further used in this work.

The parametric expression of the three-dimensional interpola-tion method is

x ¼ ðky þ ðkx � kyÞ cos2ð3tÞÞ cosðtÞ cosðuÞ;y ¼ ðky þ ðkx � kyÞ cos2ð3tÞÞ sinðtÞ cosðuÞ;z ¼ kz sinðuÞ;

ð8Þ

where t 2 ½0;2p� and u 2 ½�p=2;p=2� are arbitrary parametric vari-ables and kx;y;z are known oxidation growth rates in x; y, and z direc-tion, respectively. In our case we consider: kx ¼ km; ky ¼ ka, andkz ¼ kC or kSi.

As shown in several studies [1,24,25], the oxide growth on topand bottom of the crystal is different, thus we need to calculatethe positive and negative z coordinates separately:

z ¼ kþz sinðuÞ for u P 0z ¼ k�z sinðuÞ for u < 0

ð9Þ

kþz and k�z correspond to the growth rate in the direction of the Si-and C-face, respectively. Thus, we define that kþz ¼ kSi and k�z ¼ kC .

The parametric expression of the proposed interpolationmethod can be converted into an explicit expression, whichdescribes the surface as the zero set of equation Fðx; y; zÞ ¼ 0,where x; y, and z are the variables, e.g., vector coordinates. Theexplicit representation is more general and more suitable forone- and two-dimensional calculations, and is more closely relatedto the concepts of constructive solid geometry and modeling. How-ever, the parametric form is more useful for three-dimensional cal-culations and remains dominant in computer graphics andgeometrical modeling.


We have performed several one-, two-, and three-dimensionalcalculations of growth rates and simulations of thermal SiC oxida-tion using the proposed interpolation method together with Mas-soud’s empirical relation and Arrhenius plots. Fig. 4 showsschematic representations of the hexagonal crystal structure andvariables for simulations which are used in the following discus-sion. Out of simplicity, the two-dimensional simulations are per-formed either in the x-y or in the x-z plane. The input of the

interpolation method is an arbitrary crystal direction vector v!con-

tained in the x-y or x-z plane, for which the oxidation growth rate

has to be computed. By denoting the angle between v!

and the x-axis by a in x-y plane or by b in x-z plane, we get trivial relations

(a)

y

xα

v

(b)

z

x

v

β

Fig. 4. Schematic representation of the hexagonal crystal structure in (a) x-y and (b)x-z plane. v

!is crystal direction vector, a is an angle between the x and y-axis, and b

is an angle between the vector and the x and z-axis. Blue (diagonal), red (right),green (top), and orange (bottom) squares represent a-, m-, Si-, and C-face,respectively. (For interpretation of the references to colour in this figure legend,the reader is referred to the web version of this article.)


x ¼ j v! j cosa;y ¼ jv! j sina;

ð10Þ

and

x ¼ j v! j cos b;z ¼ j v! j sin b;

ð11Þ

(a)

0 60 120 180 240 300 360

0.78

0.80

0.82

(b)

0 60 120 180 240 300 360

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

Fig. 5. Thermally grown oxide thickness as a function of (a) angle a in x-y plane and(b) angle b in x-z plane as shown in Fig. 4. The oxide thickness Xnorm is normalizedusing the maximal oxide thickness from individual simulations and measurementsfor direct comparisons. Blue solid lines are simulations performed with availableoxidation models using the proposed interpolation method. Orange triangles andred squares are experimental measurements from [14,22], respectively. Blackarrows show fixed points for the interpolation method: km; ka; kSi , and kC .Simulations are performed for the wet thermal oxidation of 6H-SiC (0001) Si-face(n-type, on-axis) at T ¼ 1100 �C for 720 min. (For interpretation of the references tocolour in this figure legend, the reader is referred to the web version of this article.)

where x; y, and z are the crystal direction vector coordinates

v!ðx; y; zÞ and j v! j is the vector length. The crystal direction vector

v!is normalized, thus jv! j ¼ 1.

5.1. One-dimensional simulations

Thermally grown oxide thicknesses as a function of a and b, theangle between the crystal direction vector and the x-axis, are shownin Fig. 5. The oxide thicknesses have been normalizedwith themax-imal oxide thickness from individual simulations and measure-ments for direct comparisons, i.e., Xnorm ¼ 1 corresponds to themaximum oxide thickness, whereas Xnorm ¼ 0 corresponds to nooxide at all. Fig. 5a shows simulation results (blue lines) for the crys-tallographic plane x-y and Fig. 5b for the crystallographic plane x-z.Orange triangles aremeasurements by Christiansen and Helbig [14]and red squares are measurements by Tokura et al. [22]. The calcu-lation of growth rates as well as the simulations of thermal oxida-tion are performed for the angle from 0� to 360� for both planes.

In Fig. 5a, we observe six maxima and six minima in the x-yplane, which correspond to the m- and the a-face, respectively.On the other hand, in Fig. 5b we observe one maximum and oneminimum in the x-z plane, which correspond to the C- and theSi-face, respectively. From comparing the normalized oxide thick-nesses with the measurements from Christiansen and Helbig [14]we can argue that the proposed interpolation method fits experi-mental data very well. On the other hand, comparing results withmeasurements from Tokura et al. [22], the simulations do not fit allexperimental data perfectly, but the shape and the extreme valuesare properly consistent.

5.2. Two-dimensional simulations

Fig. 6 shows the two-dimensional interpolation of the lineargrowth rates B=A of the wet thermal oxidation at T ¼ 1100 �C in

(a)

-1.0

-0.50.0

0.51.0

43

44

45

46

47

-1.0

-0.5

0.0

0.5

1.0

B/A

[nm

/h]

yx

(b)

-1.0-0.5

0.00.5

1.0-1.0-0.50.0

0.51.010

20304050607080

B/A

[nm

/h]

x z

Fig. 6. Two-dimensional calculations of the SiC linear oxidation growth rates B=Ausing the proposed interpolation method in the (a) x-y and (b) x-z plane. x; y, and zare normalized crystal direction vector coordinates. Interpolation is performed forthe wet thermal oxidation of 6H-SiC (0001) Si-face (n-type, on-axis) at T ¼ 1100 �C.

(a)

-0.4-0.2

0.00.2

0.4-0.4

-0.20.0

0.20.4410

415420

425

430

435

440X

[nm

]

x y

(b)

-0.4

-0.2

0.0

0.2

0.4

500450400350300250200

-0.4

-0.2

0.0

0.2

0.4

X [n

m]

zx

Fig. 7. Two-dimensional simulations of the wet thermal oxidation of SiC in the (a)x-y and (b) x-z plane. The figures show the final oxide thicknesses X as a function ofthe normalized crystal direction vector coordinates x; y, and z. The final oxidethicknesses are obtained using the available oxidation models and the results fromprevious plots (cf. Fig. 6). Red, blue, orange, and green colors represent oxidethicknesses for the m-, a-, C-, and Si-face, respectively. Simulations are performedfor the wet thermal oxidation of 6H-SiC (0001) Si-face (n-type, on-axis) atT ¼ 1100 �C for 720 min. (For interpretation of the references to colour in this figurelegend, the reader is referred to the web version of this article.)

(a)

B/A+

C(y

)[nm

/h]

B/A+C (x) [nm/h]

ka

km

50

0

50

50 0 50

(b)

kSi

kC

B/A+

C(z

)[nm

/h]

B/A+C (x) [nm/h]

0

100

50

50 0 50

Fig. 8. Three-dimensional calculations of the SiC initial oxidation growth ratesB=Aþ C obtained with the parametric expression of the proposed interpolationmethod. The figure shows the (a) top and (b) front view of the growth rates’ surface.An arbitrary direction growth rate is calculated according to the four known growthrates (kSi; km; ka , and kC ) shown with black arrows. The surface color showscalculations for positive (green) and negative (orange) z direction. Interpolation isperformed for the dry thermal oxidation of 4H-SiC (0001) Si-face (n-type, on-axis)at T ¼ 1100 �C. (For interpretation of the references to colour in this figure legend,the reader is referred to the web version of this article.)

V. Šimonka et al. / Solid-State Electronics 128 (2017) 135–140 139

the x-y and the x-z plane using normalized crystal direction vectorcoordinates x; y, and z as input for the interpolation method. Thecombination of vector coordinates is set in a way that it gives allpossible crystal direction vectors to compute growth rates, whichis clearly seen by the gray circle below the plots. Fixed points forthe interpolation were approximated from [14,22] and calibratedaccording to the available data [26–28], thus the linear growthrates B=A towards the Si-, a-, m-, and C-faces are kSi ¼ 15:25 nm/h, ka ¼ 43:33 nm/h, km ¼ 47:19 nm/h, and kC ¼ 81:60 nm/h,respectively. The results from the interpolation are used in the fol-lowing simulations.

Oxide thicknesses thermally grown in a wet circumstance as afunction of the vector coordinates x; y, and z are summarized inFig. 7. These results show final oxide thicknesses X in the x-y andthe x-z plane of a crystal. The combination of vector coordinatesðx; yÞ or ðx; zÞ define the crystal direction for which the oxide thick-ness is calculated. The results from Fig. 7a and b cover the whole x-y and x-z plane full of the given crystal directions. In the first plotwe can observe six maxima and six minima, which correspond tothe m- and the a-face, respectively. The final oxide thickness inthe direction of the m-face is approximately 442 nm, and in thedirection of the a-face 412 nm. On the second plot we observe amaximal and minimal oxide thickness, which correspond to theC- and the Si-face, respectively. The final oxide thickness in thedirection of the Si-face is approximately 173 nm and in the direc-

tion of the C-face 531 nm. The results are in agreement with [14]for wet thermal oxidation of 6H-SiC.

5.3. Three-dimensional simulations

Fig. 8 shows the three-dimensional interpolation of the initialgrowth rates B=Aþ C of the dry thermal oxidation at T ¼ 1100 �Cusing the parametric expression of the proposed interpolationmethod (8) and (9). Fixed oxidation growth rate values arekSi ¼ 27:36 nm/h, ka ¼ 41:83 nm/h, km ¼ 66:64 nm/h, andkC ¼ 122:8 nm/h, obtained from the Arrhenius plot (Fig. 2) atT ¼ 1100 �C. The growth rate surface is given by a nonlinear inter-polation between these known growth rate values and follows thegeometry of SiC, i.e., the crystallographic planes tangent to thegrowth rate surface at kSi; km; ka, and kC are parallel to the corre-sponding faces. The distance from the origin (0,0,0) to any pointon the growth rate surface gives the oxidation rate in directionto this point. The set of growth rate values together with the SiCoxidation models are used for the following three-dimensionalsimulations of 4H-SiC dry thermal oxidation.

The surface of the oxide thicknesses of the dry initial thermaloxidation of 4H-SiC is shown in Fig. 9. The simulations are per-formed using Massoud’s empirical relation and previously calcu-lated initial growth rate values B=Aþ C (Fig. 8). The distancefrom the origin (0,0,0) to any point on the surface gives the oxidethickness in the direction of this point. For the oxidation time of15 min, the final oxide thicknesses in the direction of the common

(a)

X( y

) [nm

]

X (x) [nm]

5

0

5

5 0 5

(b)

X(z

)[nm

]

X (x) [nm]

0

10

5

5 0 5

Fig. 9. Three-dimensional simulations of the dry thermal oxidation of SiC. Thefigure shows the (a) top and (b) front view of the oxide thicknesses surface. Thefinal thicknesses X in an arbitrary crystal directions are obtained using the availableoxidation models and the results from previous plots (cf. Fig. 8). Simulations areperformed for the dry thermal oxidation of 4H-SiC (0001) Si-face (n-type, on-axis)at T ¼ 1100 �C for 15 min.


faces are approximately Xm ¼ 5:74 nm, Xa ¼ 2:67 nm,XSi ¼ 1:42 nm, and XC ¼ 11:16 nm. These results are in agreementwith [1,6] for the dry thermal oxidation of 4H-SiC.

6. Conclusions

We investigated the anisotropy of 4H- and 6H-SiC oxidationprocesses with regard to surface orientations. By carefully studyinggeometrical aspects of the hexagonal crystal structure we haveproposed an interpolation method to compute oxidation growthrate constants in one-, two-, and three-dimensional problems.The interpolation method includes well known anisotropy of theoxidation of the Si- and the C-face, as well as the anisotropicbehavior of the m- and the a-face. In the basic crystal plane x-y,which intersects with the origin of the unit cell, six maxima andsix minima are computed, corresponding to the crystal symmetryin the shape of a star.

Using the proposed interpolation method we have calculatedlinear growth rates for the wet thermal oxidation of 6H-SiC atT ¼ 1100 �C and initial growth rates for the dry thermal oxidationof 4H-SiC at T ¼ 1100 �C. With results from the interpolation wehave additionally performed one-, two-, and three-dimensionalsimulations using the Massoud oxidation model.

The presented results of thermal oxidation of SiC are in goodagreement with experimental findings from the literature. Wecan also show that the proposed nonlinear interpolation methodfits the geometry dependence of 4H- and 6H-SiC oxidation verywell. Moreover, with the proposed method, we are now able tosimulate three-dimensional dry and wet oxidation of SiC, wherethe only limiting factor is the set of fixed growth rates, which areusually obtained from measurements.

Acknowledgment

The authors wish to thank Y. Hijikata for providing experimen-tal data. The financial support by the Austrian Federal Ministry ofScience, Research and Economy and the National Foundation forResearch, Technology and Development is gratefully acknowledged.

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Framework to model neutral particle flux in convex high aspect ratiostructures using one-dimensional radiosity


⇑ Corresponding author.E-mail address: [email protected] (P. Manstetten). 1 The flux which originates from direct visibility of the source area.

Paul Manstetten a,⇑, Lado Filipovic b, Andreas Hössinger c, Josef Weinbub a,b, Siegfried Selberherr b

aChristian Doppler Laboratory for High Performance TCAD, Institute for Microelectronics, TU Wien, Gußhausstraße 27-29/E360, 1040 Wien, Austriab Institute for Microelectronics, TU Wien, Gußhausstraße 27-29/E360, 1040 Wien, Austriac Silvaco Europe Ltd., Compass Point, St Ives, Cambridge PE27 5JL, United Kingdom




Keywords:High aspect ratioNeutral particle fluxEtchingRadiosityView factor

We present a computationally efficient framework to compute the neutral flux in high aspect ratio struc-tures during three-dimensional plasma etching simulations. The framework is based on a one-dimensional radiosity approach and is applicable to simulations of convex rotationally symmetric holesand convex symmetric trenches with a constant cross-section. The framework is intended to replace thefull three-dimensional simulation step required to calculate the neutral flux during plasma etching sim-ulations. Especially for high aspect ratio structures, the computational effort, required to perform the fullthree-dimensional simulation of the neutral flux at the desired spatial resolution, conflicts with practicalsimulation time constraints. Our results are in agreement with those obtained by three-dimensionalMonte Carlo based ray tracing simulations for various aspect ratios and convex geometries. With thisframework we present a comprehensive analysis of the influence of the geometrical properties of highaspect ratio structures as well as of the particle sticking probability on the neutral particle flux.


1. Introduction

High aspect ratio structures are essential for the fabrication ofvarious semiconductor devices, where the aspect ratio (AR) of thestructure is defined as depth/diameter in case of cylinders and asdepth/width in case of trenches. One particular example isnegative-AND (NAND) flash cell fabrication [1], where three-dimensional multi-layer designs (3D-NAND) involve vertical holeswhich require aspect ratios above 40. Significant pressure on con-trol of the fabrication process as well as on modeling and simula-tion techniques originates from these high aspect ratio structures.

One process to fabricate high aspect ratio structures ision-enhanced chemical etching (IECE) [2]. In this process, the sur-face is exposed to reactive atoms and molecules from the plasma,which chemically react with the surface to form a volatile product.However, not only volatile products are created in this reaction,but also non-volatile by-products which hinder subsequent surfacereactions and therefore decrease the etch rate. This chemical seal-ing is frequently desired on the vertical sidewall of high aspectratio structures. To maintain a high etch rate at the bottom regionof a structure, the surface is additionally bombarded with vertically

accelerated ions, with the purpose of removing the non-volatileby-products on exposed areas. This makes a highly anisotropicchemical etching possible, supporting the fabrication of highaspect ratio structures.

To simulate an IECE process, a common approach is to modelthe reactive atoms and molecules of the plasma as electrically neu-tral particles that diffuse into the domain. In contrast, the acceler-ated ions are modeled as a directed source. A general simulationsequence for a single time step is to (a) calculate the local neutralparticle flux and the local ion flux adsorbed on the surface, (b)model the local surface reaction using the obtained flux rates,and (c) calculate the new surface positions.

Common approaches for three-dimensional flux calculation areMonte Carlo ray tracing [3] and radiosity based [4] methods. Whenapplying these methods to high aspect ratio structures, the compu-tational costs for the neutral flux calculation dominates the simu-lation. The local neutral flux originating from multiple reflectionsbecomes the dominant component towards the bottom of thestructures; this multiplies the computational effort by the numberof considered reflection events, compared to the costs for the com-putation of the direct flux.1 Also, the flux rates can easily vary byorders of magnitude along the structure depth; this increases the







142 P. Manstetten et al. / Solid-State Electronics 128 (2017) 141–147

number of particles necessary to obtain an acceptable signal-to-noise ratio when using a ray tracing approach. For spatial resolutionstypically desired for practical simulation cases, this leads to highcomputational costs for the full three-dimensional computation ofthe local neutral flux using Monte Carlo ray tracing or radiositybased methods.

We suggest to use a one-dimensional approximation for the cal-culation of the local neutral flux inside high aspect ratio structures.Our approach, initially introduced in [5], is radiosity based and isapplicable to simulations of convex rotationally symmetric holesand convex symmetric trenches with a constant cross-section.

The adsorption of the neutral particles is modeled with a stick-ing probability s as a locally constant parameter of the surface. Allsources and reflections are treated as ideal diffusive, which is acommon assumption for neutral particles [6]. Molecular flow (bal-listic transport) is assumed for the neutral particles. The sum ofthese assumptions allows for the computation of the neutral fluxdistribution using a radiosity approach, which was originally usedin the context of heat transfer [7] and later adopted in computergraphics to compute global illumination [8].

The surface of the structure is discretized into elements alongthe line of symmetry. Assuming a constant flux and a constantsticking probability s over each surface element, we reformulatethe discrete radiosity equation to obtain a receiving perspective,which allows for fully adsorbing surface elements.

We establish a general formulation to compute the view factorbetween two elements of a convex rotationally symmetric hole,based on a formula for the view factor between two coaxial disksof unequal radius. The view factors between two elements of aconvex symmetric trench with a constant cross-section is derivedusing the crossed-strings method [7].

The framework is validated using a three-dimensional MonteCarlo ray tracing based simulator [9] by comparing results for dif-ferent aspect ratios and sticking probabilities. Furthermore, westudy the influence of geometric variations along the wall, as wellas the variations of the particle sticking probability, on the fluxdistribution.

Kokkoris et al. [6] also proposed a framework to approximatethe neutral flux in long trenches and holes by exploiting symmetryproperties of the structures: The three-dimensional problem isreduced to a line integral and the Nyström method [10] is usedfor discretization, where a special numerical treatment is neededto avoid singularities. Spikes and oscillations of the solution nearcorners of the structure were reported, when the resolution isnot refined (compared to the resolution required by the Nyströmmethod) at these critical spots. Assumptions for the neutral flux,which are the same for our framework, are the ideal diffusesources/reflections, the locally constant sticking probability, andmolecular flow (ballistic transport without considering inter-particle collisions) of the neutral particles.

In the following sections we first define the simulation domainand introduce the surface model (Section 2). Then, we derive thereceiving perspective for the discrete radiosity equation (Section 3)and describe the computation of the view factors for holes andtrenches (Section 4). Finally, we present the results of the valida-tion and the effects of geometric variations on the wall (Section 5).

2. Simulation domain

For cylindrical holes, the simulation domain is a rotationallysymmetric closed convex surface. For trenches, the simulationdomain is a trench with a closed convex symmetric cross-section.The neutral flux source is modeled by closing the structures at thetop. This leads to a disk-shaped source and a strip-shaped sourcefor holes and trenches, respectively. Fig. 1a and b illustrates the

cross-sections of domains with vertical walls and with a kink atone half of the depth, respectively.

The surface adsorption is modeled using a locally constantsticking probability s. The received flux R is split according to s intoan adsorbed flux A and a re-emitted flux RE as depicted in Fig. 1c.Source areas additionally emit flux E independent of R.

For the remainder of this work, a sticking probability ss ¼ 1 isused for source areas which to not have any reflections originatingfrom these artificial areas; the bottom is modeled as a fully adsorb-ing area with a sticking probability sb ¼ 1. A constant stickingprobability sw is used for the walls of the structures. These choicesrepresent a reasonable approximation to the prevalent conditionsfor the neutral particles in an IECE environment.

3. Radiosity equation

Our assumptions, particularly that all sources and surfaces areideal diffuse and that the transport of the neutral particles is ballis-tic, allows for the use of a radiosity formulation.

By assuming a constant flux and a constant sticking probabilityover each surface element, the problem can be formulated usingthe discrete radiosity equation: for a surface element i the equationreads

Bi ¼ Ei þ ð1� aiÞX

j

ðFjiBjÞ; ð1Þ

where B is the radiosity (sum of emitted and reflected energies), E isthe self-emitted energy, a is the absorptance, and Fji is the view fac-tor (proportion of the radiated energy, which leaves element j and isreceived by element i). We adapt (1) to our problem by substitutingthe absorptance awith the sticking probability s and identifying theadsorbed flux as the adsorbed energy A. The radiosity B is thenrelated to the adsorbed energy A by

Ai ¼ ðBi � EiÞ si1� si

: ð2Þ

Since we are also interested in the adsorbed flux at the fully adsorb-ing areas, (1) and (2) are not applicable because limsi!1 Ai ¼ 1. Forthis reason we use the following formulation for the received flux R:

Ri ¼X

j

ðEjFjiÞ þX

j

ðð1� sjÞRjFjiÞ; ð3Þ

where the relation to the adsorbed flux is

Ai ¼ Risi: ð4Þ

Rewritten in matrix notation and resolved for the vector of thereceived flux R we obtain

FT � Eþ diagð1� sÞFT � R ¼ R;

ðI� diagð1� sÞFTÞ � R ¼ FT � E; ð5Þ

with the vector of emitted flux E, a vector of sticking probabilities s,and a matrix of view factors F (where Fij corresponds to the viewfactor i ! j).

We approximate the solution of the resulting diagonally-dominant linear system of Eq. (5) using the Jacobi method. Eachiteration of the Jacobi method can be imagined as a concurrent dif-fuse re-emission of each element to all other elements. Theadsorbed flux A is obtained by multiplying the entries in the solu-tion for R with the corresponding sticking probability s of the ele-ment (4). The relation kAk � kEk ¼ 0, which holds for closedsurfaces, can be used to test the implementation and to define astopping criterion for the Jacobi iterations.

(a) Vertical (b) Kink (c) Surf.Model

Fig. 1. Cross-sections of simulation domains with vertical walls (a) and with a kinkat one half of the depth (b). ss ; sw , and sb designate the sticking probabilities for thesource, the wall, and bottom region, respectively. (c) Illustrates the surface modelshowing the relation between the received flux R, the adsorbed flux A, and the re-emitted flux RE; source areas emit flux E independent of the received flux R.

Fig. 3. Isometric (a) and side view (b) on the four infinite strips which correspondto the surface elements a and b from Fig. 2a. In (b), the view factors from the topright strip ar towards the other three strips are visualized.

(a) Cone/Cone (b) Cone/Annulus (c) Cone/Disk

Fig. 4. Three possible pairs of segments as they result from discretizing the hole.For each pair, the near apertures an and bn , and the far apertures af and bf aredenoted. (a) Two cone-like segments. (b) Cone and annulus. (c) Cone and disk. Thefar aperture is treated as an infinitely small element.

P. Manstetten et al. / Solid-State Electronics 128 (2017) 141–147 143

4. View factors

Our approach is based on a discretization of the surface into dis-crete surface elements along the structure’s line of symmetry.Fig. 2 shows the cross-section of a convex structure and the shapeof the resulting surface elements. Two vertical ranges are indicatedin Fig. 2b and the resulting surface elements a and b are shown fora trench (Fig. 2a) and a hole (Fig. 2c). The elements are formed fromtwo strips for the trench and take the form of a sliced cone for thehole.

To assemble the matrix F we need to evaluate the view factorsbetween all possible pairs of surface elements.

4.1. Trench view factors

The view factor between two segments of a symmetric convextrench with a constant cross section, as depicted in Fig. 2a, isderived using the crossed-strings method [7]. This method com-putes the view factor between two surfaces with a constant crosssection and infinite length utilizing a two-dimensional re-formulation of the problem. For two mutually completely visiblestrips of infinite length the view factor is [7]

F1!2 ¼ ðd1 þ d2Þ � ðs1 þ s2Þ2 � a1 ; ð6Þ

where d1 and d2 denote the lengths of the diagonals when connect-ing the cross-section of the two strips to form a convex quadrilat-eral, s1 and s2 denote the lengths of the sides of that quadrilateralwhich connects the strips, and a1 denotes the length of the side ofthe quadrilateral which represents the emitting strip.

Fig. 3a is an isometric view of the four strips from Fig. 2a. Theview factors from the top right strip ar towards the other three

(a) Trench (b) Domain (c) Hole

Fig. 2. Two surface elements, which result when discretizing the domain (b) aredisplayed: (a) is the side view of two surface elements a and b, which result from atrench discretization and (c) is the isometric view of two surface elements a and b,which result form a hole discretization.

strips is visualized in Fig. 3b. The view factor between the two seg-ments a and b is

Fa!b ¼ Far!br þ Far!bl ; ð7Þwhere the subscripts denote the side of the strip according toFig. 3b. al can be neglected, as the cross section is symmetric. Theview factor of an element to itself is

Fa!a ¼ Far!al ; ð8Þwhere again the other direction can be neglected due to symmetry.Eq. (6) is used to compute the view factors between individualstrips in (7) and (8).

4.2. Hole view factors

We derive a general formulation to compute the view factorsbetween two segments of a rotationally symmetric convex holeas depicted in Fig. 2c. It is based on the view factor between twocoaxial disks of unequal radii r1 and r2 at a distance z defined by

F1!2 ¼ 12

X �ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

X2 � 4ðR1=R2Þ2q

� �

; ð9Þ

where Ri ¼ ri=z and X ¼ 1þ ð1þ R22Þ=R2

1 [11]. Using this relation andthe reciprocity theorem of view factors

S1 � F1!2 ¼ S2 � F2!1; ð10Þwhere S is the element area, we derive a general formulation for theview factor between the inner wall surfaces of two coaxial cone-likesegments whose surfaces are mutually completely visible. Fig. 4ashows two segments a and b in such a configuration and denotesthe four coaxial disks which represent the apertures of the twoelements.

In our formulation, the final goal to compute the view factorbetween two elements a and b is divided into multiple inexpensiveview factor computations between coaxial disks. First, the differ-ence of the view factors from bf towards the two disks of a is com-puted, and the reciprocity theorem (10) is applied to obtain Fabf

(red indicates sending and blue receiving areas):

Fig. 6. Normalized flux distributions along the wall and at the bottom for cylinders of as(circles) is compared to a three-dimensional ray tracing simulator (lines). The sticking prtracing and radiosity towards the wall-bottom interface are due to the resolution of the ramaximum along the cylinder radius, particularly visible for sw ¼ 0:2.

75% 112.5%125%width100%

vertical extended tapered kink

dept

h

1/2

dept

h

Fig. 5. Cross sections of the geometric variations of the wall for holes and trenches(shown for AR = 3). Starting from a vertical wall, the bottom width is increased by25% (extended) and reduced by 25% (tapered). Finally, the width at 1/2 of the totaldepth is increased by 12.5% to form a kink. The resulting angle a, which is identicalfor all three variations, is depicted.


ð11Þ

The same is done for bn to obtain Fabn :

ð12Þ

Finally Fab is obtained by subtracting Fabf from Fabn :

ð13Þ

The view factor of an element to itself Faa is computed by sub-tracting the flux which leaves through the two apertures fromunity:

pect ratio 5 (a, b) and aspect ratio 45 (c, d). Our one-dimensional radiosity approachobability of the wall sw is varied between 0.02 and 0.2. The deviations between rayy tracing simulator. In (c) the ray tracing results are plotted using the minimum and

Fig. 7. Normalized flux distributions along the wall and at the bottom of a hole and a trench of AR = 25 for sticking probabilities sw ¼ 0:2 (a, b) and sw ¼ 0:01 (c, d). Thegeometry of the structures is varied (according to Fig. 5). The results for structures with vertical sidewalls are plotted as a reference. Lines represent the results of thereference ray tracing simulator [9]. The deviations between ray tracing and radiosity towards the wall-bottom interface are due to the limited grid resolution of the raytracing simulator. The flux distributions at the bottom span the interval [0.75,0] for the tapered structures and [1.25,0] for the extended structures. In (c), the vertical dashedlines mark positions at 25% and 75% of the total depth as a reference for the results in Fig. 8.


Faa ¼ 1� Faan � Faaf : ð14ÞIf an element is an annulus or a disk (see Fig. 4b and c, respec-

tively), the general formulation still applies. For a disk, the far aper-ture is treated as an infinitely small element.

5. Results

To provide a good qualitative comparison we normalize theresults to only depend on the aspect ratio of the structure andthe sticking probability. The adsorbed flux A is divided by the areaof the element (Ai

n = Ai/Si) and normalized to the flux which asurface of the same sticking probability would absorb, if it is fullyplanar-exposed to the source (Ai

nsrc = Ain/Eisrc

n �Si).

The sticking probabilities of the source areas at the top ss andthe bottom of the structures sb are modeled as fully adsorbing inall of the following results.

5.1. Validation: cylindrical holes

To evaluate the quality of our one-dimensional radiosity model,we analyze different simulation setups of cylinders, where we varythe sticking probability of the wall between sw ¼ 0:02 and sw ¼ 0:2.Fig. 6a and b compares the flux distributions for structures whereAR ¼ 5 obtained using the proposed one-dimensional radiosityapproach with results generated with a reference Monte Carloray tracing tool [9]. Similarly, Fig. 6c and d compares the flux dis-tributions for structures where AR ¼ 45. The results show a goodagreement, aside from the deviation at the wall/bottom interface,

Fig. 8. Flux in a convex hole (a) and trench (b) (with tapered, extended, and kinked sidewalls) relative to the flux in a hole and a trench with vertical walls for an aspect ratio25 and a wall sticking probability sw ¼ 0:01. The flux at the bottom center and at two points on the wall (at 25% and 75% of the total depth) is plotted over the angle a(introduced in Fig. 5). The angle a corresponds to the taper angle (tapered), the extension angle (extended), and to the angle which is formed by a kink at one half of the totaldepth of the structure. The vertical dashed lines indicate an angle a ¼ 0:286� as a visual reference to the results in Fig. 7c.


caused by the discretization which is used in the ray tracing simu-lation. In Fig. 6c two flux distributions are plotted for the ray trac-ing results along the wall; they represent the minimum andmaximum along the cylinder radius. The separation of the flux dis-tributions, particularly visible for sw ¼ 0:2 (Fig. 6c), and the visiblenoise in Fig. 6d, reflect the stochastic nature of the ray tracingapproach.

5.2. Validation: convex structures

To validate our method for convex structures, several geometricvariations including an extended, tapered, and kinked sidewall,visualized in Fig. 5, are applied to a hole and a trench of aspect ratio25. Good agreement is achieved when comparing to the resultsobtained with a reference Monte Carlo ray tracing simulator.

Furthermore, the results allow to study the influence of the geo-metrical properties of high aspect ratio structures as well as of theparticle sticking probability on the neutral particle flux. Fig. 7 com-pares the resulting flux distributions along the wall and at the bot-tom for sticking probabilities sw ¼ 0:2 and sw ¼ 0:01. For a stickingprobability sw ¼ 0:2, Fig. 7a and b shows small variations along thewall and at the bottom for both, holes and trenches. Solely thepresence of the kink clearly increases the flux on the bottom halfof the wall.

When decreasing the sticking probability to sw ¼ 0:01, Fig. 7cindicates stronger deviations along the entire wall for all geome-tries. Fig. 7d reveals a variation of about �25% and �10% for thebottom flux in a hole and a trench, respectively.

To summarize, low sticking probabilities increase the influenceof geometric variations on the flux distributions along the wall, andespecially at the bottom of high aspect ratio structures.

5.3. Variation of wall geometries

Using our framework, the influence of the wall geometry on theflux distributions is studied in more detail using a hole and atrench of aspect ratio 25 with a wall sticking probabilitysw ¼ 0:01. For a ¼ 0:286�, this reassembles the configuration usedto produce the results in Fig. 7c and d. Fig. 8 compares the fluxat the bottom center and two points on the wall (at 25% and 75%of the depth) when additionally varying a (depicted in Fig. 5) from0� to 1�.

For the kinked structures, the angular dependence of the flux atall three positions can be approximated with a linear relation tothe flux in a structure with vertical sidewalls. The results for theextended and especially the tapered structures reveal the generallynon-linear relation already for small angles. Fig. 8a and b showsthat the kinked sidewall leads to higher flux rates at the bottom,compared to the extended configuration; the tapered configurationreduces the bottom flux.

When interpreting the results, it must be considered that thefully adsorbing bottom area changes its size when tapering orextending the structure. For a ¼ 1�, the bottom width/diameter isreduced to 13% and extended to 187%, for the tapered andextended structures, respectively. This is likely one reason why


the bottom flux is, at all angles, higher for the kinked structures,when comparing with the extended structures.

6. Summary and outlook

We provide an approximation of the local neutral flux in three-dimensional plasma etching simulations of high aspect ratio holesand trenches, using a one-dimensional radiosity approach. Theradiosity equation is reformulated into a receiving perspective,which allows to model fully adsorbing surface elements. Wecompute all relevant view factors for holes by establishing aninexpensive general formulation for the view factor betweencoaxial cone-like segments. Comparing the results for variousconvex configurations using a rigorous three-dimensional MonteCarlo ray tracing simulation good agreement is noted and theapplicability of our model for practical situations is confirmed.

We study the influence of geometric variations on the wall aswell as the sticking probability on the flux distributions. Theresults indicate a strong influence for low sticking probabilitieswhich are typical in IECE simulations of high aspect ratio struc-tures. The influence is studied in more detail for holes and trenchesusing a sticking probability sw ¼ 0:01 and an aspect ratio of 25. Theresults provide a compact overview on the magnitude of the fluxdeviation at different positions in the structure, when comparingto the idealized shape.

Our framework is based on a computationally inexpensive andstraightforwardly implementable method to compute the neutralflux distributions inside convex symmetric holes and convexsymmetric trenches of constant cross-section. It can be used as adrop-in replacement for the neural flux computation duringthree-dimensional IECE simulations of high aspect ratio structuresto significantly reduce simulation times in practical simulation

cases – or as a stand-alone tool which provides fast results forgeneral investigations.

Acknowledgments

The financial support by the Austrian Federal Ministry of Science,Research and Economy and the National Foundation for Research,Technology and Development is gratefully acknowledged.

References

[1] Dimitrakis P. Charge-trapping non-volatile memories. Basic and advanceddevices, vol. 1. Springer; 2015.

[2] Francis JPC, Chen F. Lecture notes on principles of plasma processing. Springer;2003.

[3] Ertl O, Selberherr S. Three-dimensional level set based bosch processsimulations using ray tracing for flux calculation. Microelectron Eng 2010;87(1):20–9.

[4] Ikeda T, Saito H, Kawai F, Hamada K, Ohmine T, Takada H, et al. Development ofSF6/O2/Si plasma etching topography simulation model using new fluxestimation method. In: Proceedings of the international conference onsimulation of semiconductor processes and devices (SISPAD). p. 115–8.

[5] Manstetten P, Filipovic L, Weinbub J, Hössinger A, Selberherr S. Using one-dimensional radiosity to model neutral particle flux in high aspect ratio holes.In: Joint international EUROSOI workshop and international conference onultimate integration on silicon (EUROSOI-ULIS). IEEE; 2016. p. 120–3.

[6] Kokkoris G, Boudouvis AG, Gogolides E. Integrated framework for the fluxcalculation of neutral species inside trenches and holes during plasma etching.J Vac Sci Technol A 2006;24(6):2008–20.

[7] Modest MF. Radiative heat transfer. Academic Press; 2013.[8] Philip D, Kavita B, Philippe B, Peter S. Advanced global illumination. AK Peters

Ltd; 2006.[9] Ertl O, Filipovic L, Weinbub J, Vienna TS; 2015. <https://github.com/viennats/

viennats-dev>.[10] Nyström EJ. Über die praktische Auflösung von Integralgleichungen mit

Anwendungen auf Randwertaufgaben. Acta Math 1930;54(1):185–204.[11] Howell JR, Menguc MP, Siegel R. Thermal radiation heat transfer. CRC Press;

2010.
























https://github.com/viennats/viennats-dev

https://github.com/viennats/viennats-dev









Tuning the tunneling probability by mechanical stress in Schottkybarrier based reconfigurable nanowire transistors


⇑ Corresponding author.E-mail address: [email protected] (T. Baldauf).

Tim Baldauf a,⇑, André Heinzig a, Jens Trommer b, Thomas Mikolajick a,b, Walter Michael Weber a,b

aCenter for Advancing Electronics Dresden (CfAED) and Chair of Nanoelectronic Materials, TU Dresden, GermanybNaMLab gGmbH, Dresden, Germany




Keywords:Silicon nanowireReconfigurable logicCMOSRFETSBFETTunnelingSchottky junctionStressStrainSymmetryDeformation potentialSelf-limited oxidationSimulationTCAD

a b s t r a c t

Mechanical stress is an established and important tool of the semiconductor industry to improve the per-formance of modern transistors. It is well understood for the enhancement of carrier mobility but ratherunexplored for the control of the tunneling probability for injection dominated research devices based ontunneling phenomena, such as tunnel FETs, resonant tunnel FETs and reconfigurable Schottky FETs. Inthis work, the effect of stress on the tunneling probability and overall transistor characteristics is studiedby three-dimensional device simulations in the example of reconfigurable silicon nanowire Schottky bar-rier transistors using two independently gated Schottky junctions. To this end, four different stresssources are investigated. The effects of mechanical stress on the average effective tunneling mass andon the multi-valley band structure applying the deformation potential theory are being considered.The transfer characteristics of strained transistors in n- and p-configuration and corresponding chargecarrier tunneling are analyzed with respect to the current ratio between electron and hole conduction.For the implementation of these devices into complementary circuits, the mandatory current ratio ofunity can be achieved by appropriate mechanical stress either by nanowire oxidation or the applicationof a stressed top layer.


1. Introduction

Reconfigurable nanowire (NW) transistors (RFETs) provide anincreased functionality of highly integrated circuits beyond classi-cal device scaling [1–3]. With its two independently gated Si-NiSi2 Schottky junctions (SJ) at source and drain side the RFETis able to work as either a n-FET or a p-FET device using the samephysical structure as defined by a programming voltage [4](Fig. 1). The flexible programming feature at runtime enablesthe synthesis of logic circuits and gates with lower transistorcount and reduced critical paths compared to CMOS based cir-cuits. For example a logic gate cell containing only six RFETscan be switched between full-swing complementary NAND andNOR functionality even giving an equal delay for both functions[5]. Compact XOR functions in a transmission gate configurationhave been proposed [6] and demonstrated [7] recently with onlyfour RFETs. The same cell with a different wiring serves as a 3

input majority (MAJ) gate. Since arithmetic operations can berealized efficiently with XOR and MAJ gates novel opportunitiesfor circuit design and design automation arise [6]. One-bit adderswith half of the device count compared to CMOS could be shownrecently [8]. Nevertheless, the drain currents of unstrained n- andp-RFETs with Si-NiSi2 junctions (barrier for electrons �0.66 eV, forholes �0.46 eV) are not per-se symmetric and thus do not satisfythe requirements for complementary circuit operation using adevice with identical geometry as n- and p-type transistor.Work-function/ band-offset tuning at the metal contacts orthrough doping is a difficult task in terms of variability at thenanometer-scale. In this work we employ mechanical stress tomodify the band structure of the semiconductor nanowire chan-nel yielding an effective mechanism to precisely adjust the sym-metry between n- and p-RFET without the need of doping oraltering the electrode material composition [9]. Process anddevice simulations were carried out with Sentaurus from Synop-sys (K-2015.06) to analyze the NW induced stress profiles and theresulting transfer characteristics of n- and p-programmed RFETs[10]. Effective masses are determined by band structure







Dra

in (

NiS

i 2)

Prog

ram

-Gat

e (T

i)

Nan

owir

e (S

i)

Oxi

de s

hell

(SiO

2)

Con

trol

-Gat

e (T

i)

Sour

ce (

NiS

i 2)

Longitudinal <110>

Horizontal

Vertical (100)

Scho

ttky

barr

ier

p-Type n-Type

on

off on

off

(a) (b)

Fig. 1. Schematic view of a reconfigurable silicon NW-RFET with two independently gated Schottky junctions at source and drain, (a) RFET structure (b) operation states.

T. Baldauf et al. / Solid-State Electronics 128 (2017) 148–154 149

calculations based on the empirical pseudopotential method [11].The induced mechanical stress was introduced by four differentapproaches as illustrated in Fig. 2. First, the self-limiting oxidationrepresents a reliable and uncomplicated way to form strong radialcompressive stress and will be described in detail. Moreover, thesimulated results could be verified by experimental data [12].Nevertheless, a high gate oxide thickness can be detrimental todevice performance, thus additional stressor vehicles are investi-gated: epitaxial stress from the silicidation of source/drain con-tacts, use of metal gate contacts with an intrinsic compressivestress and finally a tensile stressed top layer deposited on topof a geometrically optimized device.

The achieved results can also be applied to other type of devicesencompassing tunneling through a barrier in the on-state, such asany Schottky FETs and in certain transport mechanisms of resonanttunneling transistors [13].

(a)

(c)

Tensile Stress

Fig. 2. Simulated stress profiles of silicon nanowire junctions induced by several stress soof source/drain contacts, (c) compressively stressed metal gates and (d) tensile stressed lcase individually).

2. Mechanical stress of oxidized silicon NW

In the process simulation a 220 nm long and nearly 20 nm thickundoped silicon NW with a h1 1 0i channel direction and six facets(two times (1 0 0), four times (1 1 1)) was oxidized at 875 �C with10 slm O2 capturing the experimental structure reported in Ref.[12]. Note that the oxide reaction rate for (1 1 1) surfaces are 30–100% higher than for (1 0 0) resulting in an oval NW cross section.The appearing oxide has approximately twice the thickness versusthe consumed silicon leading to a strong volume expansion of thesilicon oxide shell and consequently giving a radial compressivestress in the silicon NW (Fig. 3). In addition, the stress modulatedreaction rate at the Si-SiO2 interfaces and the stress dependentoxygen diffusion in the tensile oxide shell cause a self-limitationof oxidation shown by the slightly saturating gate oxide thicknesswith increasing time in accordance with [14]. Both stress effects as

(b)

(d)

Compressive Stress

urces: (a) compressive stress from oxide shell, (b) tensile stress from the silicidationayer on top of the device. (Stress scale is normalized to the maximum value for each

-1.4

-1.2

-1

-0.8

-0.6

-0.4

-0.2

0

0

2

4

6

8

10

12

14

16

18

20

22

0 5 10 15 20 25

Str

ess a

vera

ge

(GP

a)

Th

ickn

ess

(nm

)

Oxidation time (min)

NanowireGate oxide

_long_hori_vert

Fig. 3. Simulated average thickness of silicon NW tsi, gate oxide thickness tox (left)and average stress values near the Schottky junction (right) versus oxidation time(875 �C, O2 = 10 slm). Initial values were tsi = 19 nm and tox = 1.5 nm (native oxide).

0

5

10

15

20

21.51

|I D| (

µA/µ

m)

|Vcg| (V)

Experiment strained

Simulation unstrained

Simulation strained

q·B,h

= 17 meV

Si-

NW

NiS

i 2

(sou

rce)

WNiSi2

EV

Si-

NW

NiS

i 2

(sou

rce)

dT

q·B,e

= -45 meV

EC

WNiSi2

mean stress values

vert = -1.23 GPa hori = -1.23 GPa long = -0.57 GPa

Fig. 4. Simulated and measured drain current of a nanowire device as a function ofthe control gate voltage Vcg normalized to the NW diameter. The program gatevoltage Vpg was 2 V to achieve ntype characteristics (blue) and �2 V to achieveptype characteristics (red). The drain voltage Vds was set to 2 V for n-type and �2 Vfor p-type, respectively. Simulations were performed for the unstrained case(dashed) and the case including stress after 25 min oxidation (solid). The insetshows a schematic view of strained and unstrained electron barrier (left) and holebarrier (right) at the source junction. In the insets the vertical axis is the energy, thehorizontal is the longitudinal distance to the metallurgic interface. (For interpre-tation of the references to colour in this figure legend, the reader is referred to theweb version of this article.)

150 T. Baldauf et al. / Solid-State Electronics 128 (2017) 148–154

well as the surface dependent oxidation rate are considered by theprocess simulator. The shown stress values of the three basic direc-tions (h1 1 0i longitudinal – channel direction, h0 0 1i vertical –wafer orientation, h1�10i horizontal – wafer flat) are simulatedwith the viscoelastic Maxwell model and are averaged over thecross-section near the Schottky interface. They increase roughlylinearly with the simulated oxidation time and are in a ratio of2:1 between the radial and the longitudinal direction.

3. Stressed Schottky barrier devices

Unstrained NW-RFETs with Si-NixSi1�x Schottky junctions arereported to have strongly asymmetric transfer characteristics forn- and p-type operation [4,7]. The disparities mainly arise fromdissimilar tunneling probabilities of electrons and holes. The sim-ulations of an unstrained structure with 12 nm NW thicknessand 8 nm gate oxide shell (after 25 min oxidation) show a ratioof 0.13 between the currents for the ntype and the ptype device(referred to as n/p ratio in the following). This is in accordance tothe results reported in Ref. [4]. By tuning the mechanical stressthe ratio could be enhanced to 1.20 nearly matching the experi-mental results with a ratio of 1.05 [12] (Fig. 4). The device simula-tion is based on drift-diffusion transport. Modified local-densityapproximation is used for quantum-mechanical confined carrierdistributions occurring at Si-SiO2 interface near the SJ. Also mobil-ity models like high-field degradation, surface scattering and stressdependent effective transport masses are considered even thoughno significant influence for short RFET devices emanates from themdue to the limitation of drain current by barrier tunneling. The car-rier injection at the SJ is computed with a nonlocal tunnelingmodel based on the approach presented in [15]. The included tun-neling probability based on Wentzel-Kramers-Brillouin (WKB)approximation can by written for example for the electrons as

CeðrÞ ¼ exp �2�h

Z r

0

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

2m�t;e

UB;e �WNiSi þ EcðxÞq

� �

s

dx

" #

; ð1:1Þ

where �h, m�t;e, UB;e, WNiSi and EcðxÞ are the reduced Planck constant,

the average effective tunneling mass as well as the barrier height forelectros, the NiSi2 workfunction and the conduction band edge,respectively. There are two important parameters controlling thetunneling probability which are depending on the mechanicalstress. One parameter is the band offset from the Fermi level ofthe injecting contact to the corresponding effective band edges EC

and EV. The other parameter is given by the average effective tun-neling mass of electronsm�

t;e and holesm�t;h, respectively. The impact

of both parameters is considered in the simulations.For determining the barrier heights UB,e and UB,h the NiSi2

workfunction was fixed at �4.73 eV related to the vacuum leveland the affinity of the corresponding band edges was calculatedwith the deformation potential theory of a multi-valley band struc-ture model [16]. Non-hydrostatic mechanical strain distorts thestrong symmetry of the silicon lattice and results in an energeticsplit between the subbands. Consequently, electrons and holesare re-distributed between lower or higher energy levels. Theweighted contribution of each sub-band is lumped into a singleeffective band shift DEc and DEV according to

DEc

kB � T300K¼ � ln

1nC

�X

nC

i¼1

exp�DEc;i

kB � T300K

� �

" #

ð1:2Þ

and

DEV

kB � T300K¼ � ln

1nV

�X

nV

i¼1

expDEV ;i

kB � T300K

� �

" #

: ð1:3Þ

In Eqs. (1.1) and (1.2) kB is the Boltzmann constant and n thenumber of sub-bands. This corresponds to an ideal Schottky barrierheight, neglecting for simplicity Fermi level pinning e.g. originatingfrom interface states such as metal induced gap states (MIGS). Notethat transport and tunneling is not individually calculated for eachsub-band, the simulator only considers the band edges.The appli-cation of compressive radial stress lowers Ec and thus the electronbarrier and the barrier width. As a consequence the tunnelingprobability increases. Conversely, the hole barrier increases andthe hole tunneling probability decreases (see inset of Fig. 4). Thistrend is consistent with band calculations with density functionaltheory [17]. The barrier heights for electrons and holes show anearly linear behavior with oxidation time. This originates fromthe linear stress increase with oxidation time and the direct depen-dence of the deformation potential (Fig. 5(a)).

The effective tunneling masses of electrons and holes have anexponential and direct influence on the tunneling probability into

-50

-40

-30

-20

-10

0

10

20

0 5 10 15 20 25

q·

(meV

)


higher barrier

lower barrier

0.2

0.25

0.3

0.35

0.4

0 5 10 15 20 25


elecronsholes

(a)

B,e

B,h

(b)

Fig. 5. Stress dependent parameters as function of oxidation time (a native oxide of 1.5 nm was assumed): (a) change of barrier height and (b) effective electron and holemass averaged over the corresponding subbands.


or out of the band and are derived from band bending around theconduction band minimum and valence band maximumwhere themost carriers are located. Therefore, the band structure of thestrained silicon was simulated with the empirical pseudopotentialmethod. Mechanical stress not only modulates the energy level ofthe sub-bands as described by the deformation potential it alsoeffects the band bending and thus the effective masses near thesub-band edges. However, this effect is much stronger for thevalence bands than for the conduction bands. The effective tunnel-ing masses of electrons and holes were calculated considering theharmonic average of the effective (tunneling) mass of each sub-band oriented perpendicular to the SJ while the sub-bands areweighed by their energy levels and density of states (DOS). Dueto the parabolic behavior and a negligible shear stress the DOSremains quite constant for all conduction subbands. Hence, the sig-nificant stress dependent change of the average effective tunnelingmass mainly arises from the energetic re-population of charge car-riers similar to the behavior of the barrier height. As an example, inthe case of the radial compressive stress from oxidation applied tothe h1 1 0i channel direction the light electron sub-bands in h0 0 1idirection having an effective mass of 0.19�m0 are lowered while theheavier sub-bands in the (1 1 0) plane with an effective mass of0.32�m0 are lifted. This increases the tunneling probability into orout of the h0 0 1i – sub-bands compared to the h1 0 0i – orh0 1 0i – sub-bands and hence decreases the average effective elec-tron tunneling mass (Fig. 5(b)). In contrast, the heavy hole band islifted while the light hole band is lowered resulting in an increasedaverage effective tunneling mass for holes. Moreover, mechanicalstress changes the DOS effective mass of the non-parabolic valencebands [18]. The resulting anisotropy of the effective masses is wellcharacterized for the two main hole bands at band edge and atroom temperature (26 meV). Fig. 6 shows the effective hole massin reciprocal space using spherical coordinates to visualize the dif-ferences between an unstrained silicon NW and a compressivelystrained NW by a 25 min oxidation step. The DOS effective massis calculated by the integration over all directions in k-space awayfrom the C-point (similar to Eq. (3) of [16]). The DOS effectivemasses at the energy level around the band edges are shown inFig. 6. Their values are comparable to the ones obtained in Ref. [18].

Using the stress-modulation from oxidation for NW RFETs thetransport characteristics of the gated SB should always be consid-ered in connection with the geometry of the device. Consequently,tsi and tox are determined by the oxidation time and have a directinfluence on the gate control. The effect is shown in Fig. 7 by then/p ratio of an unstrained device. A thinner gate oxide achieved

after short oxidation times allows a stronger band modulation inthe NW and promotes the tunneling through the higher electronbarrier. Therefore, the n/p ratio is increased. With the progressiveoxidation the ratio as determined by pure geometric and electro-static considerations decreases to 13%. This can be compensatedwith additional mechanical stress shown by the n/p ratio of thestrained device. For this combination of a NW with 19 nm initialdiameter and 1.5 nm initial native oxide we simulated a nearlyideal n/p ratio of 100% after 22 min oxidation time comparable tothe experimental result of 105%. Nanowires with a thinner initialtsi have a smaller volume to comply with the oxide growth andthus are more stressed after the same oxidation time. To decouplethe geometry from stress effects the device was simulated withand without stress dependent models to calculate a relative draincurrent change DID;strain according to:

DID;strain ¼ ID;strained � ID;unstrainedID;unstrained

ð1:4Þ

for n- and p-RFET as a function of oxidation time. The stress inducedcurrent amplification of the ntype transistors behaves supra-linearand rises up to approximately 400%. In contrast, p-type RFET oper-ation shows a degradation of up to �50%.

Both effects, barrier modulation and effective mass tuning,applied individually show comparable influences on the n/p rationand the corresponding drain current modulation DID,strain (Fig. 8,for 22 min oxidized NW). The impact of the barrier height is slightlyhigher than the one of effective tunneling mass most likely due tothe combination of the Schottky barrier height determined by theNiSi2workfunctionand the choice of silicon crystal orientation. Thuswith a different crystal orientation the stress depended modulationof the average effective tunneling mass could be weaker wherebythe influence of the barrier heightwould becomedominant. It is alsovisible that the combination of both effects has a higher/lowerimpact for the electrons/holes of the n-type/p-type than expectedfrom the linear superposition of the effects. This means that barrierheight and effective tunneling mass need to be considered at thesame time as the effects on the tunneling probability amplify ordiminish each-other under the influence of mechanical stress.

Furthermore, the influence of individual stress directions relatedto the definedNWorientationwas analyzed by separating the stresscomponents for h1 1 0i- aswell as h1 0 0i-NWs,which are also inter-esting in relation to top-down processes. Fig. 9 shows the drain cur-rent modulation of the n- and p-type RFET for modified radial andlongitudinal stress. The current of a h1 1 0i-NW is slightly moresensitive to the radial components than to the longitudinal one. It

Light hole band Heavy hole band

unst

rain

ed

stra

ined

(a)

(b) (c)

(d) (e)

Heavy hole band (26 meV)

mDOS,LH m61.0= DOS,HH = 0.47

mDOS,LH m32.0= DOS,HH = 0.22

Fig. 6. Simulated valence bands and hole effective masses. (a) isoenergy surface of heavy hole band at room temperature thermal energy (26 meV). (b) and (c) show theeffective masses of the heavy hole band (HH) and the light hole band (LH) at the band edge in unstrained silicon as a function of reciprocal space using spherical coordinates.(d) and (e) show the same for strained silicon (NWs oxidized for 25 min).

-25

0

25

50

75

100

125

-100

0

100

200

300

400

500

0 5 10 15 20 25

n/p

(%

)

I D,s

trai

n(%

)


IDpIDn

n/p unstrainedn/p strained

Fig. 7. Stress induced modulation of the drain current DID,strain (lines) and n/p ratioof strained and unstrained RFET structures (symbols) as a function of oxidationtime. Refer to Fig 3 for the thicknesses of the silicon NW the gate oxide thicknessand the stress values corresponding to the oxidation time.


can also be observed that the n/p ratio moves in favor of the n-RFETfor less compressive longitudinal stress. In other words, a tensilelongitudinal stress has the same benefit to adjust the drain currentsof n- andp-configuration as compressive radial stress. However, thisdoes not apply to h1 0 0i-NWs. Although the electron tunneling cur-rent behaves similar, the oxide stress increases the hole tunnelingcurrent as well. As the effects for n- and p- are not counteractingas for h1 1 0i, the adjustment of the n/p ratio is not possible. At last,for stress engineering it is crucial to apply a stress profile to thedevicewhere sub-bandswith low effectivemasses are energeticallypreferred, increasing the tunneling probability.

4. Other stress sources for silicon NWs

As mentioned above, a thick gate oxide with high radial stressreduces the gate control. Hence, other possible stress sources have

been investigated. As first alternative the epitaxial stress from thesilicidation of the source and drain contacts should be considered.In our experiments it could be observed that such a thin NW struc-ture promotes the formation of a very sharp silicon rich and cubicNiSi2 phase to silicon interface. It is known, that the lattice con-stant of NiSi2 along h1 1 1i is slightly smaller than that of siliconand hence an intrinsic tensile stress in the silicide region isexpected [19]. Results on the exact stress values are currentlynot available from experiments. Therefore, an estimated intrinsictensile stress of 500 MPa was assumed. In the process simulationit could be seen that this stress expands only through the first5 nm distance within the silicon NW beyond the metallurgic junc-tion and relaxes strongly which results in relatively low averagestress values within the tunneling region (Table 1). Thus, no largechanges in effective tunneling mass and band deformation occurleading to a slightly increased n/p ratio of 19% for a comparablestructure with 12 nm NW thickness and 8 nm gate oxide shell(after 25 min oxidation).

A further source of mechanical stress could be the top lying andomega shaped gate contact. Depending on the process conditions atensile or compressive stress can be imprinted [20]. Both variants,with +1.0 GPa and �1.0 GPa intrinsic gate stress, have been exam-ined. With the compressive gate material we could achieve animproved n/p ratio of 31%. The enhanced ratio results from theincreased effective tunneling mass of holes which only degradesthe p-type drain current and thus the device performance.

The most promising alternative is a stressed top layer above thecomplete gate stack structure. Silicon-nitride (Si3N4) is typicallyused for stress enhanced planar MOSFETs in industrial productionand can be deposited either with a compressive intrinsic stress upto 3.5 GPa or a tensile intrinsic stress up to 1.7 GPa [21,22]. Thatmakes this stress source universally applicable for use in othernano-scale transistor types having an energy barrier for tunnelingin the on-state and also for application to different crystal orienta-tions. First the effect of a tensile stressed top layer was analyzed forthe NW structure oxidized for 25 min. This already gave animproved the n/p ratio of 25%. Further stress penetration into the

n/p ration (%) ID,n (%) ID,p (%)

106.

1

40.7

35.0

0

20

40

60

80

100

120

DP+m*

DP

m*

366.

7

133.

3

110.

0

0

100

200

300

400

n-Type

-42.

9

-25.

5

-22.

1

-100

-80

-60

-40

-20

0

p-Type

(c)(b)(a)

Fig. 8. (a) n/p ratio and drain current modulation (DID,strain) for (b) n-type and (c) p-type devices caused by a 22 min oxidization in a RFET structures. The three bars show thedependency of the stress modulated effective tunneling mass only (m⁄), the deformation potential theory only (DP) and the combination of both methods (DP + m⁄).

-60

-40

-20

0

20

40

60

0

200

400

600

800

-0.75 -0.5 -0.25

I D,s

trai

n, p

-Typ

e (%

)

I D,s

trai

n, n

-Typ

e (%

)

long (GPa)

n-Type, <110>-NWn-Type, <100>-NWp-Type, <110>-NWp-Type, <100>-NW

-60

-40

-20

0

20

40

60

0

200

400

600

800

-1.25 -1 -0.75

I D,s

trai

n, p

-Typ

e (%

)

I D,s

trai

n, n

-Typ

e (%

)

hori = verti (GPa)

n-Type, <110>-NWn-Type, <100>-NWp-Type, <110>-NWp-Type, <100>-NW

(b)(a)

hori = verti = -1.0 GPa

long = -0.5 GPa

Fig. 9. Drain current modulation DID,strain of n-and p-type RFET depending on individual stress directions for h1 1 0i- and h1 0 0i-NWs. Base stress profile was given byrhori =rverti = �1.0 GPa and rlong = �0.5 GPa (similar to stress from oxidation). (a) Variation of longitudinal stress with constant radial stress. (b) Variation of radial stresswith constant longitudinal stress.

Table 1Overview of the simulated imprinted stress values, stress dependent effective masses and change of barrier height as well as n/p ratio (unstrained 0.13) for the four investigatedstress sources.

25 min oxidation(compressive)

NiSi2(tensile)

Metal-Gate(compressive)

Overlayer(tensile)

Overlayer (tensile) with optimizedstructure

rlong (GPa) �0.57 0.12 0.59 0.37 0.59rhori (GPa) �1.23 �0.09 �0.24 0.08 0.03rvert (GPa) �1.23 �0.08 0.41 �0.30 �0.31mt,e

* /mt,h* 0.22/0.34 0.25/0.31 0.28/0.52 0.21/0.27 0.21/0.30

q�DUB,e/q�DUB,h

(meV)�45/17 0/�1 8/�13 �8/�8 �11/�12

n/p 1.20 0.19 0.31 0.25 1.09

compressed gate part

longitudinal stress (Pa)

Fig. 10. 3D slice of the longitudinal stress profile of a gated SJ with tensile stressed (1.7 GPa) Si3N4 top layer: (a) 10 nm thick metal gate region. Compressive stress from theinterface between top layer and gate compensates the tensile stress originating from the sides of the gate resulting in an unstrained SJ. (b) 60 nm thick metal gate region. Thecompressive stress relaxes over the gate thickness and the SJ is mainly tensile strained in longitudinal direction. The effect is explored in the case of the NW RFET.



nanowire was improved by choosing a thinner gate oxide thicknessof only 2 nm. However, it was also necessary to adjust the thick-ness of the gate contact lying between the stressed top layer andthe SJ because the gate material directly at the interface to the ten-sile silicon-nitride becomes compressively stressed. This elimi-nates the tensile stress originating from the sides of the gateregion. Thus, for specific gate thicknesses the stress above the SJcan vanish (Fig. 10). This calls for a thicker gate layer to relax thecompressive component of the top side interface and to developthe tensile portion over the SJ. For the improved RFET structurewith the tensile stressed top layer we observed a n/p ratio of 1.09%.

5. Conclusion

Mechanical stress provides a flexible and dopant-free method toadjust drain currents in energy barrier based transistors. For recon-figurable FETs it allows to precisely tune the ratio between the cur-rent of the n and the ptype operation which is an importantrequirement to realize complementary circuits and to fully exploitfine-grain reconfigurability of circuits. A stress profile generated bythermal oxidation of the silicon NWwas used to describe the stressdependent multi-valley band structure and the average effectivetunneling mass as primary modifiable parameter of the currentinjection through the Schottky junctions. Furthermore, we couldshow the individual influence of both parameters as well as theamplifying impact of their combination. Moreover, the influenceof different stress directions on silicon NW structures withh1 0 0i- and h1 1 0i-orientation was investigated. With the oxidizedNW RFET we achieved a symmetric transfer characteristic betweenn- and pRFET, highly matching previous reported experimentalresults. As alternative to a thick gate oxide with inherent disadvan-tages for the electrostatics of the device we further examined themechanical stress formed by the silicidation of the source anddrain contacts, intrinsically stressed metal-gates and the applica-tion of a stressed silicon-nitride overlayer. The tensile overlay incombination with an improved structure seems to be a promisingapproach for current VLSI technologies providing the applicabilityof this method in conventional top-down process flows. In sum-mary, mechanical stress is a versatile tool to tune electron and holeconduction in devices based on different barrier tunneling mecha-nisms such as RFETs with potential use in resonant tunneling tran-sistors and band-to-band tunneling devices (TFETs) [23].

Acknowledgment

Parts of this work are supported by ‘‘Deutsche Forschungs-Gemeinschaft (DFG)” in the project ReproNano (MI 1247/6-2 andWE 4853/1-2) and the Cluster of Excellence ‘CfAED’.

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Reconfigurable field effect transistor for advanced CMOS: Advantagesand limitations


⇑ Corresponding author.E-mail address: [email protected] (C. Navarro).

C. Navarro ⇑, S. Barraud, S. Martinie, J. Lacord, M.-A. Jaud, M. VinetCEA-LETI, Minatec Campus, F-38054 Grenoble, France




Keywords:FDSOIReconfigurable FETPolarity gateReversible FETRFETSchottky barrier

a b s t r a c t

Reconfigurable FETs (RFETs) are optimized in planar Fully Depleted (FD) SOI. Their basics, electrostaticsand performance are studied and compared with standard 28 nm FDSOI and other RFETs results in theliterature. The main challenge for future broad adoption is analyzed and commented. Finally, some tipsto improve the performance such as the asymmetric silicidation at source/drain are discussed.


1. Introduction similar logic functions. On the other hand, the presence of the PGs

For more than 40 years CMOS technology has followed an inces-sant scaling, i.e. transistors shrinking, tracking the Moore’s Law [1].However, more recently, this trend has been slowed and iscurrently threatened for sub-10 nm [2]. The industry is thusresearching new device structures for future electronics thatenable continued CMOS scaling. Many different competitors havebeen proposed: Trigate FETs [3], Tunneling FETs [4] or stackednanowires [5] for example. Reconfigurable FETs, RFETs [6], standas an interesting option to reduce the number of devices in futurecircuits thanks to their reprogrammable operation.

RFETs feature metallic (typically nickel silicides as NiSi [6])source and drain (S/D) regions, where both type of carriers are ableto move freely. Together with a control gate (CG), responsible ofhandling the current flow as in MOSFETs, one or more additionalpolarity gates (PG) are employed to deal with the S/D-bodySchottky barriers (SB). The goal of these PGs is to suppress theambipolar current in SB MOSFETs during the OFF state. This config-uration allows to in-situ switch from N to P-like FETs by selectingwhich carrier is injected by tunneling. The RFET main advantagesare: (i) no doping required for S/D regions (no random dopant fluc-tuations), (ii) fewer fabrication steps and lower thermal budget(no S/D implantation, epitaxy or dopant activation), (iii) reversibleoperation and (iv) possible reduction in the number of devices for

make RFETs to present larger layout designs (up to 3 times bigger),more complex routing and increased capacitances. Furthermore,the signaling associated to these polarity gates requires extracircuitry in the design. Finally, the silicide-silicon junction qualityneeds to be well-controlled to avoid defects leading to fermi-level pinning [7], thus to unexpected silicide effective workfunc-tions and current asymmetries between N/P RFETs.

In this paper we optimized different planar Fully Depleted (FD)SOI RFET structures (Fig. 1a–c), we select the best among them andwe realized a native benchmark with FDSOI MOSFETs (Fig. 1d)using the same 28 nm technology. The following section describesthe basics in the operation of reconfigurable FETs, in particular, forthe three top-gates (3G) structure. In Section 3, we discuss aboutthe contrasts between the different RFET structures in Fig. 1a–c.We also document the reason of choosing the 3G-RFET as the bestcandidate to compare with typical FDSOI MOSFETs. Section 4 isdedicated to the native benchmark with respect to FDSOI MOSFETin terms of isolated device and logic inverter performance. In Sec-tion 5, we compare our results with those available in the literatureand comment on the differences between them. Some tips andideas to improve the RFET performance are given in Section 6.Finally, the last section is devoted to the conclusions.

2. Reconfigurable FET basics

The metallic S/D regions ensure the availability of both holesand electrons when required. The current in RFETs, as in SB







Fig. 1. (a) 1-Gate, (b) 2-Gates and (c) 3-Gates planar RFET structures compared to(d) 28 nm FDSOI featuring same gate-stack and films thicknesses. S/D regions aremetallic (silicides) in RFETs while highly doped Silicon is used in FDSOI. CG = con-trol gate, PG = polarity gate and GP = ground plane.

156 C. Navarro et al. / Solid-State Electronics 128 (2017) 155–162

MOSFETs [8,9], is due to both thermionic and field emission, that is,the contribution of carriers with sufficient energy to surmount theSchottky barrier or able to tunnel through it, respectively. Since theS/D metal workfunction is not exactly aligned with the Siliconenergy of conduction (valence) bands, the injection of electrons(holes) in the channel by thermionic emission is very limited. Thus,RFETs require the modulation of the SB thickness to enhance thecurrent by tunneling, especially at the source side.

In SB MOSFETs the S/D workfunction is clearly located closer toone of the Silicon conduction or valence energy bands, hence favor-ing the injection of one of the carriers over the other. However,since N/P RFETs are identical (no individual aspect ratio or conduc-tion booster may be applied) they must feature symmetric N/P cur-rent by default. Thus, the electron/hole currents need to be adjustedby tuning the conduction properties and especially the electron andhole SB height. Typically, this implies the use of S/D workfunctionsclose to the Silicon mid-gap (US=D � vSi þ Eg=2 � 4:61 eV). The dif-ferent effective masses and carriers mobilities between electronand holes may motivate slight workfunction deviations from mid-gap to achieve full current symmetry. Setting the silicides work-function close to mid-gap will be finally responsible of the verylow RFET output currents and limited performance as will be dis-cussed later.

In case of the 3G-RFET (Fig. 1c), the modulation of the Schottkybarriers is managed by the two lateral PGs, as seen in Fig. 2 for lowdrain voltage (VDS � 0 V). As observed, the energy barrier

Fig. 2. Simplified front-channel energy bands diagram for the 3G RFET at VDS � 0 V.(a) N-type (VPG ¼ þ2 V) and (b) P-type operation (VPG ¼ �2 V) in OFF-state and ON-state. The PGs select the carrier that is allowed to tunnel while the CG controls thecurrent flow (ON/OFF) from source to drain as in typical MOSFETs.

thickness, related to the carrier tunneling transmission, can be con-trolled thanks to the PG voltage applied with respect to S/D. Posi-tives PG biases enable electrons to tunnel from the metallic sourceto the conduction band (Fig. 2a) while negative voltages do thesame for holes toward the valence band (Fig. 2b). This carrier injec-tion is more efficient closer to the front-channel where the electro-static control induced by the polarity gates permits a sharperenergy band bending. Meanwhile, the control gate (CG) is respon-sible of regulating the current flow by inducing (OFF state) or not(ON state) an energy barrier in the middle of the channel. The oper-ation of the two gate (2G) RFET is similar but the CG is also respon-sible of governing one of the Schottky barriers which may increasethe OFF-state current. In planar RFETs, the use of the ground plane(GP) is only mandatory in case of the one top-gate (1G) RFET struc-ture, where it may act as PG or CG depending on the role of the top-gate.

3. Planar FDSOI multi-gate RFETs

All three RFET structures from Fig. 1a–c were at first simulatedusing Synopsys TCAD [10] in 2D to discern the best aspirant tocompare with FDSOI MOSFETs. The Wentzel Kramers Brillouin(WKB) model was employed as an approximation for the quantumtunneling. This model has proven to be consistent with experimen-tal results as shown in [6]. RFET structures feature 25 nm BOXthickness, 10 nm SOI layer and equivalent oxide thickness of1.4 nm. All top gates length and their spacing are fixed to 30 nm.The top-gates overlapping with the silicide is set to 15 nm. Thefinal silicon film length depends on the number of top-gates, being45/60/120 nm for the 1G/2G/3G planar RFETs, respectively. All top-gates and S/D workfunctions are initially settled to align at Siliconmid-gap (4.61 eV). The PG are fixed to ±2 V to establish the N or Pbehavior. A constant VDS ¼ �1 V is applied while the control gate isswept from�2 to +2 V. The GP remains always grounded for the 2Gand 3G-RFETs but for the 1G-RFET it operates as PG. The width isfixed to 1 lm in all structures. Reducing the width in planar RFETsyields lower currents due to the lower area at the SB junctionwhere tunneling occurs. In a real circuit, the width scaling may alsoimpact the design since the routing becomes more complex.

The comparison of the transfer characteristics is illustrated inFig. 3. As expected, the devices operate either in N or P modedepending on the PG biasing conditions. The main electrostaticresults are summarized in Table 1. The N-RFET ON current is sys-tematically higher than in P-RFET. The lower hole effective mass(m�

n ¼ 0:3m0 andm�p ¼ 0:2m0, chosen as in [11]) does not compen-

sate the lower hole mobility when the SB heights are symmetric(mid-gap), thus larger silicides workfunction (>4.61 eV) arerequired to achieve N/P current symmetry. Three main contrasts

Fig. 3. Simulated IDðVCGÞ transfer characteristics for different RFET structures with1,2 and 3 top-gates (Fig. 1a–c). VPG ¼ �2 V, VDS ¼ �1 V, VBG ¼ 0 V (2G and 3G),VBG ¼ VPG (1G). US=D ¼ UCG=PG ¼ 4:61 eV. LCG=PG ¼ 30 nm, EOT ¼ 1:4 nm, TSOI ¼ 10 nmand TBOX ¼ 25 nm. W ¼ 1 lm.

Table 1Preliminary simulations of planar RFET for different number of top gates. VBG ¼ 0 V (2G and 3G), and VDS ¼ �1 V. VPG ¼ þ2 V (N-RFET) and VPG ¼ �2 V (P-RFET). VT ¼ VCG

(IDS ¼ 0:1 �W=LSi lA/lm), ION ¼ IDS (VCG ¼ VT � 0:65 V) and IOFF ¼ IDS (VCG ¼ VT � 0:35 V). SS extracted at 0:01 � IDS (VCG ¼ VT ). DIBL calculated as DVT=DVDS for VDS ¼ 1 V and0.05 V. US=D ¼ UCG=PG ¼ 4:61 eV, LCG=PG ¼ 30 nm, EOT � 1:4 nm, TSOI ¼ 10 nm and TBOX ¼ 25 nm.

– SS mV/dec DIBL mV/V ION lA/lm IOFF nA/lm ION=IOFF �105 A/A

1G P 145.4 – 24.3 12.4 0.016N 163.7 – 41.0 10.6 0.039

2G P 142.9 – 25.7 10.0 0.025N 154.5 – 46.6 8.4 0.055

3G P 79.2 37.5 18.6 0.009 1.91N 78.5 39.6 42.5 0.005 8.96

C. Navarro et al. / Solid-State Electronics 128 (2017) 155–162 157

can be discerned between the RFETs architectures: (i) the OFF statecurrent, is higher in the 1G-RFET. The CG is not able to adequatelysuppress the back-channel tunneling induced by the PG (groundplane). (ii) The maximum current is slightly lower for the 3G dueto the longer structure. (iii) The electrostatic control is boosted inthe 3G structure being the unique device with sub 100 mV/decSS (Subthreshold Swing) and larger ION/IOFF ratio. On the otherhand, the 3G architecture presents the larger layout design andmore complex routing among all architectures considered.

Based on the electrostatic and current ratio from the prelimi-nary results in Table 1, the 3G-RFET was finally selected as thestructure to be further optimized and benchmarked against28 nm FDSOI MOSFETs. The gates length, gates spacing, silicon filmthickness, PG overlapping with S/D and back-gate bias, amongother parameters, were tuned to see the impact on the electrostat-ics. For example the influence of the control gate length, LCG, in thecurrent characteristic is shown in Fig. 4a for a N-type 3G-RFET. Asthe CG is shortened, the electrostatic control over the channel isgradually lost which is reflected by the increase in the SS. On theother hand, making the CG larger slightly improves the SS but neg-

Fig. 4. IDðVCGÞ curves for different (a) control gate length and (b) spacing betweenthe polarity gate at the source side and the control gate (the other spacer at drainside remains fixed at 30 nm) for a N-type 3G-RFET. W ¼ 1 lm.

Fig. 5. (a) Optimized 3G-RFET and (b) 27 nm length FDSOI 2D structures usedduring TCAD simulations. The 1 lm silicon substrate is not represented.

atively affects the ON current simply because the device is longerand the lateral electric field decreases. The influence of the spacingbetween the PG at the source side and the CG is also illustrated,Fig. 4b. Longer spacers enable the development of an undesiredenergy barrier throughout the uncover gate region between thePG and the CG. This additional resistance significantly reducesthe current. In fact, the 3G-RFET can be considered as a tunnelingSchottky Barrier, which is the main physical mechanism limitingthe carrier transport, in series with channel resistance plus spacerresistance.

The final optimized 3G RFET (Fig. 5a) presents US=D ¼ 4:66 eV toachieve N/P current symmetry, mid-gap workfunction top-gatesUCG=PG ¼ 4:61 eV, N-type GP, EOT ¼ 1:55 nm, TSOI ¼ 6:5 nm, and

TBOX ¼ 25 nm. A 1 lm silicon substrate, ND ¼ 2 � 1018 cm�3, is con-sidered. The gate length is reduced down to LG ¼ 20 nm while theirspacing is shortened to LSP ¼ 15 nm. The overlapping of PGs withthe body decreases to 10 nm shrinking the 3G-RFET toLSOI ¼ 70 nm. The carriers mobility fits experimental 28 nm FDSOIresults at similar gate length [12] (constant mobility model with227/60 cm2 V�1 s�1 for electrons/holes).

On its side, the FDSOI MOSFET structure (Fig. 5b) used to bench-mark the 3G-RFETs exhibits the same vertical film architecture buta 15 nm epitaxy is carried out to raise the S/D regions and reducethe series resistance. The spacing between the CG and the doped S/D regions is fixed to LSP ¼ 9 nm. Two control gate lengths areprobed, 27 and 60 nm, adjusting the constant carrier mobility foreach length independently with experimental 28 nm FDSOI results[12] as for the 3G-RFET.

4. Optimized 3G-RFET vs. FDSOI

The comparison of the IDðVCGÞ curves between the optimized 3Greconfigurable FET and the FDSOI MOSFETs is depicted in Fig. 6.Table 2 shows the main electrostatic and current parameters atminimum and equivalent effective gate length for the 28 nmFDSOI. It can be observed how the RFET presents better electro-

Fig. 6. (a) P- and (b) N-type current comparison between optimized 3G-RFET andFDSOI devices. RFET LSOI ¼ 70 nm. FDSOI LSOI ¼ LG ¼ 27 nm. VBG ¼ 0 V. W ¼ 1 lm.

Table 2Optimized 3G-RFET vs. FDSOI benchmark in planar 28-FDSOI. VBG ¼ 0 V and VDS ¼ �1 V. VPG ¼ þ2 V (N-RFET) and VPG ¼ �2 V (P-RFET). VT ¼ VCG (IDS ¼ 0:1 �W=LSi lA/lm),ION ¼ IDS (VCG ¼ VT � 0:65 V) and IOFF ¼ IDS (VCG ¼ VT � 0:35 V). SS extracted at 0:01 � IDS (VCG ¼ VT ). DIBL calculated as DVT=DVDS for VDS ¼ 1 V and 0.05 V.

– SS mV/dec DIBL mV/V ION lA/lm IOFF nA/lm ION=IOFF � 105 A/A

3G RFET P 84 98 24.5 0.19 1.27N 84 94 22.2 0.20 1.11

27 nm FDSOI P 95 148 447 1.19 3.77N 94 136 1160 0.88 13.1

60 nm FDSOI P 71 37 309 0.03 117N 70 30 1020 0.02 518


static results, SS and DIBL, than the 27 nm long FDSOI. However,when the gate length is expanded to 60 nm, the FDSOI electrostaticis much better than for the reversible device. This fact suggests thatthe worse FDSOI electrostatic control at 27 nm length is comingfrom Short-Channel Effects [13] rather than any other factor.

The maximum drain currents at fixed supply voltage (VDD) arecompared in Fig. 7a. The reversible transistor values remain verylow but symmetric, being from 70 to 105 times lower comparedto the 27 nm length FDSOI devices. This reduction in the drain cur-rent is related to several aspects: (i) the low efficiency of the carrierinjection mechanism by tunneling (at the silicide/silicon junction),(ii) to the additional resistance induced by the spacers, uncovergate regions between PG and CG contacts, and (iii) to the reducedlateral electric field. Fig. 8 illustrates the top-interface (�0.5 nmaway from the front-gate oxide) energy bands for similar biasingconditions and effective gate length. The lateral electric field, i.e.slope of the energy bands, is weaker in RFETs which implies lowercarrier accelerations and less drain current. On the other hand, theON vs. OFF current figure of merit is depicted in Fig. 7b for several

Fig. 7. (a) Maximum drain current and (b) ION vs. IOFF figure of merit comparison for3G-RFET and FDSOI. VT ¼ VCG (IDS ¼ 0:1 �W=LSi lA/lm), ION ¼ IDS(VCG ¼ VT � 0:65 V) and IOFF ¼ IDS (VCG ¼ VT � 0:35 V). RFET LSOI ¼ 70 nm. FDSOILSOI ¼ LG ¼ 27 nm. VBG ¼ 0 V. W ¼ 1 lm.

Fig. 8. Horizontal (�0.5 nm from top-interface) N-MOS conduction and valenceenergy bands for (a) RFET and (b) FDSOI at similar length. VBG ¼ 0 V.

power supply voltages. Notice how in RFETs increasing VDD firstlyreduces the IOFF unlike in MOSFETs, where it monotonicallyincreases. This artifact comes due to the way the ON and OFF cur-rents are extracted based on fixed biasing (±2/3 V and �1/3 V,respectively) from the constant current threshold voltage [14]. Atlow VDD, the RFET VT is in the linear region due to the limited cur-rent and IOFF is very high. As VDD rises, the OFF current graduallymoves to the exponential region and decreases drastically. Forhigher VDD IOFF increases again as usual.

Concerning the capacitance analysis, the simpler case withVDS ¼ VBG ¼ 0 V is addressed due to the complex charge distribu-tion in the reconfigurable FET. In such case, the control gate capac-itances are compared in Fig. 9a for isolated devices. It can benoticed how the FDSOI CG capacitance is a bit larger simply dueto the thinner lateral spacers (LSP) in the structure. However, anddespite the thicker spacers, under normal conditions when a rever-sible transistor changes its polarity, the overall capacitance is stillhigher in RFETs due to the need of driving also the capacitanceassociated to the two additional polarity gates, Fig. 9b.

Mixed-mode 2D simulations [10] are now considered to studythe logic inverter response. An external load capacitance of 0.3 fFis connected at the inverter output to account for possible parasiticas in [15]. No other capacitances or resistances due to interconnec-tions have been accounted for. The voltage-transfer characteristics(VTC) of single stage inverters made with FDSOI and RFETs aredepicted in Fig. 10a. Both designs show the typical inverter opera-tion, the RFET configuration nonetheless presents a degraded VTC.Due to particular transport mechanism, the current variation inRFET is strongly different compared to FDSOI. The drain currentat high (N-RFET) or low (P-RFET) VCG is determined by the tunnel-ing barrier thickness rather than by the control gate-inducedenergy barrier. In fact, the first derivative of the IDðVDÞ has a super-linear variation and this effect strongly influences the voltage-transfer function of the RFET inverter. The transient response to asquare signal of 500 MHz is represented in Fig. 10b. The FDSOIinverter response clearly outraces the RFET. The rise, tLH , and fall,

Fig. 9. Capacitance benchmark for (a) control gate in isolated RFET and 27 nmFDSOI. (b) Single 3G RFET polarity-gate capacitance at different control gate biases.VDS ¼ 0 V and VBG ¼ 0 V. FDSOI/RFET WP ¼ WN ¼ 1 lm.

Fig. 10. Mixed-mode (a) voltage-transfer characteristics. (b) Transient response tosquare signal, f ¼ 500 MHz. Inset: RFET inverter with 0.3 fF output capacitance.FDSOI WP ¼ 2WN . RFET WP ¼ WN .

Fig. 12. (a) Energy per operation and (b) energy delay product comparison between27 nm FDSOI and 3G-RFETs. FDSOI WP ¼ 2WN . RFET WP ¼ WN ¼ 1 lm.


tHL, times are calculated as the crossing points at 50% of the supplyvoltage, VDD. These rise and fall times can be averaged to extractthe inverter propagation delay, sP , illustrated in Fig. 11a. Symmet-ric S/D silicided RFETs (circles, �) feature, at least (VDD ¼ 2 V), 70times larger delay than FDSOI (squares, �). The different RFETand FDSOI inverter delays we extract contrast with thoseemployed in [16] to compute the overall circuit delay in complexdesigns with the logical effort method [17]. The logical effortenables the calculation of the circuit delay normalized to the inver-ter delay for a given technology. In this work we show that thedelay is significantly higher in RFETs with respect to FDSOI, so,assuming both inverter delays identical, as done in [16], leads tomisleading results.

Fig. 11b shows the static inverter current against the delay fordifferent supply biases. The larger delays in reversible FETs areobtained at lower static current. FDSOI inverters are much fasterthan RFETs at the expense of larger static power. This however,does not directly imply reduced power consumption, the mainconsumption factors are related to the dynamic and the direct pathpower as will be commented later. The longer delays in RFET areinduced by the lower drain current, Fig. 7a, yielding high equiva-lent resistances [18]:

sP ¼ lnð2Þ � CL � R ð1Þwith CL being the total inverter load capacitance. This load capaci-tance may be extracted from Eq. (1) through the propagation delayand the equivalent resistance R. The resistance was approximatedusing the maximum currents (R ¼ VDS=IDS, with IDS from Fig. 7a).Values of CL ¼ 2:2 and 2.0 fF were obtained for FDSOI and RFETinverters, respectively. These capacitance values are in line withthe simulations results in Fig. 9. Once CL is determined, the dynamicenergy per transition, E, can be obtained by using [18]:

Fig. 11. (a) Inverter delay and (b) inverters static current vs. delay invertercomparison between 27 nm FDSOI (squares, �) and 3G-RFETs with symmetric,US ¼ UD , (circles, �) and asymmetric, US – UD , (triangles, D) S/D silicidations.FDSOI WP ¼ 2WN . RFET WP ¼ WN ¼ 1 lm.

E ¼ CL � V2DD ð2Þ

The energy is shown in Fig. 12a. Very similar energies areextracted for FDSOI and RFETs as a result of having comparableoutput load capacitances. As observed, the energy can be madearbitrarily low by reducing the supply voltage. From this perspec-tive, the optimum voltage to run the circuit would be the lowestpossible that still ensures functionality. This comes at expense ofthe delay, Fig. 11a. A more relevant metric combining the measureof consumption and performance is the energy delay product (EDP)[18], represented in Fig. 12b:

EDP ¼ E � sP ¼ CL � V2DD � sP ð3Þ

The optimum VDD to run the inverter is therefore the point forwhich the EDP becomes minimum. It turns out to be �1 V forFDSOI while for RFETs the optimum voltage is larger than the max-imum VDD considered, 2 V. In any case, we find a much lower EDPfor FDSOI technology than for any RFET configuration reflecting theclear superiority of FDSOI.

Speaking of the inverter power, Fig. 13 depicts the three mainconsumption components, PSta (static), PDyn (dynamic) and PDp

(power associated to the direct path current while N- and P-FETsare active) together with the total consumption, PTot . FDSOI MOS-FETs consumes from 10% to 18% more power than RFETs due tothe larger static current (Fig. 11b) and especially the slightly largerenergy per transition (Fig. 12a). However, this result needs to becarefully considered since the RFET scenario is optimum. The PGcapacitances are not driven reducing the total output capacitance,CL, hence the energy per transition, Eq. (2), and the dynamic andtotal consumption.

Fig. 13. Power consumption comparison between (a) 27 nm FDSOI and (b) 3G-RFETat f ¼ 500 MHz. PSta ¼ ISta � VDD (ISta = static current), PDyn ¼ E � f ; PDp ¼ IDp � VDD � f(IDp = time integrated direct path current) [18]. FDSOI WP ¼ 2WN . RFETWP ¼ WN ¼ 1 lm.

Table 3RFET simulated results from the literature. All devices but this work are nanowire shape. The symmetric silicides workfunctions, US=D , are extracted from the SB heights assumingvSi ¼ 4:05 eV and Eg ¼ 1:12 eV. The maximum currents are normalized to the nanowire perimeter.

– US=D eV m�n m0 m�

p m0 In�max lA/lm Ip�max lA/lm VD V VPG V VCG V

[19] 4.40 – – 636.0 636.0 1.2 1.2 1.2[20] 4.43 – – 2.1 – 2.6 1.5 2.5[11] 4.64 0.30 0.20 8.0 8.0 2.0 2.0 2.0[15] 4.46 0.19 0.16 636.0 636.0 1.2 1.2 1.2[16] 4.71 0.19 0.16 159.0 159.0 1.5 1.5 1.5

This work 4.66 0.30 0.20 37.5 37.5 2.0 2.0 2.0


5. State-of-the-art

The limited RFET drain current represents the main drawbackregarding the performance difference with FDSOI. In this section,we compare the current from all reconfigurable FETs simulationsand experimental results published so far. Table 3 gathers all TCADresults with the maximum currents for N/P RFETs, together withthe effective masses and S/D workfunction employed when speci-fied. In other simulation works, RFETs seem to provide very decentand symmetric current levels that could balance the performancewith typical MOSFETs. Two basic discrepancies appear betweenthe results obtained in this work and the best values in Table 3from EPFL [15,19]: (i) the huge maximum currents, over600 lA/lm (almost 20 times more), and (ii) the current symmetrygiven the different S/D silicides workfunction.

Initially, the high current level could be explained by the lightereffective masses. Fig. 14a illustrates the electron/hole maximumdrain current dependence with the effective masses for a planar3G-RFET structure. Lower masses improve the tunneling efficiency,thus enhancing the current. Nevertheless, the reduction in theeffective mass only yields a factor 2–3 in the current. A not veryfine mesh, with an arbitrary 50% enhancement in the tunnelingtransmission (parameters gc/gv [10]) and the field enhancementinduced by the improved confinement due to the 3D nanowirestructure (shorter screening length than in planar FDSOI) turn to

Fig. 14. a) Maximum N/P drain current as a function of the (a) effective mass(US=D � 4:66 eV) and (b) the S/D silicides workfunction (m�

n ¼ 0:3 m0 and m�p ¼ 0:2

m0) for the optimized 3G-RFET. VDS ¼ �2 V and VBG ¼ 0 V. W ¼ 1 lm.

Table 4RFET Experimental results from the literature. All devices are nanowire shape but [21] th

– US=D eV In�max lA/lm Ip�ma

[6] 4.40 636.0 6[21] 4.43 2.1[22] 4.64 8.0[23] 4.46 636.0 6[15] 4.71 159.0 1[24] 4.66 37.5

be the responsible of this current difference. This scenario reflectsa rather too optimistic case with beneficial strain for both carrierssimultaneously, which has yet to be proven experimentally [25],and induce an unrealistic current gain of around 5 to 15 times thatcombines with the effective mass impact. In any case, the use ofideal models during simulations, not considering parasitic effectsnear the interface between metal and semiconductor, may moti-vate too favorable currents with respect to experimental results.

Attending to the identical N/P currents in [15,19], they areobtained for US=D close to 4.4 eV, which leads to extremely asym-metric SB heights, 0.35/0.77 eV for electrons and holes, respec-tively. Fig. 14b illustrates the maximum drain current for N/P3G-RFETs as a function of the silicides workfunction. Thus, theselected barriers in [15,19] should typically lead to NFET currentsmuch larger than in PFET. Identical currents are extracted atUS=D � 4:66 eV yielding barriers height of 0.61/0.51 eV. The alsostrong currents from [16] are obtained thanks to the lower effec-tive mass, improved electrostatic when using a thinner EOT andthe shorter length. It is worth noting the strong impact the Schot-tky barrier height has on the current, being able to modulate it bymore than three orders of magnitude. Finally, simulations showhow by choosing mid-gap S/D workfunctions, the maximum N/PR-FET current drops by a factor 30, Fig. 14a. Hence, the N/P currentsymmetry goal imposes the fundamental performance boundary inRFETs.

On the other hand, experimental results are summarized inTable 4. Currents are consistently below 30 lA/lm validating ourweak simulated currents. Only devices from [15] show high draincurrents over 290 lA/lm, partly induced by the large polarity gatebiases used and by the fact that the current is not symmetric whichbenefits one of the N/P branches.

6. RFET enhancement tips

This section provides some ideas to improve the operation ofRFETs.Three main advises are commented now in order to increasethe drain current:

1. Lower the effective mass to improve tunneling efficiency byapplying strain boost techniques.

2. Use compound materials to reduce the semiconductor energyband-gap, thus the electron/hole SB heights.

at is FDSOI tri-gate with thick BOX (145 nm).

x lA/lm VD V VPG V VCG V

36.0 1.2 1.2 1.2– 2.6 1.5 2.58.0 2.0 2.0 2.036.0 1.2 1.2 1.259.0 1.5 1.5 1.537.5 2.0 2.0 2.0

Table 53G-RFET simulations to improve the current by reducing the energy band-gap, using asymmetric S/D workfunctions and low ering the effective mass. VDS ¼ �1:0 V.

Eg eV v0 eV US eV UD eV m�n m0 m�

p m0 In�max lA=lm Ip�max lA=lm

1.12 4.05 4.66 4.66 0.30 0.20 28.1 30.80.99 4.035 4.66 4.66 0.30 0.20 23.3 234.61.12 4.05 4.50 4.87 0.30 0.20 130.8 142.71.12 4.05 4.66 4.66 0.19 0.16 92.6 51.41.12 4.05 4.50 4.87 0.19 0.16 277.1 182.90.99 4.035 4.50 4.87 0.19 0.16 235.8 606.8


3. Use different silicides at S/D to obtain asymmetric workfunc-tions, each of them favoring the tunneling of one type of carrier(tipically U < Eg=2 eV for electrons and U > Eg=2 eV for holes).

Table 5 compares the current at each case independently andwith all enhancing factors at the same time. The selected valuesfor band-gap, workfunctions and effective masses are not arbitrary.The 0.99 eV band-gap corresponds to SiGe with 30% Ge(v0 � 4:035 eV) [26], the silicides workfunctions to PtSi(U � 4:87 eV) and TiSi2 (U � 4:5 eV) [27] and the lower effectivemasses are commonly used as default values [15,16]. All of thesemodifications independently enhance the current.

Using SiGe slightly deteriorates (18%) the electron current sincethe electron affinity is smaller which leads to an electron SB heighta bit larger (�0.015 eV higher). This could be solved by readjustingthe S/D workfunction to mid-gap though. On the other hand, SiGeis extremely beneficial for the P-RFET current, the lower affinitycombines with the smaller band-gap and reduce the hole SB height(�0.135 eV less), hence huge current improvements (760%) areachieved. The asymmetric boost of SiGe demonstrates that usingdifferent band-gap materials can be interesting to balance the cur-rent between N/P RFETs.

The asymmetric silicidation at source and drain is even moreinteresting since it may be beneficial for both N and P configura-tions. The simulated workfunctions were selected based onFig. 14b to maintain similar electron/hole current, Fig. 15a. Theenhancement is close to a factor 4.7. Even more dissimilar silicida-tions could be employed but the transfer characteristics is rapidlydegraded as shown in Fig. 15b. Increasing (reducing) the workfunc-tion for holes (electrons) boosts the maximum currents at theexpense of the off current and electrostatic control due to theincrease in the thermionic emission. As the S/D metallic fermi levelapproaches the valence or conduction energy band, less energy isrequired to surmount the energy barrier and more carriers areinjected in the body from the source. The direct consequence ofusing this asymmetric silicidation is observed in Figs. 11 and 12(triangles, D) where the delay and EDP are reduced with respectto the symmetric RFET configuration (circles, �) by a factor

Fig. 15. Transfer characteristics for asymmetric silicidated RFET (US – UD) with (a)similar output current and (b) similar electron/hole SB heights. VDS ¼ �2 V.W ¼ 1 lm.

between 3 and 30 times. The problem is still the degraded electro-statics and the possible implementation in actual and more com-plex circuits.

Finally, lightweight effective masses provide a gain of around1.6–3, being stronger for N-RFET since the drop in the mass is lar-ger. By combining all the boosters, the current may rise up to 20times (as in the case for P-RFETs). This impressive enhancementis however not sufficient to compensate the large delay differencewith MOSFETs, especially if we account for the degradation of theelectrostatics and inverter VTC characteristics.

7. Conclusions

Reconfigurable FETs provide, in theory, an interesting scenarioto build reprogrammable logic. They represent a powerful tool toreduce the number of devices, the critical paths and allowingXOR based circuits, which are inefficient in CMOS. However, inpractice, their poor performance compared to typical MOSFETsthreatens their broad adoption in future applications. The mainRFET asset, which is the N/P operation switch in the same device,becomes also their fundamental drawback. The simultaneousenhancement of both electron and hole currents is very challeng-ing and a tradeoff appears between N- and P-RFETs performance.

Aspects like the increasing surface due to the extra gates andthe associated circuitry to control the polarity gates, the risingrouting complexity and the control of the SB quality also jeopar-dize the possible benefits of reducing the total number of transis-tors in a circuit design. In any case, the global RFET performance isnot expected to equal the one from MOSFETs, thus limiting RFETsfor embedded or not very demanding applications.

Acknowledgements

Project supported by the French ANR via Carnot funding.

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Simulation study of a novel 3D SPAD pixel in an advanced FD-SOItechnology


⇑ Corresponding author.E-mail address: [email protected] (M.M. Vignetti).

1 Early Stage Researcher supported by the 2012-FP7-ITN, n� 317446, INFIERI EUprogram.

M.M. Vignetti a,⇑,1, F. Calmon a, P. Lesieur a, A. Savoy-Navarro b

a Institut des Nanotechnologies de Lyon, Université de Lyon, Franceb Laboratoire d’AstroParticule et Cosmologie, Université Paris-Diderot, Paris, France




Keywords:3D pixelAPDSPADSOIFDSOIGeiger-modeAvalanche diodeTCAD simulationsBack-side illuminationAvalanche triggering probabilityDark count ratePhoton detection probabilityTime-of-flight applications

a b s t r a c t

In this paper, a novel SPAD architecture implemented in a Fully-Depleted Silicon-On-Insulator (SOI)CMOS technology is presented. Thanks to its intrinsic vertical 3D structure, the proposed solution isexpected to allow further scaling of the pixel size while ensuring high fill factors. Moreover the pixeland the detector electronics can benefit of the well-known advantages brought by SOI technology withrespect to bulk CMOS, such as higher speed and lower power consumption. TCAD simulations basedon realistic process parameters and dedicated post-processing analysis are carried out in order to opti-mize and validate the avalanche diode architecture for an optimal electric field distribution in the devicebut also to extract the main parameters of the SPAD, such as the breakdown voltage, the avalanche trig-gering probability, the dark count rate and the photon detection probability. A comparison between theefficiency in back-side and front-side approaches is carried out with a particular focus on time-of-flightapplications.


1. Introduction

There are manifold areas of research and commercial applica-tions where Single-Photon Avalanche Diodes (SPADs, or Geiger-mode avalanche diodes) have been extensively studied and suc-cessfully implemented for the detection of weak optical signalsin the visible and near-infrared spectrum range [1]. Moreover, dur-ing the last few years, there has been an active research on theimplementation of SPADs in the field of High Energy Physics andMedical Physics for the detection of ionizing particles [2], openingnew promising fields of application for these devices.

A SPAD consists of a p-n junction which is reverse biased abovethe breakdown voltage Vbd by an excess bias Vex. When anelectron-hole pair (EHP) is generated in the space charge region(SCR) of the junction (e.g. by an incoming photon, ionizing parti-cle), a self-sustained charge multiplication process by impact ion-

ization could be triggering according to a certain probability(depending on the applied reverse bias), giving rise to a macro-scopic electric current. Such a high current usually translates intoa high current density which could cause permanent damage inthe device. For this reason, every SPAD pixel needs suitable‘‘quenching” electronics responsible for interrupting the multipli-cation process right after the avalanche build-up by promptly low-ering the reverse bias of the junction below the breakdownthreshold.

Then, after a certain dead-time (hold-off time) during which thepixel is ‘‘blind” to any incoming photon (or particle), the electron-ics restores the p-n junction to the initial bias (reset phase). Thewhole quench/recharge cycle provides the information that anevent has occurred [1]. In this work, a novel SPAD architecture con-sisting of a 3D pixel with associated quenching electronics is pre-sented and studied by means of TCAD simulations and dedicatednumerical methods for post-processing of the output data obtainedfrom simulation. The pixel is conceived for an advanced 28 nmFully-Depleted Silicon-On-Insulator (FD-SOI) CMOS technologyand it is suitable for the detection of ionizing particles as well as







164 M.M. Vignetti et al. / Solid-State Electronics 128 (2017) 163–171

light (visible and near-infrared range) in backside illumination(BSI) mode. Thanks to its vertical 3D structure, the proposed solu-tion is expected to allow very small pixels (down to a few lm2)while enabling high fill factor. Moreover, the pixel read-out elec-tronics as well as the whole detector electronics can benefit ofthe well-known advantages brought by SOI technology such ashigher speed and lower power consumption with respect to bulkCMOS. To the best of the authors’ knowledge, this is the first timethat a 3D monolithic SPAD integrated in a standard FDSOI CMOSprocess is proposed and studied.

Fig. 1. Schematic representation of the proposed 3D pixel based on an advancedFDSOI technology.

Fig. 2. Schematic circuit (simplified) of (a) ‘‘diode BOTTOM” configuration showingall the capacitive contributions (b) ‘‘diode TOP” configuration. Observe that Cd andCp are the p-well/deep-n-well and deep n-well/p-substrate space charge capaci-tances respectively.

2. 3D pixel concept for SPAD in SOI technology

Compared to SPAD architectures conceived so far in SOI tech-nology [3–5], the pixel proposed in this work has the great advan-tage to provide a monolithic 3D structure without the need ofdedicated 3D integration techniques. The avalanche diode isindeed defined beneath the Buried Oxide (BOX) while the quench-ing electronics is sitting on top of it, in the SOI layer as depicted inFig. 1.

The pixel has been designed according to the features of anadvanced Fully-Depleted SOI technology, by exploiting the avail-able implantations and diffusions that are normally meant to pro-vide different back-biasing strategies for the transistors. The diodesensitive region is defined in the Space Charge Region (SCR) of a p-well/deep n-well junction. Premature Edge Breakdown (PEB) risk isprevented thanks to a guard-ring placed around the sensitive area.A low doped p-type region can indeed be obtained thanks to theretrograde doping of the deep n-well in the epitaxial p-type sub-strate. Such a region is responsible for smoothing down the electricfield at the junction edge that otherwise would be too intense toallow Geiger-mode operation. The diode can be connected to itsassociated electronics thanks to back-gate contacts featured bythe adopted FDSOI technology, but originally meant to enable a‘‘tunable” threshold voltage for the transistors in the SOI. Two dif-ferent biasing options are possible for the avalanche diode,depending on whether the output node is the anode (diode TOP)or the cathode (diode BOTTOM) as shown in Fig. 2. It is importantto point out that the p-well placed below the BOX (the avalanchediode’s anode) acts as a back-gate for the transistors’ channel inthe SOI, i.e. the threshold voltage is affected by the bias chosenfor the anode. It is therefore recommended to bias the p-well atground in order to prevent any threshold variation for the transis-tors. In the ‘‘diode BOTTOM” configuration (chosen for the TCADstudy discussed in Section 3), the output is sensed at the cathode,i.e. the deep n-well in Fig. 1, while the anode (according to theabove discussion) is biased at ground avoiding any transistor’sthreshold variation. However, under this configuration, the outputvoltage falls within the range from Vbd to Vbd þ Vex which is notcompatible with standard digital voltage levels, i.e. 0V to Vdd. Thisrequires an additional DC decoupling capacitor between the outputof the avalanche diode and the pixel electronics. In the ‘‘diode TOP”configuration, the p-well (anode) bias is varying since it is the out-put node, swinging within the voltage range from 0V to Vex whichis compatible with standard voltage levels if Vmax

ex ¼ Vdd. Duringevery avalanche event the transistors in the SOI layer would thusexperience higher or lower threshold voltages with respect to the‘‘quiescence state” ones, depending on the channel type. For thisreason such a configuration requires pixel electronics insensitiveto (or conveniently exploiting) back-gating effects.

Based on the considerations made so far, two matrix arrange-ments can be obtained with the proposed pixel, as shown inFig. 3. Solution (a) provides shielding of the pixel electronics bygrounding the p-well. The output is thus sensed at the cathodewhich penalizes the fill-factor as every pixel needs an independent

deep n-well. Solution (b) enables higher fill factor (common deepn-well) but the electronics need to be insensitive to back-gatingeffects. It is worth noticing that the resulting back-side illuminated3D pixel can dramatically improve the detector fill factor (FF) withrespect to traditional SPADs, especially in case of small pixels,where this would be strongly degraded by the surface of thequenching electronics sitting next to the avalanche diode. The fillfactor of the proposed 3D pixel is indeed limited by the ‘‘dead”areas of the avalanche diode only, due to the guard-ring and theminimum distance between two diodes.

3. Simulation and post-processing methodology

The proposed 3D pixel has been studied by means of TCAD sim-ulations and dedicated post-processing analysis following theapproach depicted in Fig. 4. TCAD simulations provided an estima-tion of the avalanche diode breakdown voltage (Vbd) and allowedvalidating the diode architecture for a correct Geiger-mode opera-tion by studying the electric field distribution all over the pixel.They also provided the ionization coefficients for electrons andholes (ae;ah) and the EHP generation rates for the Shockley-Read-Hall and band-to-band tunneling mechanisms (GSRH;GB2B).The post-processing analysis allowed the calculation of the mainparameters of a SPAD, such as the avalanche triggering probabilityPtr , the dark count rate (DCR) and the photon detection probability(PDP). In Sections 3.1 and 3.2, TCAD simulations and post-processing, respectively, are discussed in more details.

Fig. 3. Possible matrix arrangements for the proposed pixel. Solution (a): grounded anode. Solution (b): common deep n-well.

Fig. 4. Schematic representation of the adopted simulation strategy. TCAD resultshave been used as input data for a custom post-processing analysis.

Fig. 5. TCAD geometrical model of the 3D SOI pixel. The insert shows the ultra-thinsilicon layer over the buried oxide (Positive values refer to n-type doping. Spatialscales are in lm).

M.M. Vignetti et al. / Solid-State Electronics 128 (2017) 163–171 165

3.1. TCAD simulations

TCAD simulations of the 3D pixel have been carried out inSynopsys Sentaurus, based on realistic process parameters pro-vided by the foundry of the adopted technology. The pixel has beenmodeled as a two-dimensional geometry representing the radialcut of an avalanche diode with cylindrical symmetry (Fig. 5). Thisallowed emulating the geometry of a 3D device while dramaticallyreducing the overall computational time. Carrier transport in thedevice has been described by the drift-diffusion equation, account-ing for the Fermi-Dirac statistics for the electrons and holes distri-bution in the semiconductor. The TCAD physical modelsconsidered the doping dependence of the carriers’ mobility thanksto the Masetti model whose parameters for silicon are based on theexperimental data reported in [6]. The avalanche charge multipli-

cation process depends on the ionization coefficients for electronsand holes, ae and ah respectively, which have been calculatedaccording to the ‘‘van Overstraeten – De Man” model based onexperimental data reported in [7]. Shockley-Read-Hall (SRH) andband-to-band (B2B) tunneling processes have been considered asthe main contributors for the evaluation of the EHP generation-recombination within the avalanche diode sensitive volume.

The SRH model accounts for the presence of deep defect levelsin the silicon energy gap, while the B2B one considers the electronsand holes generation enhancement due to the potential barrierthinning along the multiplication region when the diode is reversebiased above the breakdown voltage. The SRH process is stronglydependent on the carriers’ lifetime sn;p that in turn depends on


many factors such as temperature and doping concentration. Typ-ical values of sn;p range from 1 ms to 1 ls depending on silicon pur-ity, and fall down to about 10 ns only in case of extremely highdoping levels where Auger recombination plays a crucial role [8].For this reason the authors decided to evaluate the SRH generationprocess under two different scenarios, one accounting for a dopingdependent carrier lifetime according to the ‘‘Scharfetter model” [9],the other considering constant carrier lifetimes sn ¼ 10 ls andsp ¼ 3 ls, for electrons and holes respectively [10]. Band-to-Bandtunneling has been modeled with the field-enhanced Schenkmodel neglecting the phonon-assisted tunneling contribution sincethe electric field peak in the avalanche diode is not expected toexceed the value of 8 � 105 V=cm [11]. In the present study, theauthors have chosen to keep the default parameter values providedby the simulation tool for the adopted physical models [10].

3.2. Post-processing

A post-processing analysis based on the parameters extractedby means of TCAD simulations has been performed in order toevaluate the main figures of merit of a SPAD such as the AvalancheTriggering Probability (ATP) Ptr , the Dark Count Rate (DCR) and thePhoton Detection Probability (PDP).

ATP is the probability that an EHP generated in the multiplica-tion region can successfully trigger an avalanche and can be eval-uated by solving the following couple of differential equations[12]:

dPedx ¼ aeð1� PeÞðPe þ Ph � PePhÞ

dPhdx ¼ �ahð1� PhÞðPe þ Ph � PePhÞ

(

ð1Þ

where aeðxÞ and ahðxÞ are the electrons and holes ionization coeffi-cients (resulting from TCAD simulations), respectively, while PeðxÞ,PhðxÞ are the probabilities for initiation an avalanche by an electronor a hole, respectively, generated at the position x within the spacecharge region of the avalanche diode. These equations can be inte-grated with the following boundary conditions:

Phðx ¼ xpÞ ¼ 0

Peðx ¼ xnÞ ¼ 0

where xp and xn are the boundaries of the diode SCR at the p-sideand n-side, respectively. By adopting a numerical method proposedin [13], the ATP at a position x can be conveniently obtained as thejoint probability of Pe and Ph:

PtrðxÞ ¼ Pe þ Ph � PePh ð2Þwhose average all over the space charge region provides the averageavalanche triggering probability:

Ptr ¼ 1xn � xp

Z xn

Xp

PtrðxÞdx ð3Þ

The knowledge of ATP enables the calculation of the DCR as wellas the PDP for the SPAD under study.

Dark Count Rate (DCR) refers to undesired avalanche eventswhich can be triggered by thermal and/or field-assisted generatedEHP due to Shockley-Read-Hall (SRH) and band-to-band tunnelinggeneration – recombination processes occurring in the diode spacecharge regions. The resulting spurious avalanche pulses represent asource of noise for SPAD detectors, depending on the adoptedCMOS process and increasing with the sensor area, with tempera-ture and excess bias. Based on the previous discussion, DCR can becalculated according to the following formula:

DCR ¼Z xn

xp

PtrðxÞGEHPðxÞdx ð4Þ

where GEHPðxÞ is the EHP generation rate as a function of the posi-tion xwithin the diode SCR. Such a parameter is extracted by meansof TCAD simulations and, as discussed in Section 3.1, it accounts forboth SRH and band-to-band generation phenomena in the diodeSCR.

The Photon Detection Probability (PDP) is defined as the proba-bility that a photon of a certain wavelength impinging on the pixelis effectively detected. In order for this to happen, two conditionsmust be satisfied:

– the photon has to be absorbed within the diode sensitive region,i.e. the n-type and p-type neutral regions and the SPAD multi-plication region (i.e. SCR),

– the generated EHP (either the electron or the hole) has to suc-cessfully trigger an avalanche process.

The detection process of a single photon can be described withthe help of an analytical model based on the work done by Guli-natti et al. [8]. It is convenient to simplify the study in a one-dimensional case, as depicted in Fig. 6, where it is possible to iden-tify six different regions: the back-side Anti-Reflective Coating(ARC), the p-type substrate, a SCR between the deep n-well andthe p-substrate, and the SPAD sensitive region consisting of then/p-type neutral regions and the SPAD multiplication region. It isindeed really unlikely that minority carriers generated in devicesensitive region can escape laterally without being collected byone of the two SCR. Only some of those generated really nearbythe device periphery will be probably lost through the guard-ring. These latter minor losses are neglected in this one-dimensional approximation.

A photon with wavelength k hitting the pixel from the back-sidehas a chance to be successfully detected only if it is absorbed in theSPAD active region (Fig. 6). In order to reach this area, the photonshould not be back-reflected at the ARC – p-substrate interface.Indeed the chance for the photon to cross this optical barrier isdefined by the light transmission coefficient, i.e.TðkÞ ¼ 1� RðkÞ < 1, due to the refraction index discontinuity.Moreover the photon should not be absorbed in the p-substrateregion otherwise it would be irremediably lost as there would beno chance that the generated EHP can reach the SPAD multiplica-tion region. Even if the generated minority electron reached thedeep n-well/p-substrate SCR, it would be simply collected at thecathode without triggering any multiplication process. If con-versely the photon is absorbed in the SPAD active region, threepossible scenarios are possible. Fig. 6(a) represents the case wherethe photon is absorbed in the multiplication region (i.e. SCR). Thelocal high electric field promptly accelerates the generated EHPtowards the SCR ends, which might lead to a self-sustained multi-plication process. Under this scenario, an EHP is generated within xand xþ dx in the SCR with a probability given by (5):

pabsðx; kÞdx ¼ e�aðkÞxaðkÞdx ð5Þwhere aðkÞ is the photon absorption coefficient in silicon. The gen-erated EHP can eventually trigger an avalanche process with a prob-ability PtrðxÞ, according to (2). Therefore, the photon detectionprobability under this scenario is given by (6):

PDPðaÞ ¼Z

PtrðxÞpabsðxÞdx ð6Þ

where the integral has to be calculated over the entire multiplica-tion region.

Fig. 6(b) represents the case where the photon is absorbed inthe p-type neutral region. Under this scenario, the generated EHPcan lead to an avalanche event only if the minority electron suc-cessfully reaches by diffusion the upper end of the multiplicationregion where it can eventually trigger an avalanche process with

Fig. 6. Schematic representation of a photon absorption in the active region of the proposed 3D pixel. Three main scenarios have been depicted: (a) the photon is absorbed inthe multiplication region and the generated EHP are swift away by the high electric field. (b) and (c) The photon is absorbed in the upper p-type/lower n-type neutral regionand the generated minority electron/hole randomly diffuses towards the multiplication region where it can eventually fire an avalanche.


a probability PtrðxpÞ. For this purpose it is convenient to define theminority carrier collection efficiency gn�collectionðxÞ as the probabilitythat an electron generated at position x in the p-type neutral regioneffectively reaches the SPAD multiplication region. By accountingfor the probability to generate an EHP, i.e. a minority electron,within x and xþ dx in the p-type neutral region, as described inEq. (5), the photon detection probability under this scenario canbe expressed by (7):

PDPðbÞ ¼ PtrðxpÞZ

gn�collectionðxÞpabsðxÞdx ð7Þ

where the integral has to be calculated over the entire p-type neu-tral region. A similar discussion can be done for scenario (c), wherethe neutral region is now n-type and the minority carrier is ahole:

PDPðcÞ ¼ PtrðxnÞZ

gp�collectionðxÞpabsðxÞdx ð8Þ

Some considerations are necessary for the calculation of theminority carrier collection efficiency. With respect to scenario(b), for instance, a minority electron generated in the neutral p-type region would move along a random walk in absence of astrong electric field. Such a random walk might end at the upperboundary of the SPAD multiplication region, where the carriercan eventually initiate an avalanche process. The minority electronmight also recombine with a hole along its path or at the silicon –BOX interface, but these two latter eventualities turn out to be neg-ligible. Indeed, as discussed in Section 3.1, typical minority carrierlifetimes range from 1 ms to 1 ls depending on silicon purity, andfall down to about 10 ns only in case of extremely high doping con-centration values. Since the diffusion process lasts at most only acouple of nanoseconds, the probability that a generated minoritycarrier recombines in the neutral region becomes negligible. More-over the presence of high concentration of defects at the BOX inter-face would appear as a flux of minority carriers toward the surface,which can be interpreted as the probability to lose a minority car-rier due to surface recombination. However, as discussed more indetail in Ref. [8], this effect can be neglected even by adoptingunreasonably high values of surface recombination velocity. Thesilicon dioxide interface imposes thus a (practically) zero flux ofcarriers, since they cannot escape the insulator. This means thatevery generated minority electron successfully reaches the multi-

plication region thanks to the oxide barrier at the BOX interfaceand thanks to the absence of any recombination phenomenawithin the diffusive time-lapse. For this reason, the minority car-rier collection efficiency in the p-type neutral region can be esti-mated as being 100%. Something different happens in scenario(c). The generated minority hole is, in this case, ‘‘confined” betweenthe multiplication region and the ‘‘inactive” SCR, both acting as col-lecting centers. For this reason the carrier collection efficiency isless than 100%. According to [8], this latter can be calculated bysolving the drift-diffusion equation for the hole in the n-type neu-tral region, by assuming an initial injection of minority carriers cor-responding to the photon absorption probability density all overthe region. In this way, it is possible to extract the probability thata carrier generated within x and xþ dx successfully crosses at agiven time the lower end of the multiplication region. The collec-tion efficiency is finally obtained by integrating such a probabilityover the time. A slightly different approach is proposed in thiswork, by considering only a localized pulse of light generatingexcess carriers in an n-type semiconductor [14], instead of theentire injected minority carriers distribution based on the photonabsorption probability. Moreover, this approach assumes perfectneutrality in the n-type region and thus neglects the drift compo-nent in the transport equation. Naturally, as discussed previously,the generation – recombination term of the transport equation isneglected too, since it is really unlikely that minority carriersrecombine during the very short diffusive time-lapse. This allowedextracting an analytical solution for the problem which is moreconvenient for the analysis and discussion of the results, and offersa great improvement in terms of computation complexity. Given aminority hole generated at the position xph in the neutral region att ¼ 0, the probability to find the carrier at x, after a time t > 0 isgiven by:

phðx; tÞ ¼1

ffiffiffiffiffiffiffiffiffiffiffiffiffiffi

4pDptp e�

ðx�xph Þ24Dpt ð9Þ

where Dp is the hole diffusivity in the n-type region. This equation isin the form of a Gaussian normal distribution and describes the waya generated minority carrier diffuses away from the injection pointxph. It is possible to calculate the probability that at time t the car-rier crosses the lower edge of the multiplication region, in a form ofprobability current:

Fig. 7. TCAD simulation: Electric field color map of the pixel, when the avalanchediode is reverse biased at Vrev ¼ 16:5 V (Spatial scales are in lm).


/hðxn; tÞ ¼ �Dpdphðx; tÞ

dx

�

�

�

�

x¼xn

¼ 2Dpðxn � xphÞffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

43pD3pt

3q e�

ðxn�xph Þ24Dpt

/hðd; tÞ ¼2Dpdffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

43pD3pt

3q e�

d24Dpt

ð10Þ

where d has been defined as the distance between the multiplica-tion region lower edge xn, and the carrier injection point xph. Theprobability that the multiplication region successfully collects thehole is thus obtained by integrating the probability current flowingthrough the multiplication region lower boundary over the time, asfollows:

gh�collectionðdÞ ¼ PhðdÞ ¼Z 1

0/hðd; tÞdt ¼

12

ð11Þ

Interpreting Eq. (11) with respect to scenario (c), it is possible toconclude that the carrier will diffuse towards the multiplicationregion with a 50% probability, wherever the injection point is.For this reason, the minority carrier collection efficiency in the n-type neutral region can be estimated as being 50%. This resultshould represent a good first order estimation of the collection effi-ciency. It is however important to point out that in reality a weakelectric field is normally present in the neutral regions due to thegradient of the doping concentration. The neglected drift compo-nent in the transport equation might therefore lead to a slightlydifferent result in the collection probability.

The overall photon detection probability can be finally calcu-lated by accounting for the three different scenarios/regions:

PDPðkÞ ¼ TðkÞðPDPaðkÞ þ PDPbðkÞ þ PDPcðkÞÞFor the sake of ease, the present study considers a perfect anti-

reflective coating (ARC) providing a reflection coefficient R ¼ 0 (i.e.a transmission coefficient T ¼ 1� R ¼ 1).

PDPðkÞ ¼Z

PtrðxÞpabsðx;kÞdxþ PtrðxpÞZ

gn�collectionðxÞpabsðx; kÞdx

þ PtrðxnÞZ

gp�collectionðxÞpabsðx; kÞdx

PDPðkÞ ¼ e�aðkÞtsub ðe�aðkÞWn

Z WSCR

0Ppðx0Þe�aðkÞx0aðkÞdx0

þ PtrðxnÞ12 ð1� e�aWn Þ þ PtrðxpÞe�aðkÞðWnþWSCRÞð1� e�aðkÞWp ÞÞð12Þ

where Wn;Wp;WSCR are the n/p-type and multiplication regionwidths and tsub is the p-substrate thickness.

4. Results and discussions

The simulation results for the novel 3D SPAD pixel proposed inthis work are here presented and discussed. In Section 4.1, the ava-lanche diode architecture has been first validated for Geiger-modeoperation by means of an electrostatic analysis of the adoptedgeometry, before proceeding with further studies on the device.The main figures of the proposed SPAD are subsequently evalu-ated: the breakdown voltage (Vbd) and the avalanche triggeringprobability (ATP) in Section 4.2, the dark count rate (DCR) in Sec-tion 4.3 and the photon detection probability (PDP) in Section 4.4.

4.1. Electrostatic Analysis of the avalanche diode

An electrostatic analysis on the proposed pixel has been con-ducted in order to validate the avalanche diode architecture for acorrect Geiger-mode operation. Fig. 7 shows the electric field colormap of the pixel when the avalanche diode is reverse biased atVrev ¼ 16:5 V, with grounded anode and substrate. The avalanche

generation model has been switched off in order to reproducethe electric field distribution as it would be right before the startof the multiplication process, after which the field would beaffected by the high amount of charges flowing through the junc-tion. A uniform electric field (red region) is observed in the pixelactive region, i.e. all along the horizontal direction in the p-well/deep n-well junction, which ensures a uniform avalanche trigger-ing probability in the sensitive volume. By moving towards themultiplication region periphery, the field drops gradually to lowervalues, thanks to the retrograde n-type doping in the deep n-well,effectively acting as guard-ring for the device. For this reason, Pre-mature Edge Breakdown (PEB) cannot occur, and Geiger-modecompatibility for the diode architecture can be assessed.

4.2. Breakdown voltage and avalanche triggering probability

The breakdown voltage (Vbd) of the avalanche diode in the pro-posed 3D pixel has been thus extracted in order to define thethreshold above which the SPAD can work in the Geiger-mode.For this purpose, the reverse bias I � V curve of avalanche diodedirectly obtained from TCAD simulation and the average avalanchetriggering probability (ATP) as a function of the reverse bias areplotted in Fig. 8 (right and left y-axes respectively). It is worthnoticing how both curves led, approximatively, to the same Vbd

value. The breakdown voltage observed in the I � V curve(Vbd ¼ 13:5 V) is indeed very close to the voltage correspondingto the threshold for an ATP > 0% (Vth�ATP � 13:4 V). This corrobo-rates the validity of the adopted post-processing method presentedin Section 3.2 for the extraction of the ATP. In order to implementthis latter, the ionization coefficient aeðxÞ and ahðxÞ (but also otherparameters discussed later) have been extracted from a cut-linewithin the device active region, along the vertical direction withrespect to the geometry shown in Fig. 5. Provided that the cutlineis taken at a horizontal position sufficiently distant from the guard-ring, it is indeed possible to consider the ionization coefficients tobe constant along the horizontal direction (1D symmetry). More-over it is important to point out that the TCAD simulator providesionization coefficients based on measurements where the electricfield is assumed to be constant all over the ionization path [8]. Thiscondition is generally not true for SPAD realized in very deep sub-micrometer CMOS technology due to the typically abrupt andhighly doped pn junction defining the avalanche multiplicationregion, which results in a sharp and triangular shaped electric fieldalong the diode SCR. However the SPAD proposed in the presentstudy could be considered to satisfy (to some extent) such an

Fig. 8. Symbols, left y-axes: average avalanche triggering probability calculatedaccording to the method proposed in [13]. Dashes, right y-axes: reverse bias I � Vcurve of the avalanche diode resulting from TCAD simulation. Observe that theSPAD active area diameter is D ¼ 7 lm).

Fig. 9. TCAD simulation: EHP generation mechanisms in the multiplication regionof the diode at Vrev ¼ 16:5 V.

Fig. 10. Total DCR per unit surface for the simulated avalanche diode (andcontributions of SRH and band to-band generation mechanisms).


assumption thanks to the ‘‘linearly graded” p-well / deep n-welljunction, leading to a quite smooth electric field distributionwithin the multiplication region (see insert in Fig. 7).

4.3. Dark count rate

The knowledge of the ATP as a function of the position in thediode multiplication region, i.e. PtrðxÞ, allows the calculation ofthe DCR as well as the Photon Detection Probability ðPDPÞ for theSPAD under study. According to Eq. (4), DCR calculation requiresthe extraction of the EHP generation rates as a function of the posi-tion x within the diode SCR. This has been done for several excessbiases Vex (Vex ¼ Vrev � VbdÞ above the breakdown voltage, withinthe range 0—6:5 V. Fig. 9 shows, for instance, the two main EHPgeneration mechanisms occurring in the avalanche diode underthe same bias adopted for Fig. 7 (Vex ¼ 3 V). SRH generation seemsto be the dominant generation mechanism in the avalanche diodesensitive region. Even if tunneling generation peaks to a value veryclose to the doping independent SRH generation, the former is verynarrowly distributed along the junction, leading to a minor contri-bution to the overall EHP generation.

Naturally field-enhanced generation process would anywayincrease for higher excess bias values, and would likely becomethe dominant contributors in the DCR. Moreover, as discussed inSection 3.1, the SRH generation has been evaluated based on twodifferent scenarios, i.e. by assuming either doping dependent orconstant carrier lifetime for the electrons and holes generated inthe SCR. The first scenario however led (a posteriori) to a quite highDCR which seemed unrealistic with respect to experimental datafound in literature for avalanche diodes having similar breakdownvoltages [4]. For this reason only the second scenario has been con-sidered for the DCR calculation reported in Fig. 10 in terms ofcounts per unit surface, as a function of the applied excess bias.The DCR produced individually by the two EHP generation mecha-nisms have been plotted too in Fig. 10 in order to highlight the con-tribution provided by each of them on the total counts. It ispossible to distinguish a dominating SRH region for excess biaslower than 4 V and a dominating tunneling region for voltageshigher than 5 V, depending on the strongest EHP generation mech-anism. In the SRH region, the DCR is indeed relatively moderateand increases with the excess bias according to the ATP enhance-ment shown in Fig. 8 (symbols, left y-axes). On the other hand, thislatter is not really influent in the tunneling region (ATP is >80% andslowly saturates to 100%) where the DCR rises really fast with theexcess bias mainly because of field-enhanced carrier generation. It

is worth noticing that if different carrier lifetimes for the electronsand holes were adopted in the SRH model, a similar curve wouldhave been obtained in Fig. 10. Assuming for instance that shortercarrier lifetimes with respect to those used in this study have beenadopted, a higher DCR would be observed in the SRH region (due toa higher SRH generation) and the corner defining the transitionbetween the SRH and the tunneling regions would be simplyshifted towards higher excess bias values. An opposite discussionwould stand in case of longer carrier lifetimes. Finally, it is reallyhard to make a more precise conclusion without any experimentaldata coming from direct measurements of the device.

Nevertheless, it is interesting to observe that the results shownin Fig. 10 look quite close to what can be found in literature foravalanche diodes having similar breakdown voltages, i.e.DCR � 150 Hz=lm2 for Vex ¼ 1 V [4].

4.4. Photon detection probability

The Back-Side Illuminated (BSI) Photon Detection Probability(PDP) for the proposed 3D SPAD pixel has been calculated withthe help of (12) within the wavelength range [400—1200 nm].The optical data for the photon absorption coefficient in siliconaðkÞ have been taken from Ref. [15]. Fig. 11 shows the PDP calcu-

Fig. 11. Photon detection probability for different substrate thicknesses with back-side illumination (and comparison with front-side illumination).

Fig. 12. Reflection coefficient at the Si/BOX interface for a photon travelling fromthe silicon substrate towards the ‘‘multilayer” BOX/SOI thin film structure, belowthe interconnect layer.


lated when an excess bias of 5 V is applied. Several thickness val-ues of the p-type substrate, down to 5lm have been considered.Even though this latter value might appear extremely small andquite unrealistic, it is worth noticing that ultra-thinning processdown to 4 lm over a 300 mm wafer has been actually reportedin literature, i.e. Ref. [16]. The author focused on the feasibilityfor multi-stack Wafer-on-Wafer (WOW) processes and multi-stacking for Tera-scale high density memory, but the resultsobtained in his study might be extended to other applications inthe near future. It is thus interesting to investigate the BSI perfor-mance of a SPAD under this scenario too. According to Fig. 11, thePDP in BSI mode (symbols) looks quite small with respect to whatcan be obtained in a front-side illuminated mode (dashes), espe-cially in the short wavelength range. At longer wavelengths, con-versely, the curves tend to converge towards a common trend.Fig. 11 can be better understood with the help of an approximatedform of (12):

PDPðkÞ � e�aðkÞtsub|fflfflfflffl{zfflfflfflffl}

A

aðkÞ 12PtrðxnÞWn þ PtrðxpÞWp þ PtrWSCR

� �

|fflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl}

B

ð13Þ

where Wn;Wp;WSCR are the n/p-type and multiplication regionwidths, tsub is the substrate thickness and, according to (3), Ptr isthe average ATP over the multiplication region.

The approximation arises from the fact that the photon penetra-tion depth is much larger than the overall active region width, i.e.1=aðkÞ � ðWn þWp þWSCRÞ over the considered wavelength rangewhich allows a first-order Taylor approximation of the exponen-tials in (12). Term ‘‘A” in Eq. (13) represents the probability thata photon impinging on the back-side of the pixel, successfullyreaches the lower edge of the active region. Term ‘‘B” representsconversely the probability that a photon entering the active regionis here absorbed and successfully fires an avalanche. It is thusapparent that the PDP degradation on the BSI mode is due to the‘‘A” term, which accounts in fact for the optical losses into the p-substrate. In BSI mode, shorter wavelength photons are indeedmostly absorbed within the first few hundreds of nanometers ofthe silicon substrate due to their short penetration depth. That iswhy thinner substrates provide higher PDP within this wavelengthrange. When the penetration depth approaches the substratethickness, i.e. 1=aðkÞ ¼ tsubstrate, PDP reaches a maximum. Since1=aðkÞ increases for longer wavelength, the peak moves to the rightfor thicker substrates. For longer wavelengths the penetrationdepth becomes larger which leads the ‘‘A” term to be negligible(A ! 1Þ. That explains the convergence of the BSI curves with the

FSI one towards a common trend with respect to the photon wave-length. The ‘‘B” term is conversely determined by the electrical andgeometrical properties of the SPAD active region. While these lat-ter depends on the avalanche diode architectures and ultimatelyon the adopted CMOS process, the electrical properties can be con-trolled by acting on the device excess bias voltage, which affectsthe avalanche triggering probability, as discussed in Section 3. Alittle improvement on the PDP can arise from the light reflectionat the p-well/BOX interface thanks to the ‘‘multi-layer” filmdefined by the Silicon/BOX/SOI stack (see insert inFigs. 5 and 12). Based on the same considerations made for theapproximation of (12) with (13), the overall efficiency can beexpressed as follows (14):

PDPtotðkÞ ¼ PDPð1þ RðkÞÞ ð14Þwhere RðkÞ is the reflection coefficient at the silicon/BOX interface,experienced by a photon travelling from the silicon substratetowards the ‘‘multilayer” BOX / SOI thin film structure, below theinterconnect layer (a dielectric medium). In order to provide a firstorder estimation of such an improvement, the low-k dielectric med-ium has been simply modeled with air, but a proper modelingwould be necessary for more accurate results. The reflectance underthis scenario is thus reported in Fig. 12 [17]. It is worth noticing thatwithin the longer wavelength range, where the BSI PDP wouldbecome less dependent on the substrate thickness and would alsobenefit of reflection enhancement higher than 20%, BSI SPADs canreally provide better performances than FSI ones. The scenario con-sidered in Fig. 11 for the FSI case is indeed very ‘‘optimistic” since itdoes not take into account the much lower fill-factor of a FSI pixel(since the electronics would sit next to the avalanche diode) butalso the photon reflections due to the interconnect layer of the chipas well as the SOI-BOX thin film structure. All of this translates intoan important degradation of the FSI PDP.

The BSI 3D SPAD pixel proposed in this work would be suitable,for instance, for the realization of commercially available time-of-flight (T-o-F) ranging sensors working at k ¼ 940 nm. Thesedevices are typically used for accurate measurements of the dis-tance from a target object, in camera assist (ultra-fast autofocusand depth map), user detection for power saving in smartphonesor laptops, gesture control, drones, robotics and many other appli-cations [18]. As an interesting case study, Fig. 13 shows the PDP fora BSI SPAD as a function of the substrate thickness, at k ¼ 940 nm(T-o-F ranging sensors compatible) when an excess bias of 5V isapplied on the avalanche diode. The grey curves propose an inter-esting comparison with an FSI SPAD, in the ideal case (solid line),

Fig. 13. Photon detection probability for a wavelength of 940 nm (time-of-flightranging applications) and comparisons between back-side illumination and front-side illumination (with or without reflection).


i.e. like the one considered in Fig. 11, and when only the reflectiondegradation due to the BOX-SOI multilayer thin film is taken intoaccount (dashes).

As expected, despite of the presence of a silicon substrate intro-ducing optical losses, the BSI efficiency remains within the samepercentage order of the ‘‘optimistic” FSI one. More interestingly,if reflection effects are taken into account (dashed curves), theBSI SPAD would perform even better than the FSI one, up to a sub-strate thickness of 20 lm. As discussed previously, FSI PDP degra-dation would be much larger than what has been estimated inFig. 13. This would furtherly lower the dashed grey curve andwould thus displace the intersection point with the BSI PDPtowards thicker substrate, meaning that BSI mode would be defi-nitely preferable for this kind of application.

5. Conclusions

In this work, a novel 3D SPAD pixel architecture consisting of anavalanche diode with associated electronics has been presentedand studied by means of TCAD simulations and dedicated numer-ical methods for post-processing analysis. The pixel has been con-ceived for advanced Fully-Depleted Silicon-On-Insulator (FDSOI)CMOS technology and it is suitable for the detection of ionizingparticles as well as light (visible and near-infrared range) in back-side illumination (BSI) mode. TCAD simulations based on realisticprocess parameters provided an estimation of the avalanche diodebreakdown voltage (Vbd) and allowed validating the diode architec-ture for a correct Geiger-mode operation by studying the electricfield distribution all over the pixel. They also provided the param-eters required by the post-processing analysis in order to extract

the main figures of merit for a SPAD, such as the avalanche trigger-ing probability Ptr , the Dark Count Rate (DCR) and the PhotonDetection Probability (PDP). A comparison between the efficiencyin back-side and front-side illuminated SPADs showed that the for-mer approach can provide better performance within the longwavelength spectrum range. Based on the obtained results, it ispossible to conclude that the BSI 3D SPAD pixel proposed in thiswork can be a very good candidate single-photon detector fortime-of-flight (T-o-F) ranging sensors, and more generally for longwavelength sensing applications.

Acknowledgments

This project has been funded from the European Union’s 7thFramework Program for research, technological development anddemonstration under grant agreement n� 317446.

References

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[3] Zou Y, et al. Backside illuminated wafer-to-wafer bonding single photonavalanche diode array. In: 10th conference on Ph.D. Research inMicroelectronics and Electronics (PRIME); 2014.

[4] Lee MJ et al. A first single-photon avalanche diode fabricated in standard SOICMOS technology with a full characterization of the device. Opt Exp 2015;23(10).

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[7] van Overstraeten R, de Man H. Measurement of the ionization rates in diffusedsilicon p-n junctions. Solid-State Electron 1970;13(1):583–608.

[8] Gulinatti et al. Modeling photon detection efficiency and temporal response ofsingle photon avalanche diodes. In: Proc SPIE 7355, photon countingapplications, quantum optics, and quantum information transfer andprocessing II, 73550X; May 2009.

[9] Roulston DJ et al. Modeling and measurement of minority-carrier lifetimeversus doping in diffused layers of n + p silicon diodes. IEEE Transact ElectronDev 1982;ED-29(2):284–91.

[10] Sentaurus Device User Guide; 2013.[11] Schenk A. Rigorous theory and simplified model of the band-to-band tunneling

in silicon. Solid-State Electron 1993;36(1):19–34.[12] Oldham WG, Samuelson RR, Antognetti P. Triggering phenomena in avalanche

diodes. IEEE Trans Electron Devices 1972;19(9):1056–60.[13] McIntyre RJ. On the avalanche initiation probability of avalanche diodes above

the breakdown voltage. IEEE Transact Electron Dev 1973;ED-20(7):637–41.[14] Sze S, Ng K. Physics of semiconductor devices, 3rd ed.; November 2006. ISBN:

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[17] http://www.filmetrics.com/reflectance-calculator.[18] World smallest Time-of-Flight (ToF) laser ranging sensor - VL53L0X. <http://

www2.st.com/resource/en/data_brief/vl53l0x.pdf>.






























http://www.filmetrics.com/reflectance-calculator

http://www2.st.com/resource/en/data_brief/vl53l0x.pdf

http://www2.st.com/resource/en/data_brief/vl53l0x.pdf





Reconfigurable ultra-thin film GDNMOS device for ESD protection in28 nm FD-SOI technology


⇑ Corresponding author at: STMicroelectronics, 850 rue Jean Monnet, 38920Crolles, France.

E-mail address: [email protected] (S. Athanasiou).

Sotirios Athanasiou a,b,⇑, Charles-Alexandre Legrand a, Sorin Cristoloveanu b, Philippe Galy a

a STMicroelectronics, 850 rue Jean Monnet, 38920 Crolles, Franceb IMEP, 3 Parvis Louis Néel, CS 50257, 38016 Grenoble Cedex 1, France




Keywords:CMOSElectrostatic dischargesESDFD-SOIGated diodeLBJTMOSFETSOIThyristor

a b s t r a c t

We propose a novel ESD protection device (GDNMOS: Gated Diode merged NMOS) fabricated with 28 nmUTBB FD-SOI high-k metal gate technology. By modifying the combination of the diode and transistorgate stacks, the robustness of the device is optimized, achieving a maximum breakdown voltage (VBR)of 4.9 V. In addition, modifications of the gate length modulate the trigger voltage (Vt1) with a minimumvalue of 3.5 V. Variable electrostatic doping (gate-induced) in diode and transistor body enables reconfig-urable operation. A lower doping of the base enhances the bipolar gain, leading to thyristor behavior. Thisinnovative architecture demonstrates excellent capability for high-voltage protection while maintaininga latch-up free behavior.


1. Introduction

Recent advances in Fully Depleted SOI (FD-SOI) technology [1]continue to shrink the design window [2] of ElectroStatic Dis-charge (ESD) protection devices, reducing supply voltage VDD anddecreasing breakdown voltage VBR. This window is highly depen-dent on the type of devices to be protected, as well as on the regionof operation. Contrary to the typical hybridization techniques,where the thin silicon film and Buried Oxide (BOX) are etched inorder to have direct access to the silicon substrate and fabricatebulk-like ESD devices [3], the focus of this work is to use the thinFD-SOI layer.

Previous studies have been conducted on thin film BiMOSdevice for protection of circuits operating in the typical voltagerange for FD-SOI technology [4–6]. In a BiMOS, the lateral bipolarjunction transistor (LBJT) is activated by current injection to thebase, from a lateral contact, while the MOSFET is operating in sub-threshold region. The BIMOS gain can be modulated electrostati-cally through the top or bottom gate biasing. Alternatively band

modulation devices [7] such as the Z2FET show exceptional behav-ior as ESD protection elements in FD-SOI technology.

Typical strategy for a standard process flow is to reduce thenumber of steps required for a particular device, in order to mini-mize both the variability and the cost. Thus, structures that do notrequire extra process steps for hybridization or implantation (forexample, no customized doping concentration) need to beexplored in terms of power and switching performance. Normally,high voltage transistors can sustain several hundred volts, this isnot the case with ultra-thin film and BOX (UTTB) technology sincethe breakdown of top and bottom oxides imposes limitations onthe power that a device can sustain.

In this work, we present an original structure (GDNMOS) forhigh voltage protection that combines diode and MOSFET mecha-nisms, a semi-regular structure that abides by process rules forlimiting variability. Electrical measurements prove the flexibility,functionalization and robustness of the GDNMOS. 3D TCAD [8]simulations reveal the details of the operation mechanisms as wellas the potential behavioral improvements.

In Section 2, the physical mechanisms involved are described,followed by the device structure and process. Detailed TCAD simu-lations to investigate the GDNMOS operation during an ESD stressare presented in Section 3. Finally, in Section 4 the fabricated struc-







Fig. 2. Typical high current I–V curve of a protection device.

MOS

Gate

Diode

Gate

Lg1 Lg2 MG-DG2 Bias

S. Athanasiou et al. / Solid-State Electronics 128 (2017) 172–179 173

tures are investigated by utilizing DC and Transmission Line Pulse(TLP) electrical measurements.

2. Device structure and properties

2.1. General operation mechanisms

GDNMOS is composed of a typical FD-SOI nMOSFET mergedwith an FD-SOI p-i-n gated diode, see Fig. 1. There is a common(merged) n-type area which acts as the diode cathode and as theMOSFET drain. The ultrathin bodies of the diode and transistorcan be electrostatically doped (N+ or P+, by attracting differenttypes of carriers in the ‘intrinsic’ region below the gate) via thegates or back-plane bias.

During a stress, in a thyristor-like device the trigger voltage (Vt1,see Fig. 2) is dependent on the sum of the common base currentgain (a) of the two bipolar transistors. In our case the npn LBJTformed within the nMOSFET and pnp LBJT formed between thenMOSFET and the gated diode (Fig. 1). Starting from a typical n-p-n device the common-base current gain a can be defined as [9]:

a ¼ iCiE; aNPN ¼ cE � aT � cC ð1Þ

where cE is the emitter efficiency, aT is the base transport factor,and cC is the collector efficiency:

cE ¼ aE ¼ Jnð0ÞJnð0Þ þ Jpð0Þ

¼ DnBLpEn2iBNDE

DnBLpEn2iBNDE þ DpEWBn2

iENABð2Þ

L and D are the diffusion length and constant for a type of carrier, ni

is the intrinsic carrier density and N is the doping concentration. Allof the aforementioned values are indicated with a subscript for aspecific area of the BJT: E, Emitter, B, Base, C, Collector.

In order to increase the thyristor efficiency, we have to enhancethe emitter efficiency for each BJT. This can be done by shrinkingthe gate length (by design) or by lowering the acceptor doping inbase area (by biasing). Our main purpose is to take advantage ofsuch reconfigurable behavior for emulating a PNPN thyristor struc-ture: positively biased P+ anode, floating N+ drain, P-MOSFET body,grounded N+ source (Fig. 1).

2.2. Operation mechanisms under ESD conditions

During standard operation, when the bias applied to an ESDprotection device is lower than VDD, the device should exhibit verylow leakage current. The low leakage current is attributed to thereverse bias applied to the pn junction between Emitter and Base.Low leakage region is observed by increasing the anode voltageuntil the point defined by trigger voltage (Vt1) and trigger current(It1) (Fig. 2). When a higher voltage drop occurs, bipolar orthyristor-like effects are activated, and the device starts to conductcurrent. This behavior is caused by avalanche breakdown that willbe discussed later. This operating regime continues until a pointindicated as holding point with holding voltage (Vh) and holding

Fig. 1. Schematic (left) and cross-section (right) of GDNMOS structure.

current (Ih). After this holding point, device enters the self-biasedbipolar operating region until secondary (thermal) breakdown isreached. At this point, we define a failure voltage (Vt2) and a failurecurrent (It2) beyond which the device behavior is permanentlydamaged.

2.3. Fabrication and process details

Test devices (Fig. 3) were fabricated with the 28 nm FD-SOISTMicroelectronics process featuring an ultra-thin silicon film of7 nm, ultra-thin BOX of 25 nm, high-k metal gate stack and p-type backplane (p-BP). The devices were fabricated with differentgate stack options (Fig. 3): Standard Gate (SG, EOT = 1.1 nm) andExtended Gate (EG, EOT = 3.4 nm). In DEV1, 2, 3 structures theMOS gate and the diode gate were interconnected, while inDEV4, 5, 6 they were independent. In the mixed gate stack devices,the gate oxide of the diode was always selected to be thick (EG), forincreased robustness to the stress applied to anode.

Minimum process-compliant gate dimensions were selected foreach gate stack combination. The variation of the gate length (45–150 nm) was due to the difference imposed in fabrication processfor EG and SG gate stacks and the minimum distance betweenpolysilicon structures, resulting in different minimum lengths foreach case. All devices were fabricated in multi finger topology withtotal combined finger width W of 100 lm.

3. Simulation results

The 28 nm FD-SOI GDNMOS was meshed in 3D for differentgate stack configurations. We consider phonon scattering, Cou-

(G1) (G2)

DEV1 SG SG 45nm 45nm conn 2V

DEV2 SG EG 30nm 150nm conn 4V

DEV3 EG EG 150nm 150nm conn 4V

DEV4 SG SG 45nm 45nm separ 2V

DEV5 SG EG 30nm 150nm separ 4V

DEV6 EG EG 150nm 150nm separ 4V

Fig. 3. Different device configurations fabricated.

174 S. Athanasiou et al. / Solid-State Electronics 128 (2017) 172–179

lomb scattering in doped materials, and mobility degradation dueto high field saturation and high temperature (for thermodynamicsimulations). Other active modules include avalanche model,Auger recombination model as well as dynamic non-local Band-to-Band tunneling model. In all cases Boltzmann statistics wereused for electron and hole densities calculations.

For the simulation study, the surge is an Average Current Slope(ACS) stress with a ramp from 0 A to 1 A max current during100 ns, which is equivalent to the transmission line pulse (TLP) testfor human body model (HBM) [10].

3.1. Isothermal simulation

For isothermal simulations, the simulator is solving a system ofequations [8] including Poisson:

r eruð Þ ¼ �q p� nþ ND � NAð Þ ð3ÞContact equation:

r rrUMð Þ ¼ 0 ð4Þwhere r is the metal conductivity and UM the Fermi potential.

Electron and hole equations:

Jn!¼ �nqlnrUn and Jp

!¼ �nqlprUp ð5Þ

where Un and Up are the quasi-Fermi potentials.As well as circuit equations.Boundary conditions assume all contacts on semiconductor

materials to be Ohmic, subject to charge neutrality andequilibrium.

Fig. 4 shows typical I–V characteristics resulting from ACS sim-ulation. A clear differentiation between the mixed SG-EG gatestacks as well as EG-EG gate stacks is observed as well as the effectof floating versus grounded/biased gate terminals. In the case offloating terminals, the MOSFET energy bands are affected only bythe Fermi energy difference between metal (HKMG stack) andthe silicon film, and through coupling to the backplane Fermienergy. Naturally the energy bands in silicon are bended slightlydownwards and there is no major electrostatic modulation of theLBJT behavior.

For grounded gates, the bands are affected both by the Fermienergy difference and by the potential applied, resulting in differ-ences in carrier concentration under the gate. The reason for apply-ing these initial conditions is due to the fact that in realapplications an ESD surge can happen on an integrated circuit even

Fig. 4. ACS I–V 3D TCAD simulation for devices 2, 3, 5 and 6.

if there is no power which makes it challenging to apply a constantbiasing to the gate terminals. Additionally with grounded andfloating gates all the MOSFET effects are suppressed and weobserve the real thyristor behavior. At the end of the stress, currentdensity reaches the maximum value with conduction through thewhole film (volume inversion, Fig. 5).

Fig. 6 shows the band diagram at the end of an ACS stress forgrounded nMOSFET gate and diode gate. There is a significantbending of the bands due to the high voltage drop (more than4 V). Also, we observe the difference due to using different gatestacks for the nMOSFET with different lengths. This band bendingis especially pronounced between the merged area and the nMOS-FET gate, leading to increased band to band tunneling (Fig. 7).

Avalanche breakdown serves as a trigger element to initiate theturn on of an ESD device. As the carrier energy approaches the ion-ization threshold, energy transfers from the carrier to the lattice.This causes impact ionization (II) which results in generation ofmore carriers and, ultimately, to avalanche breakdown [11]. Dur-ing the ACS stress of our device (Fig. 8) we observe that maximumII generation is located at the pn junction between the base of thenpn bipolar and the merged area. This area is the most potentialcandidate for creating an avalanche breakdown, and will be dis-cussed later.

3.2. Electrothermal simulation

During an ESD event, energy is injected into the protectiondevice. In the case of UTBB, it is imperative to study the self-heating effects in the device, primarily caused by the poor thermal

diffusivity a ¼ jqCp

� �

[11] (where Cp is the specific heat), of thick sil-

icon dioxide (BOX) compared to bulk silicon. We introduce the lat-tice temperature equation and modify previous equations (4) and(5) to include the temperature gradients:

Lattice temperature:

@

@tCLT �rjrT ¼ �r PnT þUnð ÞJn þ PpT þUp

� �

Jp� �

� ECþ32kT

�

rJn � Ev � 32kT

�

rJp ð6Þ

where j the thermal conductivity, cL the lattice heat capacitance, Pn

and Pp the thermoelectric power for electrons and holes whichaccounts for Seebeck effect.

Contact equation:

r rrUM þ PrTð Þ ¼ 0 ð7Þwhere P is the metal thermoelectric power.

Electron and hole equations:

YZ cut

Fig. 5. Current density extracted at the end of ACS stress for device 6, groundedgates. Volume conduction is visible.

Fig. 6. Energy band diagram (YZ cut) at the end of ACS I–V TCAD simulation fordevices 5 and 6.

Max B2B tunneling

Fig. 7. Band to band tunneling generation at the end of ACS stress.

Max Impact Ionization

Fig. 8. Impact ionization during the ACS stress for device5 at time t1.

Extraction point Tcrit

Fig. 9. Average and peak temperature during ESD stress due to self-heating.


Jn!¼ �nqlnðrUn þ PnrTÞ and Jp

!¼ �pqlp rUp þ PprT

� � ð8Þ

and typical circuit equations.Additionally a temperature boundary condition (T = 300 K) was

applied to the bulk silicon area below the BOX.The temperature equation (6) as well the temperature gradients

in Eqs. (7) and (8) are essential in the study of self-heating effectsand electrothermal stability of the device. The electrothermal sta-

bility with the condition @I@T

V ¼ 1V

dPdT can cause the thermal break-

down of the device through the creation of mesoplasma states[11]. By performing temperature extraction, we note a significantdifference between maximum and device average temperature(Fig. 9). This difference can be explained by the existence of a hotspot in the pn junction near the merged area (Fig. 10), the samearea where the maximum impact ionization was observed.

4. Measurements and discussion

The devices were tested in DC and TLP [12] modes under differ-ent conditions.

4.1. DC measurements

The selection of gate stack affects strongly the breakdown volt-age of the device (Fig. 11) with EG gate stack devices exhibitinghigher breakdown voltage and lower leakage. On the other hand,the use of EG gate stack limits the minimum gate length to150 nm something which strongly affects LBJT gain and in turnTLP behavior that will be discussed in the next paragraph. Break-down voltage extraction was performed on multiple dies (Figs. 11–13). Devices 4, 5 and 6 exhibit superior performance and very goodvariability.

4.2. TLP measurements

TLP measurements had duration of 100 ns or 5 ns pulse widthwith native (300 ps) or 10 ns rise time. The stress was applied onanode, while cathode was grounded. During the first measure-ments, the gates were either grounded or floating. Our primarygoal is to investigate the ESD behavior of the various structuresand evaluate the efficiency of the floating-body (without base con-tact) lateral thyristor.

For the first type of devices (Fig. 14), [13] with the two gatesconnected, we observe snapback characteristics. Same trend isobserved for in devices of second group that have separate MOSand diode gates (Fig. 15), [13], for identical biasing conditions.For these structures, there is no systematic differentiation between100 ns and 5 ns TLP I–V curves. The trigger voltage reaches 5 V. Nostrong snapback behavior is observed primarily due to (i) the lackof direct control on the Emitter-Base p-n junctions of the LateralBipolar Junction Transistors (LBJT between source and drain ofMOSFET), and (ii) the relatively high doping of LBJT base in the

Fig. 10. 2D temperature extraction during ACS stress in thermodynamic simulationafter 38 ns.

Vt1 It1 It2 Vhold VBR

DEV1 GND NA NA <20mA NA 3.1V

DEV1 FLT NA NA <180mA NA NA





DEV4 GND 4V NA >160mA 4V 4.3V

DEV4 FLT 4V NA >140mA 4V NA

DEV5 GND 3.5V NA >160mA 3.5V 4.3V

DEV5 FLT 3.5V NA >140mA 3.5V NA

DEV6 GND 4.5V NA >160mA 4.5V 4.9V

DEV6 FLT 4.3V NA >140mA 4.3V NA

Fig. 11. Extracted results for different gate biasing and configurations. We observethe improved performance with implementations 4, 5 and 6. These devices exhibithigher It2, improving robustness during an ESD event.

Safe Damaged

Fig. 12. Device 5 DC sweep with grounded G1 and G2 for breakdown voltageextraction at room temperature.

Safe Damaged

Fig. 13. Device 6 DC sweep with grounded G1 and G2 for breakdown voltageextraction at room temperature.

Fig. 14. Device 3 TLP measurements for different pulse width: 100 ns and 10 ns.

Fig. 15. Device 6 TLP measurements for different pulse width: 100 ns and 10 ns.


merged area. In terms of ESD protection capability, DEV5 and 6provide the best performance with higher It2, lower leakage andhigher breakdown voltage.


In Fig. 16 we see the chronogram extracted from the TLP mea-surements with grounded gates, at different current levels. EachTLP point is calculated as an average of voltage values betweenthe two lines in Fig. 16. It is interesting to observe the over-voltage behavior during the TLP stress. The average voltage forthe TLP curve is lower than the actual voltage applied to the device.In terms of reliability this means that for a limited time, whenover-voltage peaks appear during the measurement, the structureis forced to a higher stress than the one anticipated.

Fig. 17. Device 6. TLP 100 ns, RT 10 ns with different positive G1 biasing, VG1 = 0 Vand VBP = 0 V.

Fig. 18. Device 6. TLP 100 ns, RT 10 ns with different negative G2 biasing, VG1 = 0 Vand VBP = 0 V.

4.3. Front and back gate effect

The device behavior during a TLP stress can be modified by bias-ing the MOS gate (G1). In particular, the gate bias modulates thenMOSFET LBJT gain. With positive bias for the nMOSFET gate, theenergy bands in the base area are lowered (by �qVG1). Electronsare attracted in the bipolar base, increasing the npn LBJT gainand the overall anode current (Fig. 17). This behavior is observedwhile we are in the nMOSFET subthreshold region (VG1 < VT0).When biasing becomes higher than nMOSFET threshold voltagewe activate additionally the MOS effect.

Reciprocally, by utilizing a negative gate bias the energy bandsare raised. However, since there are no extra holes available to beattracted in the body (LBJT base), the modulation of IA-VA curves isweak while the gain is slightly decreased. These trends are verifiedby the TLP measurements presented in Fig. 18 (for VG1 = 0).

The n-type base of the pnp LBJT is located in the merged area sobiasing the diode gate does not affect strongly the pnp gain. Byapplying a positive bias to the diode gate, the base width WB ofthe pnp transistor expands under the gate and the gain is lowered.Conversely, for negative bias, it is the P+ area of the anode whichextends underneath the gate, reducing the resistance of the siliconlayer (under G2). Further analyzing Eq. (2), we note that the highdoping level in the base is the prevailing term, resulting in a verylow bipolar gain that can only marginally be affected by base widthand resistance reduction. This behavior is confirmed by the TLPresponse of the device shown in Fig. 19: there is minor modulationof the TLP characteristics as a function of VG2. The curves measuredwith VG2 = �1 V or VG2 = +1 V are superposed.

Another degree of flexibility is offered by the back gate (back-plane) biasing, albeit it is subject to super-coupling effectsobserved in UTBB FD-SOI process [14]. This is due to the existenceof both type of carriers inside the device (holes and electrons) dur-ing thyristor mode biasing (when MOSFET effect is not active). A

Over-voltage

Average area

Fig. 16. Device 6 TLP chronograms at different current values as indicated in Fig. 15for different pulse widths and rise times.

Fig. 19. Device 6. TLP 100 ns, RT 10 ns with different G2 biasing and VBP = 0 V.

large bias is needed on the back plane in order to achieve the sameresults as using the front-gate biasing (Fig. 20 compared withFigs. 17 and 18). This is due to the difference between the front

Fig. 20. Device 6. TLP 100 ns, RT 10 ns with different BP biasing for VG1 = VG2 = 0 V.

Fig. 21. ACS I–V TCAD simulation for devices 5 and 6. Top: Linear plot andcomparison with previous solution, Bottom: Semi log plot.



Fig. 22. Impact ionization during the ACS stress for device 5 with modified doping;at the trigger voltage point (t1) (TOP) at the end of the stress (BOTTOM).


gate oxide (EOT in the HKMG case) and the BOX oxide thicknesswith a coupling coefficient [15] tOX/tBOX = 0.136. The combinedgain of the 2 BJTs is limited once more by the high doping in themerged area (base) of the pnp LBJT, resulting in a lower gain forthe BJT formed with the gated diode. In the next section we will

show that doping calibration modulates the thyristor behaviorleading to radically change the ESD stress response.

5. Thyristor behavior through doping modification

One of the critical parameters of the GDNMOS is the dopingconcentration in the merged area. This area acts like the base ofthe p-n-p LBJT of the thyristor with its doping and width reverselyproportional to bipolar gain, as seen in Eq. (2). The doping profileselected for analysis in this section is compatible with the FD-SOIprocess and is equivalent to the LDD doping used in MOSFETS toreduce hot carrier effects by spreading the electric field [16]. TCADsimulations show a remarkable shift of around 2 V on the I–V curvewith snapback behavior, when this LDD doping is utilized insteadof the initial higher N+ doping (Fig. 21). The reason for this shiftis the increase in emitter efficiency and base transport factor ofthe gated diode LBJT for lower doping. Fig. 22 illustrates the impactionization rate at the beginning and at the end of the stress. It isinteresting to compare these results with those presented inFig. 8 for the device with higher doping in merged area, wherewe observe impact ionization generation through a larger volumeof silicon. With the new doping used the effect of impact ionizationis induced in a smaller volume of silicon activating avalanche mul-tiplication and triggering earlier with thyristor-like behavior.

6. Conclusion

In this work, we have introduced the ultrathin film GDNMOSdevice whose behavior was evaluated using both simulations andmeasurements on fabricated samples. No latch-up is observed,hence the device can be used for high-voltage protection. It bene-fits from simple integration on thin film and full process compli-ance. The ESD characteristics of GDNMOS can be further tunedby selecting a positive biasing for the nMOSFET gate as well asby changing the doping concentration of the merged area. TheGDNMOS shows promising characteristics and remarkable versa-tility for adoption in the FD-SOI technology.


Acknowledgements

We would like to thank N. Planes for FD-SOI wafer fabricationand procurement, Dr. Olivier Bon and the rest of ST mask genera-tion team for support. We would also like to thank our colleaguesDr. J. Bourgeat, B. Heitz and Dr. Nicolas Guitard for insight andexpertise that proved beneficial for this project. Support from EUproject WayToGoFast was highly appreciated.

References

[1] Planes N et al. 28 nm FDSOI technology platform for high-speed low-voltagedigital applications. In: Symposium on VLSI Technology (VLSIT), Jun 2012,Honolulu, US. p. 133–4. doi: http://dx.doi.org/10.1109/VLSIT.2012.6242497.

[2] Benoist T et al. Experimental investigation of ESD design window for fullydepleted SOI N-MOSFETs. Microelectron Eng 2011;88(7):1276–9. doi: http://dx.doi.org/10.1016/j.mee.2011.03.112.

[3] Golanski D et al. First demonstration of a full 28 nm high-k/metal gate circuittransfer from Bulk to UTBB FDSOI technology through hybrid integration. In:Symposium on VLSI Technology (VLSIT). p. T124–5. ISSN: 2158-5601.

[4] Galy Ph et al. BIMOS transistor in thin silicon film and new solutions for ESDprotection in FDSOI UTBB CMOS technology. In: EurosoiUlis 2015 Italy. p. 29–32. http://dx.doi.org/10.1109/ULIS.2015.7063765.

[5] Athanasiou S et al. Impact of back plane on the carrier mobility in 28 nm UTBBFDSOI devices, for ESD applications. In: EurosoiUlis 2015 Italy. p. 317–20.http://dx.doi.org/10.1109/ULIS.2015.7063837.

[6] Athanasiou S et al. Preliminary 3D TCAD electro-thermal Simulations of BIMOStransistor in thin silicon film for ESD protection in FDSOI UTBB CMOStechnology. In: ICICDT 2015. p. 1–4. http://dx.doi.org/10.1109/ICICDT.2015.7165913.

[7] Solaro Yohann et al. Innovative ESD protections for UTBB FD-SOI technology.In: Electron Devices Meeting (IEDM), Washington, US. p. 7.3.1–4. doi: http://dx.doi.org/10.1109/IEDM.2013.6724580.

[8] Synopsis Sentaurus TCAD, ver G-2012.06.[9] Jayant Baliga B. Fundamentals of power semiconductor devices. Springer

Publishing Company, Incorporated; 2008.[10] Galy Ph et al. Numerical evaluation between Transmission Line Pulse (TLP) and

Average Current Slope (ACS) of a submicron gg-nMOS transistor underElectrostatic Discharge (ESD). In: Workshop EOS/ESD/EMI, LAAS-CNRSToulouse. p. 15–7.

[11] Voldman Steven H. ESD physics and devices. John Wiley & Sons Ltd.; 2004.[12] Maloney T, Khurana N. Transmission line pulsing techniques for circuit

modeling of ESD phenomena. In: EOS/ESD symposium proceedings. pp. 49.[13] Athanasiou S et al. GDNMOS: a new high voltage device for ESD protection in

28 nm UTBB FD-SOI technology. In: EurosoiUlis 2016 Austria. p. 151–54.http://dx.doi.org/10.1109/ULIS.2016.7440075.

[14] Eminente S et al. Ultra-thin fully-depleted SOI MOSFETs: special chargeproperties and coupling effects. Solid State Electron 2007;51(2):239–44. doi:http://dx.doi.org/10.1016/j.sse.2007.01.016.

[15] Cristoloveanu S, Li Sheng S. Electrical characterization of SOl materials anddevices. Springer; 1995. doi: http://dx.doi.org/10.1007/978-1-4615-2245-4.

[16] Ogura et al. Design and characteristics of the Lightly Doped Drain-Source(LDD) insulated gate field-effect transistor. IEEE Trans Electron Dev 1980;27(8):1359–67. doi: http://dx.doi.org/10.1109/T-ED.1980.20040.

http://dx.doi.org/10.1109/VLSIT.2012.6242497

http://dx.doi.org/10.1016/j.mee.2011.03.112

http://dx.doi.org/10.1016/j.mee.2011.03.112







http://dx.doi.org/10.1109/ICICDT.2015.7165913

http://dx.doi.org/10.1109/ICICDT.2015.7165913














http://dx.doi.org/10.1007/978-1-4615-2245-4

http://dx.doi.org/10.1109/T-ED.1980.20040





Sharp-switching band-modulation back-gated devices in advancedFDSOI technology


⇑ Corresponding author at: STMicroelectronics, 850 rue Jean Monnet, 38926Crolles Cedex, France.

E-mail address: [email protected] (H. El Dirani).

Hassan El Dirani a,b,⇑, Pascal Fonteneau a, Yohann Solaro b, Charles-Alex Legrand a, David Marin-Cudraz a,Philippe Ferrari b, Sorin Cristoloveanu b

a STMicroelectronics, 850 rue Jean Monnet, 38926 Crolles Cedex, FrancebUniv. Grenoble Alpes, IMEP-LAHC, CNRS, F-38000 Grenoble, France




A band-modulation device with a free top surface, named Z3-FET (Zero front-gate, Zero swing slope andZero impact ionization) and fabricated in the most advanced Fully Depleted Silicon-On-Insulator technol-ogy, is demonstrated experimentally. Since the device has no front gate, the operation mechanism is con-trolled by two adjacent heavily doped buried ground planes acting as back-gates. Characteristics such assharp quasi-vertical switching, low leakage, and tunable trigger voltage are measured and discussed. Weexplore several variants (thin and thick silicon or SiGe body) and show promising results in terms of highcurrent, switching performance and ESD capability with relatively low back-gate and drain biasoperation.


1. Introduction

Fully Depleted Silicon On Insulator technology (FDSOI) featureshigh performance by reducing the parasitic capacitances, varyingthe threshold voltage with back-gate biasing, improving the leak-age, mobility and subthreshold swing (SS) [1,2]. In that context,devices with Ultra-Thin Body and Buried oxide (UTBB) attractincreasing attention for RF and IoT applications. In addition, FDSOItechnology benefits from simpler (planar) manufacturing processthan FinFETs, offering lower power consumption [3,4]. First intro-duced at the CMOS 28 nm node [1], the Z3-FET [5] (Zero gate, Zeroswing slope and Zero impact ionization) is a band-modulationdevice, like FED [6–8] and Z2-FET [9–11], but without top gates.The device is operated with back-gate voltage applied on two inde-pendent ground planes (GP). It exhibits ‘vertical’ switching, lowleakage current (ILeak), tunable triggering voltage (Vt1), and highON current (ION). For better electrostatic control, lower operatingvoltage, improved power consumption and further CMOS down-scaling, it is suitable to decrease the BOX and silicon film thick-nesses while making the source/drain terminals thicker (S/D)[12]. The impact of these parameters on Z3-FET is investigated inthis paper.

The device has been proposed recently [5] and further docu-mented in [13]. In this paper, we investigate in more detail thecharacteristics of Z3-FET fabricated with the most advanced,post-28 nm-node FDSOI technology [12]. The architecture, tech-nology description and the operation principle of Z3-FET aredescribed in Section 2. Section 3 is dedicated to the regular Z3-FET with undoped body. We discuss the impact of silicon filmthickness and temperature on the device performance, the capabil-ity to sustain high voltage and the response in the high currentregime. In Section 4, we introduce a doped variant of Z3-FET,explored with DC and high current TLP measurements.

2. Fabrication, architecture and principle of operation

2.1. Fabrication process

The proposed Z3-FET is fully compatible with FDSOI CMOS pro-cess flow. The process started from an SOI substrate with 20 nmBOX and 6 nm active Si layer thicknesses [12]. Variants consist ofthicker film (12 nm) and either Si or SiGe body. The thin buriedoxide separates the undoped film (NA = 1015 cm�3) from two highlydoped P and N type ground planes (with NA = ND = 1018 cm�3,respectively) acting as back-gates. In situ Si epitaxy (needed forreduced series resistance [14]) is performed only in source/drainregions. The processing of high-k dielectric and metal gate is omit-ted, making the device cost effective.







H. El Dirani et al. / Solid-State Electronics 128 (2017) 180–186 181

2.2. Device structure and operation mechanism

The Z3-FET is a forward biased P-I-N diode with an undopedultra-thin silicon film (tSi = 6 nm, Fig. 1a). The source (N+ doped)is grounded and the drain (P+ doped) is positively biased(VA > 0 V). Sharp switching is controlled by two separated groundplanes that act as back-gates (GP-N and GP-P in Fig. 1). The heavilydoped GPs are respectively positively (GP-N) and negatively (GP-P)biased. The device is normally OFF thanks to potential barriers thatblock the injection of electrons (from N+ source) and holes (from P+

drain) into the body. The twin GPs induce ‘electrostatic’ doping (N-type above GP-N and P-type above GP-P) and emulate a virtualNPNP thyristor structure. The placement and the biasing of thetwo ground planes is selected to form adequate injection barrierswhile maintaining the buried N+/P+ diode underneath the BOX inreverse mode for low leakage current. The triggering from OFFstate to ON state is achieved by increasing the anode voltage.When VA reaches Vt1, a positive feedback mechanism occurs dueto the flow of carriers from the anode to the cathode and vice versa,leading to a sudden collapse of barriers, as documented in [9]. Basi-cally, the carriers injected through one barrier lowers the height ofthe opposite barrier, via charge-induced change of body potential,initiating a positive feedback. This band-modulation mechanismresults in remarkable sharp transition from low to high current,and enables an ION/IOFF ratio of 8 decades (Figs. 2–4). Comparingto Z2-FET, the Z3-FET does not have high-k metal gate stack whicheliminates any issues related to high voltage reliability. The freesurface can be functionalized for various applications like bio, lightand radiation sensing. Another important feature of Z3-FET thatbenefits from the BOX as a gate oxide is the ability of sustaininghigh back-gate bias. These functionalities can be combined withthe typical applications of band-modulation devices (memory,ESD, fast logic), leading for example to sensors with built-inmemory.

Three variants have been fabricated. The first one has an ultra-thin silicon film (tSi = 6 nm), Fig. 1a. The second (Fig. 1b) and thethird (Fig. 1c) variants feature thicker Si film (tSi = 12 nm). The Lnpart of the third architecture (Fig. 1c) received optional highN-type doping. All structures have fixed width (300 lm).

Fig. 1. Schematic of Z3-FET architecture in advanced FDSOI technology

3. Z3-FET characterization and analysis

The fabricated devices were systematically characterized in sta-tic and pulsed (TLP) modes. In the following, the undoped versionof Z3-FET is explored with variable silicon film thickness (6 nm and12 nm) and different types of channel doping (Si in Fig. 2a and band SiGe in Fig. 2c). VGbP and VGbN represent the back GP-P andGP-N biases, respectively.

3.1. DC characteristics and hysteresis

Figs. 2–4 show the typical output device characteristics: sharpswitch, low leakage current, tunable triggering voltage Vt1 and hys-teresis. The need to keep the PIN diode in OFF state requires robustbarriers that block the injection of carriers into the channel. Inultrathin devices, the Lp barrier is strong enough even at VGbP = 0 Vfeaturing a very low leakage current (ILeak < 10�11 A) but degradedsharp switching. A thicker film (tSi = 12 nm) is needed to reinforcethe electron barrier while negatively biasing the GP-P (VGbP = 2 V).The sharp switch is recovered for VGbN P 1 V, as shown in Fig. 2b.

The feedback between the barriers is affected by the silicon filmthickness. In ultrathin films, the recombination rate of carriersincreases, as dominated by the interfaces, and the effective carrierlifetime decreases. Numerical simulations with reduced carrierlifetime confirmed the degradation of the switch sharpness [5].In order to trigger the feedback mechanism between the barriersand retrieve the sharp switch, two solutions have been tested.The first approach consists in negatively biasing the GP-P; how-ever, VGbP = �2 V is not sufficient to retrieve the sharp switchand the characteristics are similar to those in Fig. 2a. It seems thatthe lifetime is too short and does not allow the carriers injectedthrough one barrier to reach the second barrier and initiate thefeedback mechanism. The second solution is to increase the filmthickness from 6 nm to 12 nm; a steep switch over >6 decades ofcurrent is indeed observed in Fig. 2b. With SiGe body, the barriersare weaker and the carriers can be injected more easily than indevices with Si channel. This leads to a slight reduction of trigger-ing voltage Vt1, as seen in Fig. 2c, that is attractive for low-powercircuits.

: (a) tSi = 6 nm, (b) tSi = 12 nm and (c) partially N-doped channel.

Fig. 2. Experimental DC IA-VA characteristics for different GP-N biases in Z3-FETs with (a) thin film tSi = 6 nm and VGbP = 0 (similar curves for VGbP = �2 V); (b) thicker filmtSi = 12 nm and VGbP = �2 V; (c) thicker SiGe body tSiGe = 12 nm and VGbP = �2 V. Ln = Lp = 200 nm. The saturation of ON current is an artefact due to the 1 mA currentcompliance used in the setup.

Fig. 3. IA-VGbN transfer characteristics for various anode bias VA in Z3-FET with (a) ultrathin body and (b) thicker body. Ln = Lp = 200 nm, 1 mA current compliance.

Fig. 4. Variation of triggering voltage Vt1 with GP-N bias for (a) ultrathin body tSi = 6 nm at VGbP = 0 V and (b) thicker body tSi = 12 nm at VGbP = �2 V.

182 H. El Dirani et al. / Solid-State Electronics 128 (2017) 180–186

The transfer characteristics IA-VGbN is shown in Fig. 3 whichconfirms the ability of the Z3-FET to switch from a low current inOFF state (IOFF < 10�13 A) to a high current in ON state (ION > 10�3 A).While the ultrathin (6 nm) Z3-FET shows �90 mV/decade sub-threshold swing (Fig. 3a), the thicker (12 nm) device exhibits asharp switch (Fig. 3b). A higher anode voltage further improvesthe switching performance. Similar vertical slope characteristicsare obtained by back-sweeping VGbP as shown in [5]. The Z2-FET,governed by its front-gate, features a sharper OFF to ON state tran-

sition (�1 mV/decade [10,11,15–17]) than the Z3-FET (DVGbN/DIA = 7 mV/decade, Fig. 3b), which is operated by the back-gatesthrough a thick oxide (BOX). The turn-on voltage is controlled bythe potential difference between the anode and GP-N (VA � VGbN).As VA increases, a higher VGbN is needed to block the device, asshown in Fig. 3b.

As VGbN increases, the holes injection barrier is stronger,hence a higher Vt1 is needed to turn on the device. The evolutionof triggering voltage with VGbN is presented in Fig. 4a and b,

Fig. 5. Output IA-VA curves showing sharp switching and gate controlled hysteresisfor various VGbN. VGbP = �1 V, Ln = Lp = 200, tSi = 12 nm, 1 mA current compliance.


showing that Vt1 is very sensitive to the back-gate bias (DVt1/DVGbN = 900 mV/V).

In ultrathin devices with grounded GP-P, the impact of thechannel length on the triggering voltage Vt1 is low (Fig. 4a). Onthe other hand, devices with thicker tSi need a negative VGbP = �2 Vto achieve the sharp switch. The strong coupling between the GPbias and the channel makes the ON voltage Vt1 adjustable up to2 V. This coupling effect reduces as device length decreases (hexa-gon symbols, Fig. 4b) because the barriers are weaker.

In the following, we discuss the hysteresis. The output IA-VA

curves in Fig. 5 show that the device is in OFF state at relativelylow bias (VA < 2 V) and turns ON sharply when VA reaches the trig-gering voltage Vt1. As VA is swept back, a small anti-clockwise hys-teresis is observed until VA is able to turn the device OFF. Since therobustness of Ln barrier is improved with VGbN, the triggering volt-age is increased and the hysteresis window is enlarged, as illus-trated in Fig. 5.

It is important to note that the electrostatic control of the devicebarriers can decrease with increasing the reverse bias of the diodeformed by the GPs (see Section 3.3). In this case, the barriers arerelatively weaker and the OFF state is retrieved for lower sweep-back VA. As a result, the hysteresis window is wider, which is ben-

Fig. 6. (a) DC IA-VA curves for two temperatures: high temperature T = 125 �C (red sqVGbP = �2 V. (b) Vt1 versus GP-N bias at T = 25 �C and 125 �C. (c) Variation of DVt1/DT withcolor in this figure legend, the reader is referred to the web version of this article.)

eficial for promoting the Z3-FET as a competitor of 1T-DRAMmemory.

3.2. Impact of operating temperature

Some applications require high device performance in a widetemperature range. For that purpose, the Z3-FET was characterizedat room temperature and high temperature (125 �C). Fig. 6 showsthat the Z3-FET is also functional at high temperature. The switchfrom OFF to ON state is slightly affected by the operating temper-ature, as seen in Fig. 6a. Fig. 6b shows that the reduction of Vt1 isequal to 0.4 V (DVt1/DT = �3 mV/�C). However, the quasi-lineardependence of Vt1 on VGbN is maintained from room temperatureup to 125 �C. The Vt1 variation also increases when reducing thedevice length (�5 mV/�C for Ln = Lp = 200 nm and �2 mV/�C forLn = Lp = 500 nm), as presented in Fig. 6c. Finally, the ION/IOFF ratio,108 at room temperature, reduces to 107 at 125 �C, since the ther-mal energy of carriers increases at higher temperature [17,18] andthey can easily cross the device from node to node. Consideringthese results, it can be concluded that the small temperature-dependence of Z3-FET is an asset for ESD protection schemes.

3.3. High voltage

The advantage of having the triggering voltage modulated bythe GPs allows using the Z3-FET as a high voltage device. IncreasingVGbN to 7 V requires in principle a higher anode voltage VA to turnON the device. However, the actual mechanism is more subtle anddepends on the channel length, as shown in Fig. 7. In long Z3-FET,Vt1 (VGbN) is a monotonic function (Fig. 7a), whereas in short deviceVt1 decreases for VGbN higher than 5 V (Fig. 7b). This means that thehole injection barrier starts to shrink for VGbN > 5 V, which seemscounter-intuitive. We explain this surprising effect by the expan-sion of the depletion region of the reverse-biased diode formedby the two GPs below the BOX. The width Wdep of the junctiondepletion region is calculated for different doping concentrationsin Fig. 7c. In the studied case (NA = ND = 1018 cm�3 for GP-P and

uare symbols) and room temperature (blue circle symbols) for various VGbN anddevice length. tSi = 12 nm, 1 mA compliance. (For interpretation of the references to

Fig. 7. Current versus anode voltage measured for GP-N bias reaching high voltage in (a) short Z3-FET, Ln = Lp = 200 nm and (b) long Z3-FET, Ln = Lp = 500 nmwith VGbP = �1 V.(c) Evolution of lateral depletion width between the GPs versus reverse bias VGP = VGbN � VGbP for different doping concentrations. tSi = 12 nm.

Fig. 8. TLP characterization results. (a) IA-VA curves in short and long Z3-FETs for 5 ns pulse width (open symbols) and 100 ns (closed symbols) with native rise time(�300 ps), VGbN = 2 V and VGbP = �2 V. (b) Variation of failure current It2 with device length for 5 ns and 100 ns pulse width. tSi = 12 nm.

Fig. 9. Non-destructive TLP measurements for 100 ns pulse width in short (solidlines) and long (dotted lines) Z3-FETs for VGbN = 2 V and various GP-P bias.tSi = 12 nm.


GP-N respectively), the depletion zone reaches 150 nm at VGP =VGbN � VGbP = 8 V. Thus the electrostatic control of the GPs on thechannel decreases, implying narrower barriers and a Vt1 reductionfor VGP > 5 V, as noticed in Fig. 7b. The channel control is retrievedby increasing the device length (Ln = Lp �Wdep). The long Z3-FET(Ln = Lp = 500 nm, Fig. 7a) can sustain high anode voltage up to8 V without device breakdown. A second solution is to use heavierdoping in GPs: for NA = ND = 1019 cm�3, the space charge region ofthe diode falls down below 40 nm even at high voltage (Fig. 7c).However, overdoping the ground planes (by ion implantation)may also affect the body doping. Note that the diode formed bythe two GPs is always reversed biased and exhibits negligible leak-age current.


The ESD behavior was investigated with transmission line pulse(TLP) characterization [19,20]. We used different pulse widths(tPW = 5 and 100 ns) and native rise time (�300 ps). Typical mea-surements are shown in Fig. 8. The high current regime is domi-nated by self-heating where the temperature rise degrades themobility and eventually leads to thermal runaway causing device

breakdown. As noticed in Fig. 8a, the heating is reduced for shorterpulse widths, where the failure current It2 of short Z3-FET (Lp =

Fig. 10. Current versus drain voltage measured for (a) different geometries at VGbN = VGbP = 0 V and (b) various VGbP bias (Ln = 200 nm, LP = 150 nm at VGbN = 0 V). Doped Z3-FETs with tSi = 12 nm.

Fig. 11. TLP IA-VA characteristics for 5 ns (open symbols) and 100 ns (closedsymbols) pulse width with native rise time (�300 ps). N-doped Z3-FET with Lp =Ln = 200 nm and VGbN = VGbP = 0 V. tSi = 12 nm.


Ln = 200 nm) is improved from 4.9 mA/lm for tpw = 100 ns up to7.6 mA/lm for tpw = 5 ns. The maximum current value and the trig-gering voltage Vt1 depend on device length. Shorter Z3-FETs showimproved performance: easier triggering with smaller Vt1 andhigher current capability (Fig. 8a). The evolution of failure currentIt2 with device length is presented in Fig. 8b. It is confirmed that It2increases for shorter pulse widths and decreases with the devicelength. Thanks to the high performance, even at tpw = 100 ns, Z3-FET stands as a viable candidate for protection against HBM-type(Human Body Model) ESD events.

Fig. 9 confirms that the triggering voltage of the device is tun-able not only by GP-N but also by GP-P bias and device length.The higher the |VGbP| bias, the larger the triggering voltage. Takingadvantage of these adjustable parameters, our devices are able tofulfill the ESD design window requirements showing ultra-lowleakage current, high failure current and abrupt switching.

4. Doped Z3-FET

The undoped variant of Z3-FET features excellent performancebut requires a negative bias on GP-P and a positive bias on GP-N,which is unsuitable in some applications. In order to address thisissue, a new variant has been fabricated with a highly doped Lnpart of the channel (Fig. 1c). The device behavior is discussed inthe following section.

4.1. Static DC leakage characteristics

The IA-VA characteristics of the doped Z3-FET are presented inFig. 10 for different geometries (Fig. 10a) and various VGbP bias val-ues (Fig. 10b). The N-doped Ln region of the channel forms a natu-ral strong barrier against hole injection, avoiding the positive bias

of the GP-N. Hence, the device is blocked even without back-gatebias (Fig. 10a). By contrast, the Lp region is left undoped and showsa clear dependence on GP-P bias (Fig. 10b). In short devices, theGP-N barrier is narrow and cannot prevent completely the injec-tion of holes toward the cathode. Since at VGbP = 0 V the GP-P bar-rier is weak, the leakage current is too high. In order to avoidleakage, the device length can be increased (Fig. 10a). An alterna-tive solution, effective in both short and long devices, is to nega-tively bias the GP-P (Fig. 10b). When the barriers are broader(long device) and higher (VGbP < 0), the triggering voltage increasesas shown in Fig. 10a.


Fig. 11 shows the S-shaped negative-resistance characteristicfor the partially N-doped device with no back-gate bias which isan important feature for ESD chip designers. Compared to undopeddevice with the same length (Lp = Ln = 200 nm, Fig. 8a), the dopedZ3-FET exhibits a higher triggering voltage (Vt1 = 2.5 V in Fig. 11)with similar failure current It2 = 7.2 mA/lm. Nevertheless, thedynamic resistance RON is increased in doped devices due to thehigh recombination rate in the channel.

5. Conclusion

A gateless band-modulation device (Z3-FET) was proposed anddemonstrated experimentally in the most advanced FDSOI tech-nology. Several variants with different silicon film thicknessesand doping levels were studied. High performance in terms of trig-gering, leakage current and failure current have been reported. Forproper operation, the film thickness is very important, thickerdevices showing sharper characteristics. Experiments showed thatthe Z3-FET characteristics are weakly dependent on temperature.Finally, the high regime current, investigated with TLP measure-ments, confirmed that Z3-FETs can serve as robust ESD protectionelement, high-voltage device, 1T-DRAM memory and, thanks tothe absence of the top gate, as ion-, photo-, and radiation sensors.

Acknowledgements

The layout, process and ESD/LU teams at STMicroelectronics arethanked for helpful support and fruitful discussions. We also thankthe European project WayToGoFast for financial support.

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[14] Fenouillet-Beranger C, Denorme S, Perreau P, Buj C, Faynot O, Andrieu F, et al.FDSOI devices with thin BOX and ground plane integration for 32 nm node andbelow. Solid State Electron 2009;53(7):730–4.

[15] Wan J, Le Royer C, Zaslavsky A, Cristoloveanu S. A systematic study of thesharp-switching Z2-FET device: from mechanism to modeling and compactmemory applications. Solid State Electron 2013;90:2–11.

[16] Solaro Y, Wan J, Fonteneau P, Fenouillet-beranger C, Le Royer C, Zaslavsky A,Ferrari P, Cristoloveanu S. Z2-FET as a novel FDSOI ESD protection device. SolidState Electron 2014;97:23–9.

[17] El Dirani H, Solaro Y, Fonteneau P, Ferrari P, Cristoloveanu S. Properties andmechanisms of Z2-FET at variable temperature. Solid State Electron2015:8–13.

[18] Rodriguez N, Andrieu F, Navarro C, Faynot O, Gamiz F, Cristoloveanu S.Properties of 22 nm node extremely-thin-SOI MOSFETs. In: Int SOI Conf. IEEE;2011. p. 1–2.

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Electrical characterization and modeling of 1T-1R RRAM arrays withamorphous and poly-crystalline HfO2


⇑ Corresponding author.E-mail address: [email protected] (A. Grossi).

1 Universitat Autònoma de Barcelona (UAB), Departament d’Enginyeria Electrònica,08193 Bellaterra, Spain.

2 IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany.

Alessandro Grossi ⇑, Cristian Zambelli, Piero Olivo, Alberto Crespo-Yepes 1, Javier Martin-Martinez 1,Rosana Rodríguez 1, Monserrat Nafria 1, Eduardo Perez 2, Christian Wenger 2

Università degli Studi di Ferrara, Dip. di Ingegneria, Via Saragat 1, Ferrara 44122, Italy




Keywords:RRAM arrayFormingRead windowEnergy saving

a b s t r a c t

In this work, a comparison between 1T-1R RRAM arrays, manufactured either with amorphous or poly-crystalline Metal–Insulator–Metal cells, is reported in terms of performance, reliability, Set/Reset opera-tions energy requirements, intra-cell and inter-cell variability during 10k endurance cycles and 100k readdisturb cycles. The modeling of the 1T-1R RRAM array cells has been performed with two differentapproaches: (i) a physical model like the Quantum Point Contact (QPC) model was used to find the rela-tionship between the reliability properties observed during the endurance and the read disturb tests withthe conductive filament properties; (ii) a compact model to be exploited in circuit simulations toolswhich models the I–V characteristics of each memory cells technology.


1. Introduction

Resistive Random Access Memories (RRAM) technology gath-ered significant interest for several applications [1–3]. RRAMbehavior is based on the possibility of electrically modifying theconductance of a Metal–Insulator–Metal (MIM) stack: the Set oper-ation moves the cell in a low resistive state (LRS), whereas Resetbrings the cell in a high resistive state (HRS) [4,5]. To activate sucha switching behavior, some technologies require a preliminaryForming operation [6–8].

The choice of a proper Metal-Insulator–Metal (MIM) technologyfor RRAM cells, exhibiting good uniformity and low switching volt-ages, is still a key issue for array structures fabrication and reliableelectrical operation [9]. Such a process step is mandatory to bringthis technology to a maturity level. In this work, a comparisonbetween 1T-1R RRAM 4kbits arrays manufactured either withamorphous [5] or poly-crystalline [10] HfO2 is performed. In amor-phous HfO2 the conduction mainly occurs through a conductive fil-ament with a variable concentration of defects, whereas in poly-crystalline HfO2 the conduction occurs only through grain bound-aries with a very low defect concentration. The differences in termsof conduction properties and defect concentrations translate into

different switching properties [9], with several implications oninter-cell variability (variations between cells) and intra-cell vari-ability (cycle-to-cycle variations of any given cell).

In this work, that is an extended yet complete picture of theresults presented in [11], a comparison in terms of performance,reliability, Set/Reset operations energy requirements, intra-celland inter-cell variability during 10k endurance cycles is reported.In addition to the previously presented results, 100k read disturbcycles were performed to deepen the understanding of the reliabil-ity of each technology. Moreover, to understand the relationshipbetween the reliability properties observed during the enduranceand read disturb tests and the conductive filament properties,Quantum Point Contact (QPC) modeling [12] was used, since itallows to correctly represent the measured I–V characteristicsindependently from the conduction mechanism. Even if the QPCallows to model the conductive filaments properties taking intoaccount the cell-to-cell variability, it offers a technology descrip-tion that sometimes is complex to be implemented in circuit sim-ulation tools. To this extent, an equivalent circuit model able tooffer a simpler description of the devices was applied and validatedon both MIM technologies. The memory cells used in this work canbe modeled using a diode-resistance equivalent circuit model. Themodel parameters extracted from the fittings of experimental I–Vcurves can provide additional information about electrical proper-ties of the memory cells to be exploited in the design of RRAMarrays.







188 A. Grossi et al. / Solid-State Electronics 128 (2017) 187–193

2. Experimental setup

The 1T-1R memory cells in the 4kbits arrays are constituted bya select NMOS transistor manufactured with a 0.25 lm BiCMOStechnology whose drain is in series to a MIM stack. The wordline(WL) voltage applied to the gate of the NMOS transistor allows set-ting the cell current compliance. The cross-sectional ScanningTransmission Electron Microscopy (STEM) image of the cell andthe 1T-1R cell schematic are reported in Fig. 1. The variable MIMresistor is composed by 150 nm TiN top and bottom electrode lay-ers deposited by magnetron sputtering, a 7 nm Ti layer, and a 8 nmHfO2 layer deposited with two different Atomic Vapour Deposition(AVD) processes resulting either in amorphous (A) or poly-crystalline (P) HfO2 films, respectively. The resistor area is equalto 0.4 lm2. Amorphous films have been integrated also with aresistor area equal to 1 lm2. This latter process option showsimproved reliability and performance [4]. The Forming/Set/Resetoperations on the arrays were performed by using an IncrementalPulse and Verify algorithm. The bitline (BL), sourceline (SL) and WLvoltages applied during Forming, Set, Reset and Read operationsare reported in Table 1. Reset operations were performed by apply-ing the highest WL voltage available (2.8 V on array A and 2.5 V onarray P) to maximize the cells switching yield while avoiding thebreakdown of the MIM [13]. Pulses were applied during Formingby increasing VBL with DVBL = 0.01 V, whereas during Set and ResetDVBL = 0.1 V and DVSL = 0.1 V have been used, respectively. Eachpulse featured a duration of 10 ls, with a rise/fall time of 1 ls toavoid overshoot issues. Set operation was stopped on a cell whenthe read-verify current reached 20 lA, whereas Reset was stoppedwhen 10 lA was reached. Forming, Set and Reset BL/SL voltagesnecessary to reach the requested read-verify current targets areextracted from the characterization data and labelled as VFORM, VSET

and VRES, respectively.


Arrays using A-HfO2 (A-array) with resistor area of 0.4 lm2,1 lm2 and P-HfO2 (P-array) resulted in a Forming Yield (calculated

Fig. 1. Cross-sectional STEM image (a) and schematic (b) of the 1T-1R cellintegrated in the arrays.

Table 1Forming, set, reset and read voltage parameters.

Operation VSL [V] VBL [V] VWL [V]

Forming 0 2–3.2 1.5Set 0 0.2–3.2 1.5Reset 0.2–3.2 0 2.5 (A)/ 2.8 (P)Read 0 0.2 1.5

as the cell percentage showing a read verify current after formingIread P 20 lA) of 58%, 90% and 95%, respectively. Fig. 2 shows theaverage current ratios between Low Resistive State (LRS) and HighResistive State (HRS) read currents (ILRS/IHRS), calculated on theentire cells population during SET/RESET cycling at Vread = 0.2 Von A-array and P-array, and their relative dispersion coefficient.The minimum current ratio that allows to correctly discriminatebetween HRS and LRS, defined as ILRS/IHRS > 2, is indicated for com-parison [5]. The average ratios of A-arrays with resistor area of0.4 lm2 and 1 lm2 go under the minimum ratio limit after 200and 1k cycles, respectively. To evaluate the cell-to-cell variabilitythe dispersion coefficient of ILRS and IHRS distributions, defined as(r2=l), has been used. P-array showed higher Ratio (�2.8) evenafter 10k cycles, but also a higher dispersion coefficient after Form-ing (i.e., cycle 1). The grain boundaries conduction mechanism inthe poly-crystalline HfO2 structure could be the reason of thehigher cell-to-cell variability in P-arrays [14]. A-array with resistorarea of 1 lm2 shows a slightly higher average ratio than A-arraywith resistor area of 0.4 lm2.

Fig. 3 shows a comparison between ILRS and IHRS cumulative dis-tributions measured at cycle 1 and after the endurance test: A-arrays show more compact distributions at cycle 1, however afterthe endurance test P-array shows a higher percentage of correctlyswitching cells reaching the Set/Reset verify targets. IHRS cumula-tive distribution in P-array show a longer tail at cycle 1 comparedto A-arrays. After 10k cycles only an increase of the tail in P-arraycan be observed whereas on A-arrays a strong shift of the distribu-tions towards higher currents occurs, resulting in a higher numberof cells not reaching the Reset threshold. IHRS cumulative distribu-tion in A-array with resistor area of 1 lm2 shows lower currents atcycle 1 than A-arrays with resistor area of 0.4 lm2, however after10k cycles IHRS cumulative distributions are very similar. In ILRScumulative distributions a tail creation of cells not able to reachthe Set threshold can be observed on P-arrays after 10k cycles,whereas on A-arrays a strong shift of the distributions towardslower currents occurs, resulting in a higher number of cells notreaching the Set threshold especially when cells with resistor areaof 0.4 lm2 are considered. A-array with resistor area of 0.4 lm2

shows a high number of cells not reaching the Set threshold evenat cycle 1.

Fig. 4 shows the average Set and Reset switching voltages (VSET,VRES) and their relative dispersion coefficients: lower VSET and VRES

are required on P-array which shows no variations during theendurance test, whereas VSET, VRES increase on A-arrays duringcycling. VRES on P-array shows the highest variability. A-arraysshow similar behavior of the average VSET and VRES (a lower averageVSET is observed on A-array with larger resistor area only up to 500

100

101

102

103

104

Switching Cycles

0

0.5

1

1.5

2

2.5

3

3.5

4

I LR

S/I

HR

S

A (1μm2)

A (0.4 μm2)

P (0.4 μm2)

Min. Ratio

(a)

100

101

102

103

104

Switching Cycles

0

2

4

6

8

10

12

14

16

I LR

S/I

HR

S D

isp.

Coe

ff.

A (1 μm2)

A (0.4 μm2)

P (0.4 μm2)

(b)

Fig. 2. ILRS/IHRS current ratio average values (a) and dispersion coefficients (b)calculated during cycling.

0

IREAD [μA]

0102030405060708090

100C

umul

ativ

e P

roba

bilit

y [%

]

HRS (A, 1μm2)

LRS (A, 1μm2)

HRS(A, 0.4μm2)

LRS (A, 0.4μm2)

HRS (P, 0.4μm2)

LRS (P, 0.4μm2)

RESETVerify Target

FORM/SETVerify Target

(a)

0

10 20 30 40

10 20 30 40

IREAD [μA]

0102030405060708090

100

Cum

ulat

ive

Pro

babi

lity

[%]

HRS (A, 1μm2)

LRS (A, 1μm2)

HRS (A, 0.4μm2)

LRS (A, 0.4μm2)

HRS (P, 0.4μm2)

LRS (P, 0.4μm2)

RESETVerify Target

FORM/SETVerify Target

(b)

Fig. 3. IHRS and ILRS cumulative distributions at cycle 1 (a) and at cycle 10k (b).

100

101

102

103

104

Switching Cycles

0

0.5

1

1.5

2

2.5

3

VSE

T [

V]

VSET(A, 1 μm2)

VSET(A, 0.4 μm2)

VSET(P, 0.4 μm2)

(a)

100

101

102

103

104

Switching Cycles

0

0.1

0.2

0.3

0.4

VSE

T D

isp.

Coe

ff.

VSET(A, 1 μm2)

VSET(A, 0.4 μm2)

VSET(P, 0.4 μm2)

(b)

100

101

102

103

104

Switching Cycles

1

1.5

2

2.5

3

VR

ES [

V]

VRES(A, 1 μm2)

VRES(A, 0.4 μm2)

VRES(P, 0.4 μm2)

(c)

100

101

102

103

104

Switching Cycles

0

0.05

0.1

0.15

0.2

0.25

VR

ES D

isp.

Coe

ff.

VRES(A, 1 μm2)

VRES(A, 0.4 μm2)

VRES(P, 0.4 μm2)

(d)

Fig. 4. VSET and VRES average values (a,b) and dispersion coefficients (c,d) calculatedduring cycling.

A. Grossi et al. / Solid-State Electronics 128 (2017) 187–193 189

cycles), while a higher VSET and VRES dispersion can be observed inA-array with smaller resistor area.

Fig. 5 shows the cumulative distributions of Forming, Set andReset switching voltages at cycle 1 and after the endurance test:Forming,Set and Reset algorithms starting point and last attemptare indicated, corresponding to the first and the last voltage pulseavailable in the incremental pulse and verify procedure. P-arrayrequires lower VSET and VRES but higher VFORM if compared to A-array with the same resistor area. A-array with larger resistor arearequires higher VFORM, moreover it can be observed that �40% ofthe devices with smaller resistor area reached the forming thresh-old at VFORM = 2 V, corresponding to the first attempt of the Form-ing Algorithm. Since P-array shows a more compact distributionon VSET and a larger VRES than A-arrays, faster Set operation couldbe reliably used on P-array, whereas on Reset an incremental pulse

VFORM [V]

0102030405060708090

100

Cum

ulat

ive

Pro

babi

lity

[%]

Forming Algorithm Start

FormingAlgorithmLast Attempt

A, 1μm2

A, 0.4μm2

P, 0.4μm2

(a)

VSET, VRES [V]

0102030405060708090

100

Cum

ulat

ive

Pro

babi

lity

[%]

A, 0.4μm2

A, 1μm2

P, 0.4μm2

SETRES

Set/ResetAlgorithm Start

Set/ResetAlgorithmLast Attempt

(b)

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

VSET, VRES [V]

0102030405060708090

100

Cum

ulat

ive

Pro

babi

lity

[%]

A, 0.4μm2

A, 1μm2

P, 0.4μm2

SETRES

Set/ResetAlgorithm Start

Set/ResetAlgorithmLast Attempt

(c)

Fig. 5. VFORM, VSET and VRES cumulative distributions at cycle 1 (a) and at cycle 10k(b).


with verify technique is required to ensure good reliability. A-arrays show large distributions on both VSET and VRES, hence theadaptation of incremental pulse with verify techniques is manda-tory on such arrays.

Fig. 6 shows the average energy required to perform Set andReset operations on a single cell: P-array shows lower power con-sumption with a lower increase during cycling. A-arrays with dif-ferent resistor area show similar power consumption duringReset operation, whereas a lower consumption during Set isobserved on A-array with larger resistor area only up to 500 cycles.The overall energy required to create/disrupt the conductive fila-ment during Set/Reset operations has been calculated as:

E ¼X

n

i¼1

Vpulse;i � Ipulse;i � Tpulse þ Vread � Iread;i � Tread ð1Þ

where n is the number of Reset pulses applied during incrementalpulse operation, Vpulse;i is the pulse voltage applied at step i; Ipulse;iis the current flowing through RRAM cell during pulse i application,Tpulse ¼ 10 ls is the pulse length, Vread ¼ 0:2 V is the read voltageapplied during verify operation, Iread;i is the current read during readverify step i, and Tread ¼ 10 ls is the verify pulse length.

In the considered RRAM cells the read signals has the samepolarization of the Set operation (both pulses are applied on theBL), hence the read disturb could only be a problem on cells inHRS state since a very long sequence of read pulses could slowlyre-create the conductive filament, resulting into an undesiredswitch from HRS to LRS [13]. Read disturb has been evaluated onlyon cells in HRS state for each considered technology: Fig. 7 showsthe average HRS read current and its relative standard deviation

100

101

102

103

104

Switching Cycles

0

10

20

30

40

50

60

SET

Ene

rgy

[nJ]

A (1 μm2)

A (0.4 μm2)

P (0.4 μm2)

(a)

100

101

102

103

104

Switching Cycles

0

10

20

30

40

50

60

RE

S E

nerg

y [n

J]

A (1 μm2)

A (0.4 μm2)

P (0.4 μm2)

(b)

Fig. 6. Energy required to perform Set (a) and Reset (b) operations as a function ofthe Set/Reset cycle number.

100

101

102

103

104

105

Read Cycles

6

8

10

12

I HR

S [μA

]

A, 1 μm2

A, 0.4 μm2

P, 0.4 μm2

(a)

100

101

102

103

104

105

Read Cycles

0

2

4

6

8

I HR

S D

ispe

rsio

n C

oeff

.

A, 1 μm2

A, 0.4 μm2

P, 0.4 μm2

(b)

Fig. 7. Average read current variation (a) and dispersion coefficient evolution (b) ofHRS calculated during 100k read disturb pulses, with Vpulse ¼ 0:2 V.

measured during 100k read operations. P-array shows the highestread current variation, confirming that on such technology due tothe high leakage currents it is easier to create conductive paths.

4. 1T-1R cells modeling

Extracting and modeling suitable parameters for the I–V charac-teristics is important to gather statistical information for any kindof non-volatile memory [15]. In the RRAM arrays of this work, I–Vcharacteristics have been measured after-forming and modeledwith two different approaches: in order to understand the differ-ences on the conductive filament properties and variability QPCmodeling has been used as in [16], while an equivalent circuitmodel [17] was used to obtain a description implementable in cir-cuit simulation tools.

4.1. QPC modeling

Reset I–V characteristics measured after-forming were used toanalyze the conductive filament properties through QPC model.HRS current is calculated according to the expression:

I ¼ 2ehG=G0 eVþ 1

aLn

1þ eaðU�beVÞ

1þ ea½Uþð1�bÞeV�

� ��

ð2Þ

where U is the barrier height (bottom of the first quantized level),

a ¼ tBp2h�1 ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

2m�=Up

is a parameter related to the inverse of thepotential barrier curvature (assuming a parabolic longitudinalpotential), m� ¼ 0:44m0 is the effective electron mass and tB is thebarrier thickness at the equilibrium Fermi energy. b takes intoaccount how the potential drops at the two ends of the filament:b ¼ 1 has been used since the constriction is highly asymmetric[16]. G=G0 is a conductance parameter equivalent to the numberof filaments at very low voltages: in a very approximate way, a sin-gle highly conductive filament can be viewed as a parallel combina-tion of elementary nanowires [18].

I–V Reset operation has different impacts from cell-to-cell,resulting either into a break or a modulation of the conductive fil-ament (CF) [8,16]. In the former case the presence of a potentialbarrier is assumed, hence fitting is performed consideringG=G0 ¼ 1 and the average barrier length d and radius of the con-striction r are calculated according to [12]. In the latter case,assuming the absence of a potential barrier, the normalized con-ductance of the filament G=G0 is calculated. The percentage of cellsresulting either into a CF break or modulation are reported inTable 2: the high leakage current in P-array makes very difficultto completely interrupt the conductive path hence the lowest per-centage of CF break is obtained, whereas the highest percentage isobtained on A-array with the larger resistor area. The cumulativedistributions of a and U fitting parameters calculated on the CFbreak cells are reported in Fig. 8.

Average value and standard deviation of the fitting parametersare reported in Table 3. The cumulative distributions of calculatedbarrier length d and radius r of the CF constriction are reported inFig. 9, while the average value and standard deviations arereported in Table 4. A-array with the small resistor area showsthe largest radius with the lowest barrier length: the presence of

Table 2Reset condition comparison.

Technology C.F. Break [%] C.F. Modulation [%]

A, 1 lm2 45 55

A, 0.4 lm2 34 66

P 0.4 lm2 20 80

0 5

α [eV]-1

0102030405060708090

100

Cum

ulat

ive

Pro

babi

lity

[%]

A, 1 μm2

A, 0.4 μm2

P, 0.4 μm2

(a)

10 15 20 0.0 0.5 1.0 1.5 2.0

φ [eV]

0102030405060708090

100

Cum

ulat

ive

Pro

babi

lity

[%]

A, 1 μm2

A, 0.4 μm2

P, 0.4 μm2

(b)

Fig. 8. Cumulative distribution of a and U fitting parameters used on CF break cells.

Table 3Average value and standard deviation of fitting parameters calculated on CF breakcells.

Technology a ½eV��1 / ½eV�

Avg. Std. Avg. Std.

A, 1 lm2 2.67 3.02 1.21 0.58

A, 0.4 lm2 6.83 5.48 0.07 0.06

P, 0.4 lm2 16.08 5.06 0.17 0.25

d [nm]

0102030405060708090

100

Cum

ulat

ive

Pro

babi

lity

[%]

A, 1 μm2

A, 0.4 μm2

P, 0.4 μm2

(a)

0.0 0.5 1.0 1.5 2.0 0.0 2.0 4.0 6.0 8.0

r [nm]

0102030405060708090

100

Cum

ulat

ive

Pro

babi

lity

[%]

A, 1 μm2

A, 0.4 μm2

P, 0.4 μm2

(b)

Fig. 9. Cumulative distribution of calculated barrier length d (a) and radius of thefilament constriction r (b) on CF break cells.

Table 4Average value and standard deviation of barrier length and filament radius calculatedon CF break cells.

Technology d [nm] r [nm]

Avg. Std. Avg. Std.

A, 1 lm2 0.37 0.11 0.85 0.62

A, 0.4 lm2 0.25 0.24 4.25 2.25

P, 0.4 lm2 1.29 0.36 1.71 0.65

1.0 1.5 2.0 2.5 3.0

G/G0

0102030405060708090

100

Cum

ulat

ive

Pro

babi

lity

[%]

A, 1 μm2

A, 0.4 μm2

P, 0.4 μm2

Fig. 10. Cumulative distribution of G=G0 fitting parameters used on hard to disruptcells.

Table 5G=G0 average value and standard deviation.

Technology G=G0

Avg. Std.

A, 1 lm2 1.61 0.26

A, 0.4 lm2 1.56 0.53

P, 0.4 lm2 1.67 0.42


a very large constriction with a very low barrier explains the issuesin controlling the cells’ uniformity during Set and Reset operations.A-array with the larger resistor area shows higher barrier andsmaller radius, resulting into a higher controllability during Setand Reset. Moreover, the highest parameters uniformity isobserved, which translates into the highest HRS and LRS currentsuniformity. A possible reason to explain the difference in thepotential barrier between the two amorphous films is related tothe defects concentrations in the HfO2. Indeed, amorphous films

integrated with lower area are affected by a higher defect concen-tration that eases the Reset process and therefore results in a lowerpotential barrier in the HRS. P-array shows the largest barrier withthe highest variability: the highest barrier is the reason of thehigher average ratio between HRS and LRS, while the high variabil-ity generates the high current variability observed in HRS.

In case of CF modulation fitting has been performed assuminglarge negative U values, a fixed to 1 (even if a and U play no rolein such condition) and G=G0 P 1 due to the presence of the resid-ual filament. Fig. 10 shows the cumulative distribution of G=G0

conductance values fitting parameters used on hard to disruptcells: it can be observed that A-array with the larger resistor areashows the lowest variability, which is the reason of the lowestHRS current variability observed during Reset with the IncrementalPulse and Verify algorithm. Average value and standard deviationof the fitting parameter G=G0 are reported in Table 5.

4.2. Equivalent circuit modeling

Electrical models are a power tool to analyze memory cells andcircuits based on Resistive Switching (RS) devices allowing evalu-ating characteristics like power consumption or performance inlarge RS devices arrays [17,19]. To model the experimental I–Vcurves during both RS states (i.e., LRS and HRS) we use a Diode-Resistor based circuit (Fig. 11) where the resistance (R), the diodesaturation current (Is) and diode ideality factor (n) are the param-eters of the model [17]. VAPP represents VBL or VSL, which are theapplied voltages to produce the Set and Reset processesrespectively.

To fit all the experimental I–V curves an automatized processhas been developed to extract the model parameters values (Tables6 and 7) for each curve. Fig. 12 shows some examples of experi-mental LRS I–V curves (circles) before the Reset process and thesimulated curves using the circuit model of Fig. 11 with suitableparameters (continuous lines). As can be observed, the model fitsperfectly with the experimental results for both amorphous andpoly-crystalline samples. For each kind of samples, the analyzed

Fig. 11. Equivalent model for the 1T-1R device based on a Diode-Resistor circuit.Resistance (R), saturation current (Is) and ideality factor (n) of the diode are theparameters used to fit the conduction of the 1T-1R devices at both resistive states,LRS and HRS, and for both types of samples, amorphous and poly-crystalline.

Table 6Model parameters of the amorphous samples I–V fittings for both states, LRS and HRS.

Set Reset

Avg. Std. Avg. Std.

R [KX] 25.84 29.6 6.25 4.18IS [A] 9.75e�5 4.56e�5 6.39e�8 1.37e�7n 8.95 7.06 5.76 5.19

Table 7Model parameters of the poly-crystalline samples I–V fittings for both states, LRS andHRS.

Set Reset

Avg. Std. Avg. Std.

R [KX] 1.34 1.61 8.88 12.9IS [A] 5.67e�5 8.4e�5 1.52e�5 4.29e�7n 3.95 5.03 1.18 2.35

Fig. 12. Experimental LRS I–V curves (circles) and the simulated curves (continuouslines) obtained using the Diode-Resistor model. With a suitable parameter Set, themodel reproduces properly the experimental curves for both poly-crystalline andamorphous samples.

Fig. 13. Experimental HRS I–V curves (circles) and simulated HRS curves (contin-uous lines) using the Diode-Resistor model for both amorphous and poly-crystallinesamples. Noisy currents at low voltages cannot be fitted by the model, especially forthe amorphous samples where current values for VBL below 1 V are not considered.


voltage range was limited by the Reset voltage that is lower for thepoly-crystalline samples.

The same automatic process was also used to fit HRS I–V curvesfor both samples types. Fig. 13 shows experimental HRS curves(circles) before the Set process and the corresponding simulatedcurves (continuous lines). Amorphous samples show very noisyIHRS currents at low voltages (<1 V) that could be caused by the nat-ure of the memory cell and the array structure where the drivetransistor effect on the electrical characteristics of the memory

must be analyzed in detail. This noisy current must be neglectedto avoid errors during the fitting process. For this reason, IHRS val-ues for VBL below 1 V are not considered to force better fittings forvoltages larger than 1 V, where the I–V curves are not affected bythe noise. This consideration affects the obtained model parame-ters values (Tables 6 and 7). Thus, the best fittings for the amor-phous HRS I–V curves require a mean R parameter value(6.25 KX) which is lower than the one obtained for the LRS(25.84 KX). This low value of the R parameter at HRS combinedto the very low value of IS at HRS (6.39e-8A) provides the best fit-ting between the experimental and the modeled curves.

5. Conclusions

1T-1R RRAM arrays manufactured with P-HfO2 shows severaladvantages compared to A-HfO2 even considering their improvedprocess: higher current Ratio, lower switching voltages, lowerpower consumption, minor endurance degradation and higheroverall yield. Moreover, P-array show very low VSET variability,hence faster Set operation could be reliably performed. P-array dis-advantages are represented by the larger HRS distribution afterForming, the higher Reset voltage dispersion, the lower read dis-turb immunity and the higher VFORM if compared to A-array withthe same resistor area, however it must be pointed out that suchoperation is performed only once. The grain boundaries conductionmechanism in the poly-crystalline HfO2 structure could be the rea-son of the higher cell-to-cell variability observed in P-arrays. QPCmodeling allowed showing that the higher uniformity observedon A-array with the large resistor area can be ascribed to a lowerconductive filament shape variability in terms of radius of the con-striction and barrier height, whereas the P-array shows the highestvariability in terms of conductive filament shape: the reason couldbe ascribed again to the different conduction mechanism and thehigher leakage currents observed on such technology. A diode-resistor equivalent circuit model correctly fits the experimentalRS I–V characteristics of poly-crystalline and amorphous samplesfor both LRS and HRS. However, noisy current levels at low volt-ages, especially for amorphous samples, could lead to a non-wellfitted curve. Thus, it is needed to remove them for a suitable cur-rent fitting at larger voltages.

Acknowledgments

This work was supported by the European Union’s H2020research and innovation programme under grant agreement No.


640073 and by ENIAC Joint Undertaking 2013-2, PANACHE No.621217. UAB authors acknowledge funding from the SpanishMINECO and ERDF (TEC2013-45638-C3-1-R) and the Generalitatde Catalunya (2014SGR-384).

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[6] Walczyk D, Bertaud T, Sowinska M, Lukosius M, Schubert MA, Fox A, et al.Resistive switching behavior in TiN/HfO2/Ti/TiN devices. In: Int.Semiconductor Conf. Dresden-Grenoble (ISCDG). p. 143–6.

[7] Lorenzi P, Rao R, Irrera F. Forming kinetics in HfO2-based RRAM cells. IEEETrans Electron Devices 2013;60(1):438–43.

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Inverse-magnetostriction-induced switching current reduction ofSTT-MTJs and its application for low-voltage MRAM


⇑ Corresponding author.E-mail address: [email protected] (Y. Takamura).

Yota Takamura a,⇑, Yusuke Shuto b, Shu’uichiro Yamamoto b, Hiroshi Funakubo c,Minoru Kuribayashi Kurosawa a, Shigeki Nakagawa a, Satoshi Sugahara a,b

a School of Engineering, Tokyo Institute of Technology, Tokyo, Japanb Laboratory for Future Interdisciplinary Research of Science and Technology, Tokyo Institute of Technology, Yokohama, Japanc School of Materials and Chemical Technology, Tokyo Institute of Technology, Yokohama, Japan




a b s t r a c t

A new spin-transfer torque (STT) magnetic tunnel junction (MTJ) using an inverse magnetostriction (IMS)material for the free layer is proposed for low-voltage MRAMs. The MTJ is surrounded by a piezoelectricgate structure so that a pressure for introducing the IMS effect can efficiently be applied to the free layerwithout any high-yield-strength support structure. During STT-induced magnetization switching, theenergy barrier height for the switching can be lowered by the IMS effect, and thus a critical current den-sity (JC) for the magnetization switching can dramatically be reduced. Energy performance of a low-voltage STT-MRAM cell using the proposed MTJ and a FinFET is also demonstrated.


1. Introduction

Low-voltage (or near-threshold voltage) operations of comple-mentary metal-oxide-semiconductor (CMOS) logic systems haveattracted considerable attention owing to the ability of dramaticreduction of dynamic and static power dissipation [1]. In particu-lar, low-voltage (�0.3–0.4 V) operations can minimize the energydissipation (or maximize the energy efficiency) of logic systems[1], and thus this operation mode is promising for always-on appli-cations such as various wearable devices [2]. Nonvolatile dataretention adaptable to low-voltage operations is highly requestedfor these applications. However, in general, it is difficult for flashand other emerging nonvolatile memories to satisfy this require-ment, since the low-voltage write operation degrades the dataretention performance.

Spin-transfer torque (STT) magnetic tunnel junctions (MTJs)could be a candidate for a low-voltage nonvolatile memory ele-ment owing to the current-driven operation behaviour of the MTJs,i.e., as far as the critical current density (JC) for their current-induced magnetization switching (CIMS) can be obtained at adesired low-voltage, there is no limitation for the (write-) opera-tion voltage. Various efforts including perpendicular magnetic ani-sotropy electrodes have been paid to reduce JC [3]. Although JC canbe reduced by lowering the energy barrier (EB) of MTJs, this leads tothe degradation of the thermal stability and thus the retention

ability. Techniques for energy barrier reduction applied only duringCIMS would be promising for managing low JC and high thermalstability. Saito et al. [4] proposed a switching field reductiontechnique based on the inverse magnetostriction (IMS) effect forfield-induced magnetization switching of MTJs using a super mag-netostriction material for the free layer. This technique would alsobe applied to JC reduction for CIMS of STT MTJs. Note that pressures(<1 GPa) required for energy barrier deformation of the IMS layerof such MTJs would be obtained using a piezoelectric (PE) materialwith a low voltage bias (discussed later).

In this paper, we propose a new STT MTJ using an IMS materialfor the free layer (hereafter, referred to as an IMS-MTJ) and compu-tationally investigate IMS-induced switching current reduction ofthe IMS-MTJ. Energy performance of a low-voltage MRAM cellusing the proposed IMS-MTJ and a high performance FinFET is alsodemonstrated.

2. Proposed IMS-MTJ

Fig. 1(a) shows schematic device structures of the proposed STTMTJ using an IMS material for the free layer. The device is com-prised of perpendicularly magnetized ferromagnetic electrodes(pinned and free layers), a tunnel barrier (TB), and a PE gate sur-rounding the MTJ part. The torus-shape PE gate structure is origi-nally proposed for a piezoelectronic transistor [5]. The free layerconsists of the IMS layer and high spin-polarization interfaciallayer facing the TB. These two layers are magnetically coupled,i.e., the magnetization direction of the interfacial layer is governed







Fig. 1. (a) Schematic device structure and cross section of a proposed IMS-MTJ. Another possible structure is shown in (b).

Y. Takamura et al. / Solid-State Electronics 128 (2017) 194–199 195

by that of the IMS layer. The PE gate acts as a stressor to the freelayer. The polarization of the PE material is parallel to the z-axis(see Fig. 1(a)), and the electrodes of the PE gate are placed so asto apply an electric field parallel to the polarization. The PE gateexerts a compressive stress to the IMS layer. Therefore, the IMSlayer needs to possess a negative magnetostrictive constant toreduce the energy barrier for the magnetization switching. Anotherpossible configuration of the PE gate is shown in Fig. 1(b). Thepolarization of the PE material is toward the central axis of theMTJ pillar as shown in the figure, and thus the electrode is formedto surround the outer periphery of the PE material.

3. Modelling and calculation procedure

IMS-induced STT magnetization switching behaviour was anal-ysed based on the LLG (Landau-Lifshits-Gilbert) equation withSlonczewski’s STT term [6,7]. In this study, we assumed that theIMS free layer had no in-plane magnetic anisotropy. When STT isexerted on the IMS layer of the IMS-MTJ, the time-evolution ofthe tilt angle (hM) component of the magnetization can be derivedfrom the LLG equation:

Mc

dhMdt

¼ �a @

@hfEiðhMÞ þ ESTTðhMÞg; ð1Þ

where c is the gyromagnetic constant, M the saturation magnetiza-tion of the IMS layer, a the damping factor, h the axis for the tiltangle of the magnezation. Ei(hM) is the internal energy of the mag-netization given by

EiðhMÞ ¼ KU � 2pM2 þ 23kP

� �

V sin2 hM ð2Þ

where KU the uniaxial magnetic anisotropy energy density, k themagnetostrictive constant (<0), P the pressure applied to the IMSlayer, and V the volume of the IMS free layer. The first, second,and third terms in Ei(hM) represent the uniaxial magnetic aniso-tropy energy, the demagnetization energy, and the magnetostrictiveenergy that expresses the IMS effect, respectively. Here, the IMSlayer is assumed to have a cylindrical shape, and P is applied toward

the central axis of the IMS-MTJ from the outer periphery of the IMSlayer. ESTT(hM) in Eq. (1) represents the potential energy for STT andit is given by [8],

ESTTðhMÞ ¼�hg2ea

I cos hM ; ð3Þ

where g is the spin transfer efficiency and I the current passingthrough the IMS layer. In this paper, the CIMS behaviour accompa-nied with/without the thermal excitation effect [9,10] were anal-ysed using the energy curve E(hM) = Ei(hM) + ESTT(hM) with itseffective energy barrier height EB for the magnetization switching.EB is given by the difference between the maximum and initialvalue (at hM = 0) of E(hM) as follows:

EB ¼ EðhmaxÞ � Eð0Þ

¼ KU � 2pM2 þ 23kP

� �

V 1� �hg2ealm

J

2 KU � 2pM2 þ 23 kP

� �

2

4

3

5

2

ð4Þ

where J is the current density passing through the IMS-MTJ and lmthe thickness of the IMS layer. hmax is given by

hmax ¼ cos�1�hg2ea J

2 KU � 2pM2 þ 23 kP

� �

lmð5Þ

Eq. (4) clearly shows that EB can be reduced by P and J, i.e., by boththe IMS and STT effects. The critical current density JC0(P) for themagnetization switching at T = 0 K can be defined as a current den-sity when EB = 0:

JC0ðPÞ ¼4ealm�hg

KU � 2pM2 þ 23kP

� �

; ð6Þ

Note that when P = 0, JC0(P) corresponds to Slonczewski’s criticalcurrent density at T = 0 K for ordinary STT-MTJs [7]. For the descrip-tion of the critical current density JCT at finite temperatures, a biterror rate (BER) of the IMS-MTJ needs to be introduced. Using BERof 10�x, JCT can be written using the Koch model [10,11]:

JCTðPÞ ¼ JC0ðPÞ 1� kBTEBðPÞV ln

1x ln 10

tps0

� ��

; ð7Þ

Table 1Simulation parameters for IMS-MTJ.

Tunneling magnetoresistance: TMR 100%Resistance-area product: RA 2 X�lm2

Voltage at half-maximum TMR: Vhalf 0.5 VJCT without the IMS effect 2.5 � 106 A/cm2

JCT with the IMS effect 0.1 � 106 A/cm2

Resistance: RP(0) (Parallel mag.) 6.36 kXRAP(0) (Antiparallel mag.) 12.7 kX

196 Y. Takamura et al. / Solid-State Electronics 128 (2017) 194–199

where kB is the Boltzmann constant, T the temperature, tp the pulsewidth of the current and pressure applied to the IMS layer, and s0the attempt time.

In this study, SmFe2 [12] is used for the IMS material, since itpossesses a large negative magnetostrictive constant. A devicestructure consisting of a CoFeB/MgO/CoFeB/SmFe2 MTJ part and aPMN-PT [13] gate surrounding it is employed. The material con-stants and device parameters used in this study are shown inTables 1 and 2, which were determined by reference to reporteddata [12–16]. Note that D is defined by the energy barrier heightfor the switching at P = 0 MPa, i.e., EB(P = 0) =D.

Table 2Material constants and device parameters for IMS-MTJ.

MTJ part

Ku (MJ/m3) M (T) k (ppm) a R (nm) lm (nm) t (nm) D H

0.56 0.64 �1258 0.005 10 2 10 60 1

YMTJ, YPE: Young modules of the MTJ and PE parts, m: Poisson’s ratio, eS33: Relative permi

Fig. 2. Energy curves E(hM) for the IMS free layer of the IMS-MTJ, in which (a) P is varierepresent current density passing through the device and pressure applied to the IMS la

Fig. 3. (a) Effective energy barrier EB as a function of J, in which P is varied from 0 to 200of the IMS-MTJ as a function of P.

Operations of proposed STT-MRAM cells (shown later) wereanalysed by HSPICE with a 20-nm-technology FinFET PTM [17]and our developed MTJ macromodel [18]. This macromodel canclosely fit experimentally observed electrical characteristics ofordinary MTJs within an error of 1.5% [18].

4. IMS-MTJ characteristics

Fig. 2 shows E(hM) for the IMS free layer as a function of tiltangle hM of the magnetization (see Fig. 1(a)). The energy curvecan be deformed by the STT effect, resulting that the effectiveenergy barrier height EB for the magnetization switching is reducedby J (Fig. 2(a)). This behaviour is consistent with the free layer ofconventional STT-MTJs. This effective energy barrier can be alsolowered by applying P to the free layer owing to the IMS effect(Fig. 2(b)). The STT magnetization switching (CIMS) occurs whenthe energy barrier disappears, and thus the IMS-induced barrierlowering is effective at reducing the critical current of the CIMS,as shown in Fig. 2(c). The effective barrier decreases with increas-ing J depending on P, and JC0 can be reduced with increasing P, asshown in Fig. 3(a). For ordinary STT-MTJs, JC0 can be reduced by

PE gate part

s0 (ns) YMTJ (GPa) YPE (GPa) m eS33 d31 (nm/V) w0 (nm)

1 40 60 0.3 741 �0.852 10

ttivity, d31: Piezoelectric strain constant.

d with J = 0, (b) J is varied with P = 0, and (c) P is varied with J = 1 MA/cm2. J and Pyer, respectively.

MPa in steps of 50 MPa. (b) Spin-transfer torque magnetization switching efficiency

Fig. 4. (a) BER as a function of J, in which P is varied from 0 to 200 MPa in steps of 50 MPa. (b) JCT as a function of P for various tp.

10 7 10 5 10 30

1

2

tp (s)

J CT

(MA

/cm

2 )

P = 0 MPa

100

200

50

150

BER = 10 6

Fig. 5. JCT as a function of tp for BER = 10�6, in which P is varied from 0 to 200 MPain steps of 50 MPa.

Fig. 6. Low-voltage MRAM cells using an IMS-MTJ with (a) drain-side MTJconnection (DSM) and (b) source-side MTJ connection (SSM) configurations forthe IMS-MTJs shown in Fig. 1(a). (c) and (d) also show DSM and SSM cells using theIMS-MTJ shown in Fig. 1(b), respectively.

Table 3Read/write operation architecture.

Read Write (AP? P) Write (P? AP)

BL H L HSL L H LWL H H HPE L H H


lowering D (=EB|J=0), which degrades thermal stability. However,JC0 also diminished by P without reducing D for the proposedIMS-MTJ, i.e., the IMS-MTJs can possess high thermal stability orretention ability. Fig. 3(b) shows CIMS efficiency of IMS-MTJs as afunction of P. The CIMS efficiency is given by a ratio of the effectiveenergy barrier EB(P) for the switching to the critical current IC0(P)[19]. The CIMS efficiency remains constant at a reasonable valueregardless of P.

Fig. 4(a) shows the BER as a function of J at room temperature,in which P is varied and the pulse width tp for J and P are fixed at30 ns. The BER rapidly increases with decreasing J for each P con-dition, when J is lower than JC0(P). Therefore, the critical currentdensity JCT determined by a given BER is important in practiceand used for the following discussion. Fig. 4(b) shows JCT forBER = 10�6 as a function of P, in which pulse width tp is varied.JCT can be effectively reduced by increasing P depending on tp.

Fig. 5 shows JCT as a function of tp for BER = 10�6. The non-linearbehaviour (concave upward decreasing function) of the JCT-tpcurve, which is commonly observed for ordinary STT-MTJs [9],appears for all the pressure conditions and JCT increases withdecreasing tp. The magnetization switching with JCT = 0.1 MA/cm2

and BER = 10�6 can be achieved for a moderate tp (several tens ofnanoseconds).

5. Low-voltage MRAM application

Fig. 6(a) and (b) shows two types of MRAM cells using theIMS-MTJ shown in Fig. 1(a). The cell shown in Fig. 6(a) is the same

configuration as conventional MRAM cells, i.e., the cell configura-tion with the drain-side MTJ connection (DSM cell). The cell shown

Fig. 7. P as a function of VPE for the IMS-MTJs shown in Fig. 1(a) and (b). VPE represents a bias voltage of the PE gate.

Fig. 8. Cell currents as a function of VDD for (a) the DSM cell and (b) the SSM cell during the read operation mode.

0 0.3 0.6 0.90

10

20

30

40

50

Nfin=1, 2, 3

VDD (V)

Mag

neto

curr

ent r

atio

(%)

VG = VDD SSM cell

DSM cell

Nfin = 1

Fig. 9. Magnetocurrent ratio as a function of VDD for the DSM and SSM cells duringthe read operation mode.

0 0.3 0.6 0.9

10 1

100

101

102

Nfin = 1

P→AP

JCT = 0.1 MA/cm2

VDD (V)

Cel

l cur

rent

(µA

)

VG = VDD

AP→P

JCT = 2.5 MA/cm2

Fig. 10. Cell currents as a function of VDD for the SSM cell during the write operationmode.

198 Y. Takamura et al. / Solid-State Electronics 128 (2017) 194–199

in Fig. 6(b) has a configuration with the source-side MTJ connec-tion (SSM cell), in which the connected MTJ feeds back its voltagedrop to the gate of the MOSFET. Since the degree of this negativefeedback depends on the resistance states of the MTJ, the cell cur-rents of the SSM cell can be effectively controlled by the magneti-zation configuration of the MTJ (shown later). In this study, aFinFET is used as a selector transistor for both the cells. Table 3shows an operation architecture of these cells. Note that the IMSeffect is not induced during the read operation, and it is employedonly during the write operation. Fig. 7(a) and (b) shows P as a func-tion of VPE (that is a bias voltage of the PE gate; see Fig. 1 and

Table 2) for the IMS-MTJs shown in Fig. 1(a) and (b), respectively.P required for the IMS-induced switching current reductiondescribed above (several hundreds of MPa) can easily be yieldedby VPE = 0.2 V or less, when a thin piezoelectric material isemployed for the PE gate (see Table 2). Fig. 6(c) and (d) showsDSM and SSM cells using the IMS-MTJ shown in Fig. 1(b).

Fig. 8(a) and (b) shows cell currents as a function of VDD for theDSM and SSM cells, respectively, during the read operation, inwhich VPE and VG are set to zero and VDD, respectively. Althoughthe cell currents of the SSM cell are lower than those of the DSMcell, its magnetocurrent ratio (that is a rate of change of the cell

0.2 0.4 0.6 0.8 1.0

10 2

10 1

100

VDD (V)

Ene

rgy

(pJ)

Fig. 11. Write energy as a function of VDD for the SSM cell.


currents in the parallel and antiparallel configurations: cMC = (IP -� IAP)/IAP) is sufficiently high to distinguish the parallel andantiparallel states even at VDD = 0.3 V, as shown in Fig. 9. In addi-tion, the magnetocurrent ratio can be enhanced by the numberof the fin channel of the FinFET, as shown in Fig. 9. On the otherhand, the magnetocurrent ratio of the DSM cell is severelydegraded for lower VDD operations. Note that when VDD is less than0.4 V, the magnetization switching does not occur during the readoperation (since the cell currents do not exceed JCT for VPE = 0 V;see Table 1).

Fig. 10 shows cell currents during the write operation for theSSM cell (in which VPE is applied). The cell current can exceed JCTfor the IMS-induced switching, when VDD P 0.2 V. Fig. 11 showsthe write energy for the SSM cells as a function of VDD. Here, theenergy to drive STT currents and the static energy for the PE gateto apply a pressure to the IMS free layers are included in the calcu-lation. By reducing VDD from 0.9 V to 0.2 V, the write energy can beconsiderably reduced to 1/400. Note that the energy consumptionof the PE gate is negligibly small in comparison with that of CIMS.

6. Conclusions

A new IMS-MTJ was proposed and computationally analysed forlow-voltage STT-MRAM applications. The free layer of the IMS-MTJconsists of a thin IMS material film and high spin-polarizationinterfacial layer facing the tunnel barrier, and it is surrounded bya PE gate so that a pressure for introducing the IMS effect can effi-ciently be applied to the free layer without any high-yield-strengthsupport structure. During STT-induced magnetization switching,

the energy barrier height for the switching can be lowered by theIMS effect, and thus JC can be dramatically reduced. The writeenergy of a low-voltage STT-MRAM cell using an IMS-MTJ with aFinFET can be hugely reduced compared to conventional MRAMcells.

Acknowledgement

This study was partly supported by JSPS KAKENHI Grant and JSTCREST program. This work is also supported by VLSI Design andEducation Center (VDEC), The University of Tokyo with the collab-oration with Synopsys Corporation.

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[15] Park JH, et al. Enhancement of data retention and write current scaling for sub-20 nm STT-MRAM by utilizing dual interfaces for perpendicular magneticanisotropy. In: 2012 VLSI, paper 7.1.

[16] Gajek M et al. Spin torque switching of 20 nm magnetic tunnel junctions withperpendicular anisotropy. Appl Phys Lett 2012;100(March):132408/1–8/3.

[17] Predictive Technology Model (PTM) <http://ptm.asu.edu/>.[18] Yamamoto S, Sugahara S. Nonvolatile static random access memory using

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[19] Hu G, et al. STT-MRAM with double magnetic tunnel junctions. In: 2015 IEDM,paper 26.3.

























http://ptm.asu.edu/






CONTENTS—continued from inside back cover]

C. NAVARROAVARRO, S. BARRAUDARRAUD, S. MARTINIEARTINIE, J. LACORDACORD, M.-A. JAUDAUD and M. VINETINET: Reconfigurable fieldeffect transistor for advanced CMOS: Advantages and limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

M. M. VIGNETTIIGNETTI, F. CALMONALMON, P. LESIEURESIEUR and A. SAVOY-AVOY-NAVARROAVARRO: Simulation study of a novel 3DSPAD pixel in an advanced FD-SOI technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

S. ATHANASIOUTHANASIOU, C.-A. LEGRANDEGRAND, S. CRISTOLOVEANURISTOLOVEANU and P. GALYALY: Reconfigurable ultra-thin filmGDNMOS device for ESD protection in 28 nm FD-SOI technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

H. ELL Dirani, P. FONTENEAUONTENEAU, Y. SOLAROOLARO, C.-A. LEGRANDEGRAND, D. MARIN-ARIN-CUDRAZUDRAZ, P. FERRARIERRARI and

S. CRISTOLOVEANURISTOLOVEANU: Sharp-switching band-modulation back-gated devices in advanced FDSOI technology 180

A. GROSSIROSSI, C. ZAMBELLIAMBELLI, P. OLIVOLIVO, A. CRESPO-RESPO-YEPESEPES, J. MARTIN-ARTIN-MARTINEZARTINEZ, R. RODRIGUEZODRIGUEZ,M. NAFRIAAFRIA, E. PEREZEREZ and C. WENGERENGER: Electrical characterization and modeling of 1T-1R RRAM arrayswith amorphous and poly-crystalline HfO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Y. TAKAMURAAKAMURA, Y. SHUTOHUTO, S. YAMAMOTOAMAMOTO, H. FUNAKUBOUNAKUBO, M. K. KUROSAWAUROSAWA, S. NAKAGAWAAKAGAWA and

S. SUGAHARAUGAHARA: Inverse-magnetostriction-induced switching current reduction of STT-MTJs and itsapplication for low-voltage MRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

EDITORIAL ADVISORY BOARD

P. AVOURISVOURIS, Yorktown Heights, NY, USAG. BACCARANIACCARANI, Bologna, ItalyL. COLOMBOOLOMBO, Dallas, TX, USAJ. G. FOSSUMOSSUM, Gainesville, FL, USAG. GHIBAUDOHIBAUDO, Grenoble, FranceG. GILDENBLATILDENBLAT, Tempe, AZ, USAS. HALLALL, Liverpool, UKT. HASHIZUMEASHIZUME, Saitama, JapanS. HWANGWANG, Yongin-si, Gyeonggi-do, South KoreaC. JAGADISHAGADISH, Canberra, ACT, AustraliaK. KAKUSHIMAAKUSHIMA, Midori-ku, Yokohama, Japan

S. KELLERELLER, Santa Barbara, CA, USAJ.-HH. LEEEE, Gwanag-Gu, Seoul, South KoreaC. MCCANDREWNDREW, Tempe, AZ, USAC. MCCCONVILLEONVILLE, Coventry, UKS. RINGELINGEL, Columbus, OH, USAJ. SCHMITZCHMITZ, Enschede, NetherlandsA. SEABAUGHEABAUGH, Notre Dame, IN, USAM. S. SHURHUR, Troy, NY, USAA. WAAGAAG, Braunschweig, Germany


FOUNDING EDITOR

DRR W. CRAWFORDRAWFORD DUNLAPUNLAP

EDITORS

E. CALLEJAALLEJA

Dept. of Electronic Engineering (ISOM), ETSI Telecommunication,Universidad Politecnica de Madrid (UPM), 28040 Madrid, Spain

S. CRISTOLOVEANURISTOLOVEANU

Grenoble INP, Ref: LPCS-SSE, 46 av. Felix Viallet,F-38031 Grenoble Cedex 1, France

Y. KUKUK

Dept. of Physics & Astronomy, Seoul National University (SNU),Gwanack-ku Silim-dong, Seoul, South Korea

A. ZASLAVSKYASLAVSKY

Solid State Electronics, Brown University Engineering, 182 Hope Street,Providence, RI 02912, USA

Author inquiries: You can track your submitted article at http://www.elsevier.com/track-submission. You can track your accepted article at

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CONTENTS—continued from outside back cover]

C. SCHULTE-CHULTE-BRAUCKSRAUCKS, S. GLASSLASS, E. HOFMANNOFMANN, D. STANGETANGE, N. vONON DENDEN DRIESCHRIESCH, J. M. HARTMANNARTMANN,Z. IKONICKONIC, Q. T. ZHAOHAO, D. BUCAUCA and S. MANTLANTL: Process modules for GeSn nanoelectronics with highSn-contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

B. C. PAZAZ, M. CASSEASSE, S. BARRAUDARRAUD, G. REIMBOLDEIMBOLD, M. VINETINET, O. FAYNOTAYNOT and M. A. PAVANELLOAVANELLO: Studyof silicon n- and p-FET SOI nanowires concerning analog performance down to 100 K. . . . . . . . . . . . . . 60

A. S. N. PEREIRAEREIRA, G. DEDE STREELTREEL, N. PLANESLANES, M. HAONDAOND, R. GIACOMINIIACOMINI, D. FLANDRELANDRE and

V. KILCHYTSKAILCHYTSKA: An in-depth analysis of temperature effect on DIBL in UTBB FD SOI MOSFETs basedon experimental data, numerical simulations and analytical models . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

R. BERTHELONERTHELON, F. ANDRIEUNDRIEU, S. ORTOLLANDRTOLLAND, R. NICOLASICOLAS, T. POIROUXOIROUX, E. BAYLACAYLAC, D. DUTARTREUTARTRE,

E. JOSSEOSSE, A. CLAVERIELAVERIE and M. HAONDAOND: Characterization and modelling of layout effects in SiGe channelpMOSFETs from 14 nm UTBB FDSOI technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

H. J. PARKARK, L. PIRROIRRO, L. CZORNOMAZZORNOMAZ, I. IONICAONICA, M. BAWEDINAWEDIN, V. DJARAJARA, V. DESHPANDEESHPANDE and

S. CRISTOLOVEANURISTOLOVEANU: Back-gated InGaAs-on-insulator lateral N+NN+ MOSFET: Fabrication and typicalconduction mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

V. DESHPANDEESHPANDE, V. DJARAJARA, E. O’’CONNORONNOR, P. HASHEMIASHEMI, K. BALAKRISHNANALAKRISHNAN, D. CAIMIAIMI, M. SOUSAOUSA,

L. CZORNOMAZZORNOMAZ and J. FOMPEYRINEOMPEYRINE: DC and RF characterization of InGaAs replacement metal gate(RMG) nFETs on SiGe-OI FinFETs fabricated by 3D monolithic integration. . . . . . . . . . . . . . . . . . . . . 87

D. TOMASZEWSKIOMASZEWSKI, G. GŁUSZKOUSZKO, L. ŁUKASIAKUKASIAK, K. KUCHARSKIUCHARSKI and J. MALESINSKAALESINSKA: Elimination of thechannel current effect on the characterization of MOSFET threshold voltage using junction capacitancemeasurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

D. BOUDIEROUDIER, B. CRETURETU, E. SIMOENIMOEN, R. CARINARIN, A. VELOSOELOSO, N. COLLAERTOLLAERT and A. THEANHEAN: Lowfrequency noise assessment in n- and p-channel sub-10 nm triple-gate FinFETs: Part I: Theory andmethodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

D. BOUDIEROUDIER, B. CRETURETU, E. SIMOENIMOEN, R. CARINARIN, A. VELOSOELOSO, N. COLLAERTOLLAERT and A. THEANHEAN: Lowfrequency noise assessment in n- and p-channel sub-10 nm triple-gate FinFETs: Part II: Measurements andresults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

C. MARQUEZARQUEZ, N. RODRIGUEZODRIGUEZ, F. GAMIZAMIZ and A. OHATAHATA: Systematic method for electrical characterizationof random telegraph noise in MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

B. KAZEMIAZEMI ESFEHSFEH, S. MAKOVEJEVAKOVEJEV, D. BASSOASSO, E. DESBONNETSESBONNETS, V. KILCHYTSKAILCHYTSKA, D. FLANDRELANDRE and

J.-P. RASKINASKIN: RF SOI CMOS technology on 1st and 2nd generation trap-rich high resistivity SOI wafers . 121

C. JUNGEMANNUNGEMANN, T. LINNINN, K. BITTNERITTNER and H.-G. BRACHTENDORFRACHTENDORF: Numerical investigation of plasmaeffects in silicon MOSFETs for THz-wave detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

V. SIMONKAIMONKA, G. NAWRATILAWRATIL, A. HOSSINGEROSSINGER, J. WEINBUBEINBUB and S. SELBERHERRELBERHERR: Anisotropic interpolationmethod of silicon carbide oxidation growth rates for three-dimensional simulation. . . . . . . . . . . . . . . . . . 135

P. MANSTETTENANSTETTEN, L. FILIPOVICILIPOVIC, A. HOSSINGEROSSINGER, J. WEINBUBEINBUB and S. SELBERHERRELBERHERR: Framework to modelneutral particle flux in convex high aspect ratio structures using one-dimensional radiosity . . . . . . . . . . . . 141

T. BALDAUFALDAUF, A. HEINZIGEINZIG, J. TROMMERROMMER, T. MIKOLAJICKIKOLAJICK and W. M. WEBEREBER: Tuning the tunnelingprobability by mechanical stress in Schottky barrier based reconfigurable nanowire transistors . . . . . . . . . 148

[continued on last page

Available online at www.sciencedirect.com

ScienceDirect

SOLID-STATEELECTRONICS

An International Journal

Volume 128, February 2017 ISSN 0038-1101

EDITORS:

E. Calleja

Madrid

S. CristoloveanuGrenoble, France

Y. Kuk

Seoul, South Korea

A. Zaslavsky

Providence, RI

Special Issue:Extended papers selected from

EUROSOI-ULIS 2016

Guest Editors

Viktor SverdlovSiegfried Selberherr

ISSN 0038-1101ISSN 0038-1101

Printed in the Netherlands

SPECIAL ISSUE: EXTENDED PAPERS SELECTED FROM EUROSOI-ULIS 2016

Guest Editors

Viktor Sverdlov and Siegfried Selberherr

V. SVERDLOVVERDLOV and S. SELBERHERRELBERHERR: Special Issue of Solid-State Electronics, dedicated to EUROSOI-ULIS2016 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

J. M. C. STORKTORK IEEE Fellow and G. P. HOSEYOSEY: SOI technology for power management in automotive andindustrial applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

B. MOHAMADOHAMAD, C. LEROUXEROUX, D. RIDEAUIDEAU, M. HAONDAOND, G. REIMBOLDEIMBOLD and G. GHIBAUDOHIBAUDO: Reliable gatestack and substrate parameter extraction based on C-V measurements for 14 nm node FDSOI technology 10

M. A. ELMESSARYLMESSARY, D. NAGYAGY, M. ALDEGUNDELDEGUNDE, N. SEOANEEOANE, G. INDALECIONDALECIO, J. LINDBERGINDBERG,

W. DETTMERETTMER, D. PERICERIC, A. J. GARCIA-LOUREIROARCIA-LOUREIRO and K. KALNAALNA: Scaling/LER study of Si GAAnanowire FET using 3D finite element Monte Carlo simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

N. SANOANO: Variability and self-average of impurity-limited resistance in quasi-one dimensional nanowires. . 25

T. A. KARATSORIARATSORI, C. G. THEODOROUHEODOROU, S. HAENDLERAENDLER, C. A. DIMITRIADISIMITRIADIS and G. GHIBAUDOHIBAUDO: Draincurrent local variability from linear to saturation region in 28 nm bulk NMOSFETs . . . . . . . . . . . . . . . . 31

S. STRANGIOTRANGIO, P. PALESTRIALESTRI, M. LANUZZAANUZZA, D. ESSENISSENI, F. CRUPIRUPI and L. SELMIELMI: Benchmarks of a III-VTFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmeticcircuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

P. G. D. AGOPIANGOPIAN, J. A. MARTINOARTINO, A. VANDOORENANDOOREN, R. ROOYACKERSOOYACKERS, E. SIMOENIMOEN, A. THEANHEAN andC. CLAEYSLAEYS: Study of line-TFET analog performance comparing with other TFET and MOSFETarchitectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

C. MEDINA-EDINA-BAILONAILON, C. SAMPEDROAMPEDRO, F. GAMIZAMIZ, A. GODOYODOY and L. DONETTIONETTI: Confinement orientationeffects in S/D tunneling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

[continued on inside back cover


Volume 128, February 2017

CONTENTS

Abstracted / Indexed in: Res. Alert, Cam. Sci. Abstr., Chem. Abstr. Serv., Curr. Cont./Phys. chem. & Earth Sci., Curr Cont./Eng. Tech. & Appl. Sci., Curr. Tech. Indx, Eng. Indx, INSPEC Data.,

PASCAL-CNRS Data., Curr. Cont. Sci. Indx, Curr. Cont. SCISEARCH Data., SSSA/CISA/ECA/ISMEC, Mater. Sci. Cit. Indx, Appl. Sci. & Tech. Indx, Wilson Appl. Sci. & Tech. Abstr. Also covered in

the abstract and citation database Scopus�. Full text available on ScienceDirect�.

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