Souvik Mahapatra Department of Electrical Engineering
description
Transcript of Souvik Mahapatra Department of Electrical Engineering
Negative Bias Temperature Instability (NBTI) in p-MOSFETs: Characterization, Material/Process Dependence and Predictive Modeling (Part 1 of 3)
Souvik Mahapatra Department of Electrical Engineering Indian Institute of Technology Bombay, Mumbai, IndiaEmail: [email protected]; [email protected]
Co-contributors: M. A. Alam & A. E. Islam (Purdue), E. N. Kumar, V. D. Maheta, S. Deora, G. Kapila, D. Varghese, K. Joshi & N. Goel (IIT Bombay)
Acknowledgement: C. Olsen and K. Ahmed (Applied Materials), H. Aono, E. Murakami (Renesas), G. Bersuker (SEMATECH), CEN IIT Bombay, NCN Purdue, Applied Materials, Renesas Electronics, SEMATECH, SRC / GRC
1
Outline
Introduction, Basic NBTI signatures
2
Role of Nitrogen – Study by Ultrafast measurement
Estimation of pre-existing and generated defects
Predictive modeling
Fast / Ultra-fast drain current degradation measurement
Conclusions / outlook
Transistor process / material dependence
Part-I
Part-II
Part-III
Outline
Introduction, Basic NBTI signatures
3
Role of Nitrogen – Study by Ultrafast measurement
Estimation of pre-existing and generated defects
Predictive modeling
Fast / Ultra-fast drain current degradation measurement
Conclusions / outlook
Transistor process / material dependence
Negative Bias Temperature Instability (NBTI)
Issue: p-MOSFET in inversion
4
VDD
VDD
VG=0
100 101 102 103
10-2
10-11.2nm (nitrided)stress (-VG)
1.9V2.1V T=100OC
T=27OCV
T (V)
stress time (s)
Degradation increases at higher T and higher (negative) stress bias
Parametric degradation (VT, gm) in time, shows power law time dependence (~ A*tn)
Kimizuka, VLSI’00
A Simple Physical Framework of NBTI
5
Parametric (VT, gm, IDLIN) shift due to positive charges generated at the Si/SiO2 interface and/or at SiO2 bulk
S D
B
G
Generation of interface traps
Generation and subsequent charging of bulk oxide traps
Charging of pre-existing (process related) bulk oxide traps
Very Long Time DegradationUniversally observed long-time power-law time exponent of n = 1/6 in “production quality” devices
Chen, TSMC, IRPS’05
1.2 1.8 2.40.05
0.10
0.15
0.20
0.25
0.30
Vstress [Volts]
-250C 450C1050C 1450C
Deg
rada
tion
Slop
e, n
1/6 line
Stress time ~ 28Hr
Krishnan, TI, IEDM’06 (in Islam et. al)Stress Time > 1000 Hr
Tech A, V1
Tech A, V2
Tech B, V1
Vm
in fo
r SR
AM
~t1/6
Haggag, Freescale, IRPS’07
Similar observation in circuits
Important feature for prediction of degradation at end-of-life 6
Dependence on Stress VG and Gate Leakage
7
Kimizuka, VLSI’99
NBTI not governed by gate voltage – higher NBTI (lower lifetime) for thinner oxide
10-5 10-4 10-3 10-2
1010
1011
T=25OC TPHY
36A 26A
[JG. VG. t] (arb. unit)
CO
X/q *
VT s
hift
(cm
-2)
No correlation with electron energy dissipated in anode
Mahapatra, TED’04
IG
IB
ISD
-VG
2 3 4 5 61010
1011 T=25OC TPHY
36A 26A
q.VG (eV)
CO
X/q *
VT s
hift
(cm
-2)
No correlation with electron energy even under ballistic limit
p-MOSFET inversion: Electron tunneling from gate to bulk, hole tunneling from bulk to gate
Dependence on Stress EOX
8
Tsujikawa, IRPS’03
NBTI governed by oxide electric fieldHuard, MR’05
V T
* C O
X /
q
1 10
3
4
5
8
10
12
VG
EOX
T=25OC
NIT shift (109 cm-2)
VG (V
), E O
X (M
V/c
m)
TPHY(AO)
2636
10-1100 101 102 103 104
stress time (s)
PI, -3.2VNA, -3.2VNA, -4.2V
10-4
10-3
10-2
10-1
T=25OC
TPHY=26AO
Norm
alized ID shift (VG -V
T =0.7V)
PMOS inversion shows similar NBTI as NMOS accumulation under similar oxide field (not same voltage)
Mahapatra, TED’04
Parametric Degradation
Degradation in subthreshold slope (due to generation of interface traps, NIT)
Tsujikawa, MR’05
For a given VT, larger IDLIN for thinner oxide (lower overdrive)
9
For a given VT, IDSAT > IDLIN (as 1 < < 2)
VVV
II
TG
T
DLIN
DLIN
)(
VV)V(
II
TG
T
DSAT
DSAT
Krishnan, IEDM’03
Gate Insulator Material / Process Impact
10
Larger NBTI for SiON compared to SiO2 gate insulator
Mitani IEDM’02NBTI reduction by suitable “process optimization”
Sakuma IRPS’06
Increase in NBTI with higher N content in the gate insulator
Tan EDL’04
VT = A*tn
Post Stress NBTI Recovery
11
Recovery of degradation after removal of stress
Reisinger IRPS’06
Stress Recovery-VG (S)-VG (R)
Recovery of subthreshold slope interface trap passivation
Tsujikawa, MR’05
Recovery depends on stress-recovery bias difference and SiON process
0.10.20.30.40.50.60.70.80.91.01.1
Low N%
fract
ion
rem
aini
ng
tSTR=1000sVSTR / VREC (V)
-1.7 / -1.3-2.3 / -1.8-2.3 / -1.3-2.3 / -1.0
10-7 10-5 10-3 10-1 101 103 1050.10.20.30.40.50.60.70.80.91.01.1
High N%
tSTR=1000sVSTR / VREC (V)
-1.7 / -1.3-2.3 / -1.8-2.3 / -1.3-2.3 / -1.0
recovery time (s)
fract
ion
rem
aini
ng Kapila, IEDM’08
DC and AC Stress – Duty Cycle & FrequencyRecovery: Lower NBTI for AC stress
12
Nigam, IRPS’06
Fernandez, IEDM’06
Independent of frequency when properly measured (no high f reflection)
?
0 101103105107109
Toshiba STIMEC NUS
Ours: (v-low N%) (mid N%)
frequency (Hz)0 20 40 60 80100
0.00.20.40.60.81.0
RDThree wellTwo well
duty cycle (%)
InfineonTUV
degr
adat
ion
Large spread of published data on duty cycle dependence, AC/DC ratio
Mahapatra, IRPS’11
Motivation
Understanding and estimation of defects responsible for degradation under accelerated stress condition
13
Explanation of the following features:
Strong gate insulator process dependence
Time evolution of degradation, prediction at long time
Temperature and oxide field dependence of degradation
Recovery of degradation after DC stress
Duty cycle and frequency dependence under AC stress
Predictive modeling for lifetime projection – extrapolation of short-time accelerated stress data to end-of-life under use condition
Outline
Introduction, Basic NBTI signatures
14
Role of Nitrogen – Study by Ultrafast measurement
Estimation of pre-existing and generated defects
Predictive modeling
Fast / Ultra-fast drain current degradation measurement
Conclusions / outlook
Transistor process / material dependence
Issues with Measure-Stress-Measure Approach
15
Lower magnitude & higher slope (n) due to recovery during measure delay
100 101 102 10310-2
7x10-2
T=150OC
EOT=2.2nm (nitrided)VG(stress)=-3.0VVG(meas)=-1.5V
50ms, 0.185100ms, 0.20350ms, 0.213
VT (
V)
stress time (s)
Stress
Measurement-VG (M)
-VG (S)M-time
0 50 100 150 2000.14
0.16
0.18
0.20
0.22
0.24
0.26
0.28
0.300.05s (delay)0.35s1s
time
expo
nent
Temperature (OC)
Increase in slope (n) with higher T and higher measure delay – artifact
Unintentional recovery during measurement delay
Need “delay-free” measurement
Varghese, IEDM’05
Ultra-Fast Measure-Stress-Measure (MSM) Method
16
DCPS
PGU
IVC
DSO
Superpose fast triangular pulse on top of stress gate voltage – measure ID-VG (hence VT) using IVC-DSO
Larger degradation and recovery magnitude for fast MSM compared to conventional (slow) MSM
Yang, VLSI’05
Ultra Fast MSM (Constant Current) Method
17
Switch between stress & measure modes
ID kept constant, change in VT (due to NBTI stress) gets adjusted by VG change, hence VT ~ VG
Reisinger, IRPS’06
Clear stress VG dependence of degradationWeak T activation of degradation at short stress time
OPAMP based feedback to force constant current in measure mode
On-The-Fly (OTF) IDLIN Method (Conventional)
SMU
PGU Start ID sampling in SMU
Continue ID sampling without interrupting stress
Delay in IDLIN0 measurement: time-zero delay t0 ~ 1ms
I DLIN
timeRangan, IEDM’03
V G
10-4 10-2 100 102 104620640660680700720740760780
T=125OCVG=-2.9V
RTNO (22.5AO)
PNO (23.5AO)
I DLI
N (
A)
time since application of VG,STRESS
SMU triggers PGU, PGU provides gate stress pulse
18
Calculated Degradation from IDLIN Transient
19
V (t) = – (IDLIN (t) – IDLIN0 (1ms))/IDLIN0 (1ms)
10-4 10-2 100 102 10410-3
10-2
10-1
RTNO (22.5AO, 6%)
T=125OC-2.3V-2.5V-2.9V
scaled data
t0 delay = 1ms
V (V
)
stress time (s) 10-4 10-2 100 102 10410-3
10-2
10-1
scaled data
RTNO (22.5AO, 6%)VG=-2.9V
55OC
85OC
125OCt0 delay = 1ms
V (V
)
stress time (s)
Clear bias dependence for all time – scalable to unique relation
Clear T dependence for all time – scalable to unique relation
Varghese, IEDM’05
10-4 10-2 100 102 104620640660680700720740760780
T=125OCVG=-2.9V
RTNO (22.5AO)
PNO (23.5AO)
I DLI
N (
A)
time since application of VG,STRESS
IDLIN0
Conventional OTF Measurement Results
Power law time dependence of longer time data, with time exponent n ~ 0.14-0.15 for all stress bias and temperature
Stress VG and T
Different magnitude but similar time exponent for different film type (Details of GOX process dependence discussed later)
Mahapatra, IRPS’07 20
100 101 102 103
10-2
10-1
PNO (21%)
PNO (14%)
-VG(V) / T(OC) [1.2nm]1.9 / 100 1.9 / 1251.55 / 125 2.1 / 1251.9 / 125 1.9 / 150
VT (
V)
stress time (s)100 101 102 1036x10-3
10-2
10-1
T=125OC
PNO(1.7nm, 28%), -2.3VPNO(2.2nm, 29%), -2.5VRTNO(1.2nm, 11%), -1.9VRTNO(1.2nm, 17%), -1.75VCONT(1.3nm), -1.9V
VT
(V)
stress time (s)
Film type, EOT
Ultra-Fast On-The-Fly (UF-OTF) IDLIN Method
21
SMU
PGU
IVC
DSO
Start ID sampling (1s rate) using IVC-DSO, trigger PGU via SMU
Current measurement: Short-time (1s-100ms) using IVC-DSO, long time (≥1ms) using SMU
Kumar, IEDM’07
Delay in IDLIN0 measurement: time-zero delay t0 ~ 1s
-4 0 4 8 12 16 20
500
550
600
650
700
750
time (s)
I DLI
N (
A)
-4.0-3.6-3.2-2.8-2.4-2.0-1.6-1.2-0.8-0.4
VG,STRESS
T=125OC
PNO (2.35nm)
VG (V
)
10-7 10-5 10-3 10-1 101 103620640660680700720740760780
T=125OCVG=-2.9V
PNO (23.5AO)
RTNO (22.5AO)I DLI
N (
A)
time since application of VG,STRESS
Degradation: Impact of “Time-Zero” Delay
t0 delay: Time lag between application of stress VG and measurement of 1st IDLIN data
22
10-6 10-3 100 1033x10-3
10-2
10-1
V (V
)
stress time (s)
t0 delay 1s1ms30ms
T=1250CEOX = 8.5 MV / cm
PNO (23.5AO, 17%)
PNO: Higher NBTI for lower t0 delay, t0 delay mostly impacts short-time dataRTNO: Large t0 impact on short- and long-time data, higher NBTI compared to PNO
V = IDLIN/IDLIN0 * (VG – VT0), where IDLIN0 picked at 1s, 1ms and 30ms
10-7 10-5 10-3 10-1 101 103620640660680700720740760780
T=125OCVG=-2.9V
PNO (23.5AO)
RTNO (22.5AO)I DLI
N (
A)
time since application of VG,STRESS
10-6 10-3 100 1033x10-3
10-2
10-1T=1250C
EOX ~ 8.5 MV / cm
t0 delay 1s1ms30ms
V (V
)
stress time (s)
RTNO (22.5AO, 6%)
Maheta, PhD thesis (IITB)
Time Evolution of Long-time Degradation
23
10-2 10-1 100 101 102 1035x10-3
10-2
10-1
t0=1s
EOX=8.5MV/cm, T=125OC
n=0.06
n=0.12
RTNO (22.5AO, 6%)
PNO (23.5AO, 17%)
stress time (s)
V(V
)
101 102 103 1047x10-3
10-2
7x10-2
EOT=1.4nmN=12%
t0=1s
|VG|=1.9; 2.1; 2.3; 2.5 (V)
T=125OC
V (V
) stress time (s)
1.8 2.0 2.2 2.4 2.60.08
0.12
0.16
0.20
EOT=1.4nmN=12%
T=125OC; t0=1s10s-10Ks10s-1Ks100s-10Ks
time
expo
nent
(n)
stress -VG (V)
Similar n for different stress VG, time range for linear fit
Power-law time dependence at longer stress
Time exponent (n) depends on t0 delay – reduces at lower t0 but saturates for t0 < 10s10-6 10-5 10-4 10-3 10-2
0.06
0.09
0.12
0.15
0.18PNO (14AO-23.5AO; 17%-22%)
RTNO
time
expo
nent
(t=1
0s-1
000s
)
t0 delay (s)Maheta, PhD thesis (IITB)
UF-OTF: Bias Dependence of Degradation
24
RTNO shows higher magnitude and lower bias dependent acceleration compared to PNO
10-6 10-3 100 1033x10-3
10-2
10-1EOT = 23.5 A0
N% = 17
t0=1s
V (V
)
stress time (s)
-VG (V)
3.32.92.5
T=1250C
PNO
10-6 10-3 100 1033x10-3
10-2
10-1
EOT=22.5 A0
N%=6
t0=1s
RTNO
T=1250C
-VG (V) 3.3 2.9 2.5
V (V
)
stress time (s)
Lower long-time power law time exponent (n) for RTNO compared to PNO – n independent of oxide field
6 7 8 9 10
0.04
0.06
0.08
0.10
0.12
0.14
RTNO (22.5AO, 6%)
PNO (14AO-23.5AO, 17%-22%)
time
expo
nent
(10s
- 10
00s)
EOX (MV / cm)
T = 1250C
t0 = 1s
Maheta, TED 2008
UF-OTF: Temperature Dependence of Degradation
25
RTNO shows negligible T dependence at short time, weak T activation at longer time
10-6 10-3 100 1033x10-3
10-2
10-1
RTNO
EOT = 22.5 A0
N% = 6
EOX ~ 8.5 MV/cm
T (0C)1258555
V (V
)
stress time (s)
10-6 10-3 100 1033x10-3
10-2
10-1
EOT = 23.5 A0
N% = 17V (V
)
stress time (s)
T (0C)1258555
EOX
~8.5 MV/cm
t0=1s
PNO
PNO shows strong T activation from short to longer time
Long-time power law time exponent (n) independent of T (no delay artifact)
0 30 60 90 120 150 180
0.04
0.06
0.08
0.10
0.12
0.14
RTNO (22.5AO, 6%)
PNO (14AO-23.5AO, 17%-22%)
t0=1s
EOX ~ 8.5 MV / cm
T (0C)
tim
e ex
pone
nt (1
0s -1
000s
)
Maheta, TED 2008
Mobility Correction
26
Difference between V (OTF) and VT (MSM, peak gm method) due to mobility degradationV read at VDD gives 1:1 correlation with VT
OTF: Stress followed by recovery at VG=VDD
101 102 10310-2
10-1
V (UF-OTF)
VT (UF-MSM)
degr
adat
ion
(V)
stress time (s)
VG,STRS=-2.1VT=125oC
PNO (14AO, N=12%)
10-7 10-5 10-3 10-1 101 10310-3
10-2
10-1
PNO (23.5AO, 17%)
Stress (VG=-2.9V)Recovery (VG=-1.3V)Scaled stress
degr
adat
ion
(V)
stress / recovery time (s)0.00 0.02 0.04 0.06 0.08 0.100.00
0.02
0.04
0.06
0.08
0.10
UF-MSM
UF-OTF
VG,SENS(V)-2.1 (Stress)-1.1 (VDD)
-I D
LIN/I D
LIN
0 * (V
G,S
EN
S -
VT0
)
VT (peak gm method)
Scaling end of stress data to recovery data measured at 1s enforces mobility correction
Stress
Recovery
-VG (S)
-VG (R)
Mobility correction: Islam, IRPS’08
Summary
On-the-fly (OTF) IDLIN methods can be used to study degradation from 1ms (fast version) and 1s (ultra-fast version) time scale
27
Recovery of NBTI degradation after removal of stress – issues with conventional “slow” MSM methods
Important process dependent signatures observed in sub ms time scale by UF-OTF method (discussed in detail later)
OTF IDLIN needs mobility correction to obtain VT shift
Ultrafast MSM can provide VT shift with negligible artifacts, is useful for capturing long time degradation for lifetime determination, early part (t<1s) degradation cannot be studied
Constant current ultrafast MSM method is an alternative, but needs subthreshold slope correction to determine proper VT shift
Outline
Introduction, Basic NBTI signatures
28
Role of Nitrogen – Study by Ultrafast measurement
Estimation of pre-existing and generated defects
Predictive modeling
Fast / Ultra-fast drain current degradation measurement
Conclusions / outlook
Transistor process / material dependence
Background – The “Philosophy”
29
I-V measurements (previous section) influenced by generation of interface and bulk traps, plus trapping in pre-existing traps
S D
B
G
How to independently estimate pre-existing traps? Eg: Flicker noise
How to independently estimate interface and bulk trap generation? Eg: DCIV, Charge pumping, Flicker noise, LVSILC and SILC
Can different measurements be correlated?
Flicker Noise Measurement (Pre-stress)Measure ID power spectral density versus frequency at low gate overdrive
p+p+
n
DC Supply + LPF
LNA + DSA
SVG = SID / gm
Flicker noise due to trapping/ detrapping of holes in oxide traps
Increase in pre-existing hole trap density with N density
30
High pre-existing hole trap density for certain (type-B) devices
22.6 29.4 34.6 41.3 42.50
10
20
30
40
50
60
PNO w proper PNA
Fixed inversion chargeFreq = 15.625 Hz
atomic N%
S VG
V2 /Hz
3x100 101 1023x10-13
10-12
10-11
10-10
Type-B
Identical inversion charge
Type-AS VG (V
2 /Hz)
frequency (Hz)Kapila, IEDM’08
31
DCIV Measurements
Sweep VG with S/D in F.B, measure ISUB due to electron-hole recombination in traps at or near Si/SiO2 interface
np+p+
ISUB
VF
Stathis IRPS’04
Neugroschel, MR’07
Increase in ISUB due to stress seen in both SiO2 and SiON: Indicates trap generation at or near Si/SiO2 interface
Stress time
Stress time
32
DCIV Measurements
Power law time dependence (A*tn), with n ~ 1/6 at long stress time for different stress VG and T
Campbell IRPS’06
SiON, 2.3nm
Neugroschel, MR’07
Neugroschel, MR’07
Stress
Recovery
Reduction in ISUB after stress seen in both SiO2 and SiON: Indicates recovery of generated traps
Recovery time
Correlation of DCIV to I-V Measurements
33
Similar degradation and recovery signatures across different methods: VT, gm (from slow MSM I-V) and IDCIV (DCIV)
Good correlation of IDCIV to VT & gm degradation during stress and recovery
33Chen, IRPS’03
Charge Pumping Measurements
34
ICP
p+p+
n
Pulse VG repetitively from inversion to accumulation, measure ISUB due to electron-hole recombination in traps at Si/SiO2 interface and inside SiO2 bulk
100 101 102 1032x100
101
102CP (f=800kHz)VG=-3.0V (stress)EOT=2.2nm
T=150OC
T=27OC
stress time (s)
NIT (x
109 c
m-2)
CP current increase (trap generation) with stress time - power law time dependence - larger n than IDLIN measurement
Time exponent increases with delay time and stress T – recovery related artifact
0 50 100 150 2000.18
0.20
0.22
0.24
0.26
0.28
0.30
0.32
0.340.35s (delay)0.5s1s
time
expo
nent
Temperature (OC)
Varghese, IEDM’05
Correlation of CP to I – V Measurements
35
Both VT (slow MSM) and ICP shows power law time dependence and higher degradation for NO-SiON
Both VT (slow MSM) and ICP shows recovery of degradation, and larger recovery for NO-SiON
Mitani, MR’08
Impact of Stress on Flicker NoiseIncrease in flicker noise after stress generation of traps
36Kapila, IEDM’086 7 8 9 104x10-1
100
101
6x101
EOT=21.4AO
N=29%
t-stress=4000s
T=150OC
EOX (MV/cm)
degr
adat
ion
VT (mV)
SVG x 10-12 V2/Hz
NIT x 1010 cm-2
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
362916
field
acc
eler
atio
n fa
ctor
N% (atomic)
SVG VT NIT
3x100 101 1024x10-13
10-12
10-11
10-10
measure:|VG|=0.9V|VD|=1.5V
1/f trend line
EOT=20AO, N=36%
post-stress
pre-stress
stress VG=-2.3V; T=150OC stress t=4000s
S VG (V
2 /Hz)
frequency (Hz)
Similar voltage acceleration (G) of VT (I-V), NIT (CP) and SVG (Noise)Similar reduction of G for VT, NIT and SVG with increase in N (trap generation near interface)
37
Direct Comparison of Multiple MeasurementsTwo measurement methods in sequence to determine VT and NIT during stress and recovery
Measurement (stress off) triggers recovery, captured degradation depends on measurement time and gate voltage during measurement
Less issue if measured long time after stress is stopped, as recovery goes in log-time scale
Measured degradation (during stress) depends on measurement sequence
Yang, VLSI’05
Comparison of CP and OTF-IDLIN (t0=1ms)
100 101 102 10310-3
10-2
7x10-2
PNO (29%, 2.14nm)
On-the-fly Idlinn=0.15
VG=-3.0V; T=150OC
C-P, n=0.26
VT &
q.
NIT/C
OX (V
)
stress time (s)
As measured difference ~ 10X NBTI not due to trap generation?
Band gap scan: Full for IDLIN, partial near midgap for CP
Correct for band gap difference
Inherent recovery for CP
Correct for recovery
Final difference within ~ 20%
StressCP Meas.
Stress
IDLIN CP
38Mahapatra, IRPS’07
Low Voltage (LV) SILC
39
Increase in gate leakage current after stressKimizuka, VLSI 00
Stathis, IRPS’04
Two peaks evolve with stress time at VG~VFB (1V) and VG ~ 0V
LVSILC increase ~ Interface trap generation
SILC (~VFB) due to electron tunneling from Si/SiO2 to SiO2/poly-Si interface traps
Krishnan, IEDM’05
SILC (~0V) due to VB electron tunneling from poly-Si to Si/SiO2 interface traps
Anomalous NBTI Degradation?
Identical time exponent (n) at different (lower) stress VG – “normal NBTI”
Increase in n at higher stress VG – contribution from additional physical process?
Chen IRPS’05
40
Similar effect seen in thicker oxideMahapatra, IEDM’02
10-1 100 101 102 103 104 10510-3
10-2
10-1
100
stress time (s)
T=25OC TPHY=36A
-VG(V) 4.50 5.255.50
V T shi
ft (V
)
Anomalous NBTI – Bulk Trap Generation
41Mahapatra, IEDM’02
10-1 100 101 102 103 104 10510-3
10-2
10-1
100
stress time (s)
T=25OC TPHY=36A
-VG(V) 4.50 5.255.50
V T shi
ft (V
)
Increase in “n” also seen for high stress VB
10-1 100 101 102 103 104 10510-3
10-2
10-1
VG=-4.5V
T=25OC, TPHY=36A
VB(V)0.04.05.0
stress time (s)
VT s
hift
(V)
Higher n coincides with SILC (~generation of bulk oxide traps)
10-1 100 101 102 103 104 105
0.0
0.5
1.0
1.5
2.0
2.5
stress time (s)
SIL
C (%
, VG=-
4V)
10-1 100 101 102 103 104 105
0.0
0.5
1.0
1.5
2.0
SIL
C (%
, VG=-
4V)
stress time (s)
IG
IB
ISD
Hot Hole Induced Generation of Bulk Traps
VB >0
IGIB
ISD
HH generation at higher VG reproduced by VB>0 at lower VG
100 101 102 103 1042x109
1010
1011
Difference
VB=0VVB=2V
NIT (c
m-2)
stress time (s)
2x10-1
100
101 SILC
(%, V
G =-2V)
T=27OC TPHY=26AO VG=-3.1V
SILC
Increased n at VB>0, presence of SILC, similar degradation of SILC and enhanced degradation
0 1000 2000 3000 40000
2
4
6
8
Difference
Recovery: VG, VB=0V
VB=2V
VB=0V
T=27OC, TPHY=24AO, VG=-3.1V
NIT (1
010 c
m-2)
stress / recovery time (s)
No recovery of enhanced degradation for VB>0 stress
42Varghese, EDL Aug’05
Summary
Differently processed devices show difference in pre-existing bulk traps (Flicker noise on pre-stressed devices)
43
NBTI: Generation of interface traps, charging of pre-existing and generated bulk traps
Interface / near interface and bulk trap generation signatures shown by multiple measurements
Evidence of interface / near interface trap generation from DCIV, high frequency charge pumping, LVSILC
Evidence of bulk trap generation from HVSILC
Several important factors need to be carefully considered if attempts are made to compare multiple measurements
Outline
Introduction, Basic NBTI signatures
44
Role of Nitrogen – Study by Ultrafast measurement
Estimation of pre-existing and generated defects
Predictive modeling
Fast / Ultra-fast drain current degradation measurement
Conclusions / outlook
Transistor process / material dependenceGo to Part – II