Assume for the problems below that VVtnbodyeffect is .9 V. Assume ß

1. a) (10 %) Identify the sources and drains in a transmission gate at t=0+ when V= 1.4 v. Let Vgn = 2.5 v, and Vgp

b) (15 %) What regions are the two transistors in when t=0justify your answers. !MOS transistor at t=0+ Step 1: Is there body effect? Yes, there is! F Step 2: Is the transistor ON? Vgs ≥ Vtnbodyeffect? 2.5-.3≥ .9? Yes, the transistor is ON! 2.2≥ .9? Yes, the transistor is ON!

Step 3: Is the transistor in Linear region or in Saturation region?

Vds ≥ Vgs-Vtnbodyeffect?

1.4-.3≥ (2.5-.3) - .9?

1.1 ≥ 2.2-.9?

1.1 ≥ 1.3? The inequality is false, so the

Solution: Homework Assignment #4 EE 477 Fall 2014 Professor Parker

Assume for the problems below that Vdd = 2.5 v, Vtp0 is -.7 v. and Vtn0 is .7 V. VAssume ßn (kn)= 219.4 W/L µ A(microamps)/V2 and ßp (k

Identify the sources and drains in a transmission gate at t=0+ when Vgp = 0.0 v.

b) (15 %) What regions are the two transistors in when t=0+? when t= infinity?

ere body effect? Yes, there is! For our analysis we use Vtnbodyeffect =.9 V

Yes, the transistor is ON!

.9? Yes, the transistor is ON!

Is the transistor in Linear region or in Saturation region?

1.3? The inequality is false, so the SMOS transistor is in linear region at t=0+.

Vtpbodyeffect is -.9 v. and (kp)= 51 W/L µ A/V2

Identify the sources and drains in a transmission gate at t=0+ when Vin = .3 v and Vout

t= infinity? Be sure to

or our analysis we use Vtnbodyeffect =.9 V

at t=0+.

PMOS transistor at t=0+

Step 1: Is there body effect? Yes, there is! For our analysis we use Vtpbodyeffect = -.9 V Step 2: Is the transistor ON? Vgs ≤ Vtpbodyeffect? 0-1.4≤ -.9? Yes, the transistor is ON!

Step 3: Is the transistor in Linear region or in Saturation region?

Vds ≥ Vgs-Vtpbodyeffect?

.3-1.4 ≥ (0-1.4) – (- .9) ?

-1.1 ≥ -1.4+.9?

-1.1 ≥ -.5? The inequality is false, so the PMOS transistor is in Saturation region at t=0+.

!MOS transistor at t=infinity Step 1: Is there body effect? Yes, there is! For our analysis we use Vtnbodyeffect =.9 V Step 2: Is the transistor ON? Vgs ≥ Vtnbodyeffect? 2.5-.3≥ .9? 2.2≥ .9? Yes, the transistor is ON!

Step 3: Is the transistor in Linear region or in Saturation region?

Vds ≥ Vgs-Vtnbodyeffect?

.3-.3≥ (2.5-.3) - .9?

0 ≥ 2.2-.9?

0 ≥ 1.3? The inequality is false, so the SMOS transistor is in linear region at t=infinity.

PMOS transistor at t=infinity Step 1: Is there body effect? Yes, there is! For our analysis we use Vtpbodyeffect = -.9 V Step 2: Is the transistor ON? Vgs ≤ Vtpbodyeffect? 0-.3≤ -.9? The inequality is false, so the PMOS transistor is in Cutoff region at t=infinity.

2. a) (10 %) Assume that an inverter is on segment A of the input/output transfer curve. What is the range of input voltages that will prevent the inverter to move into segment B after reaching steady state?

The range of voltages is the range that allows the SMOS transistor to be in cut-off region and the PMOS to be in linear region. Sotice that both conditions should happen.

The SMOS is in cutoff when the input voltage Vgsn is less than Vtn0.

So, the range of voltages at the input is any voltage that is lower than Vtn0. Vgsn < Vtn0.

b) (2%) is there current flow between the vdd and gnd path of the inverter while the inverter is on segment A?

If Vin is near to 0.0 V, the current flow is negligible because the SMOS would be considered to be OFF. As we increase Vin reaching near Vtn0, then there would be some small current flow (subthreshold current) because the SMOS is not completely OFF. 3. a) (5%) Assume for an inverter kn > kp. Would the input/output voltage transfer curve stays longer on segment A? If not, briefly explain what happens to the input/output voltage transfer curve.

It doesn’t stay longer in segment A. When kn > kp the switching from a high output voltage to a low output voltage happens with an input voltage that is smaller than Vdd/2. Let us recall that the C region occur at Vdd/2 only when kn=kp. Sow that kn>kp, the C region moves to the left, reaching the “knee” of segment D with a smaller input voltage.

b) (3%) Assume that for the condition kn > kp, the inverter is on segment D of the input/output voltage transfer curve. What is the maximum value of input voltage that keeps the inverter in segment D?

The transition from region D to E occur when the PMOS transistor moves from Saturation to Cutoff region, while the SMOS transistor remains in Linear region. The maximum voltage to keep the inverter in segment D should be Vin<Vdd+Vtp0 to prevent the PMOS to move into Cutoff region.

4. (5%) Assume kp=kn, what is the maximum output voltage to stay on region D?

When kp=kn, the C region is at Vin=Vdd/2. Let us find Vdsn (output voltage) at the limit when the SMOS moves from linear region (segment D) to saturation region (segment C). That condition occur when

Vdsn=Vgsn – Vtn0

=Vin – Vtn0

=Vdd/2-Vtn0

Therefore, the maximum voltage to stay in region D is Vout less than Vdd/2-Vtn0.

What would be the region of operation of the transistors if we exceed that voltage?

In region D, PMOS transistor is in Saturation region, while SMOS is in linear region. If we exceed the maximum output voltage the inverter moves to C region, where the PMOS and SMOS are in Saturation.

5. (7%) Asssume that kn = kp, initially Vin=Vdd and so the PMOS transistor of the inverter is in cutoff region. What are the regions of operation of the transistors in the inverter when Vin decreases to 1.7 V?

Let us recall that when kn=kp, the C region is at Vdd/2. Vdd/2= 2.5/2 = 1.25 V. To be in the E region, Vin=Vdd+Vtp0=2.5 - .7=1.8 V. Therefore, at Vin=1.7 V, the inverter is in the D region, where the SMOS is in Linear region and the PMOS is in Saturation region.

6. (5%) If the segment C of the input/output voltage transfer curve moves to the right, what is the effect on noise margins? Is high noise margin or low noise margin affected?

If the C region moves to the right, the “knee” of the input/output transfer curve at which we measure VIL and VOH occurs with a higher input voltage. That is, VIL increases. Similar condition occurs for the “knee” of the input/output transfer curve at which we measure VIH and VOL. Therefore, VIH also increases. This means that LOW noise margin increases, while HIGH noise margin decreases (see the definitions in the answer for Q10b).

7. (3%) If the C segment occurs when Vin is lower than Vdd/2, what does that tell us about the ratio of kn and kp ? kp/kn<1

8. (10%) What are the regions of operation of the transistors in the inverter when there is a current spike?

both transistors are in saturation and current flows momentarily from vdd to ground.

9. (10%) An inverter has the transistors sized so that the ratio of kimply that the transistor switches from high to low with a larger or smaller input voltage?

When kp/Kn =.5, it implies that Kn>Kp, and the C region of the curve moves to the left, so that inverter switches from high to low

What regions are the transistors in when Vin = Vdd/2?

Vin=Vdd/2=1.25 V

Vdd+Vtp0 =2.5-.7= 1.8 (condition for region E)

So, Vin=Vdd/2=1.25 V< Vdd+Vtp

The SMOS is in Linear region and theinput/output transfer curve.

10. a) (4%) Redraw the input/output voltage transfer curve of the inverter with the same details provided in solution of HW4 Fall 2012 . Identify VIHmin, VILmax VOHmin, and VOLmaxVOL) in the input/output voltage transfer curve of the inverter.input/output transfer curve = -1

Comment from Dr. Parker: Kang has a different definition for Voh and Vol

An inverter has the transistors sized so that the ratio of kp to kn = .5.switches from high to low with a larger or smaller input voltage?

When kp/Kn =.5, it implies that Kn>Kp, and the C region of the curve moves to the left, so that inverter switches from high to low with a smaller input voltage.

What regions are the transistors in when Vin = Vdd/2?

.7= 1.8 (condition for region E)

So, Vin=Vdd/2=1.25 V< Vdd+Vtp0 and transistors are in segment D.

The SMOS is in Linear region and the PMOS is in Saturation; they are in segment D of the

10. a) (4%) Redraw the input/output voltage transfer curve of the inverter with the same details provided in solution of HW4 Fall 2012 http://www-classes.usc.edu/engr/ee-s/477p/f12/asst4soln.pdf

Identify VIHmin, VILmax VOHmin, and VOLmax (in the text they use VIH, VIL VOH, and VOL) in the input/output voltage transfer curve of the inverter. Identify both points where slope of

1

Kang has a different definition for Voh and Vol.

= .5. Does this ratio switches from high to low with a larger or smaller input voltage?

When kp/Kn =.5, it implies that Kn>Kp, and the C region of the curve moves to the left, so that the

; they are in segment D of the

10. a) (4%) Redraw the input/output voltage transfer curve of the inverter with the same details s/477p/f12/asst4soln.pdf

(in the text they use VIH, VIL VOH, and Identify both points where slope of

b) (2%) Define VIH, VIL VOH, and VOL and write down the definitions of HIGH noise margin and LOW noise margin.

VIH= minimum HIGH input voltage VIL= maximum LOW input voltage

VOH= minimum HIGH output voltage VOL=maximum LOW output voltage

HIGH noise margin = VOH - VIH

LOW noise margin = VIL – VOL

c) (4%) To have an optimal inverter with high noise immunity, our goal would be to design an inverter such that VIH is very far from VIL or very close to VIL? Briefly explain your answer.

VIL should be as close as possible to VIH, so that the inverter switches as fast as possible from a low to a high output voltage or from a high to a low output voltage.

11. (5%) A novel inverter has the input/output voltage transfer curve like the one in the figure below. What are the values of VIL, VIH, VOL and VOH that give best noise margins? What are the HIGH and LOW noise margins?

VIH= minimum HIGH input voltage = 1 VIL= maximum LOW input voltage = .3

VOH= minimum HIGH output voltage = 1.2 VOL=maximum LOW output voltage = .3/2= .15

HIGH noise margin = VOH – VIH = 1.2 – 1 = .2 LOW noise margin = VIL – VOL = .3 - .3/2 = .15