Soi aalam

A

Presentation On

SOI Devices

Presented by:

Aalam Khan

1JNU ECE CA12014 SOI TECH

OutlinesOutlines

• Introduction• SOI Technologies• Advantages Of SOI• SOI Devices• Applications• Conclusion• References

JNU ECE CA12014 SOI TECH 2

IntroductionIntroduction• Increasing demand of high performance, low

power, small area can be achieved by SOI Tech.• SIO2 layer is created by flowing oxygen onto

silicon wafer.• Insulating layer reduces junction capacitance and

also reduce power consumption.• Floating body• Less area because no metal contact to wells


4

depletion regionThin body

JNU ECE CA12014 SOI TECH

Partially Depleted vs. Fully-Partially Depleted vs. Fully-

DepletedDepleted

• Partially-depleted SOIo The body is thicker than the depletion region, so bulk

voltage can vary depending on the amount of charge present

o This varying charge changes Vt because of the body effect

• Fully-depleted SOIo Body is thin, depletion region spans bulko Body charge is fixed, body voltage does not changeo Harder to make because of thin body


SOI TECNOLOGIESSOI TECNOLOGIES

• SOS (Silicon-On-Sapphire)

• SIMOX (Separation by IMplanted OXygen)

• BESOI (Bond and Etch-back SOI)

• Smart- Cut®

• ELTRAN® (Epitaxial Layer TRANsfer)


SIMOX SOI TechnologySIMOX SOI Technology

• High oxygen dose(standard)

• 1.8E18/cm2, 200 kev• low dose + high temp. oxidation

• Oxygen implanter development

• High current, low contamination, uniformity


AdvantagesAdvantages


Benefits of SOIBenefits of SOI

• Simple Isolation• Higher Density• Reduced S/D junction capacitance• No latch up• Low soft Errors• Speed Increases• Less Power consumsion• Less area



Fully depleted SOI

FD-SOI

Implementation

ARM7

SOI provides a viable low-power solution

1/3 power consumptionof bulk device with same performance


The inherent advantages of SOI are essential today

• Compared to bulk-CMOS, SOI technology offers–––––

Lower power, 30- 40% lower power (or higher performance)Less process complexity and variabilityMore reliable: 10x soft error rate reduction and no latch upFD- SOI/ FinFET: stable SRAMsSimplifies Digital, Analog and RF integration in SoCs

SOI DisadvantagesSOI Disadvantages

• Floating body causes the History Effecto This changes Vt, which changes the delay of the

circuit

• Self-heating• Modeling issues


Commercialized SOI WafersCommercialized SOI Wafers

• SOS : Kyocera, Union Carbide, Asahi kasei

• SIMOX : IBIS(Mitsubishi)

: NSC, Komatsu(NTT)

• Bond and layer transfer SOI

• : SOITEC, Canon, SiGen

• BESOI : Isonics, BCO, Hughes, SiBond


Present SOI Device and CircuitsPresent SOI Device and Circuits

• IBM : CPU with 300mm, 0.1 micron, Cu

• Motorola : commercial G4, 2GHz G5 power PC

• Intel : DST- sub 30nm TSOI, sub 70nm gate

• AMD : mobile, space, 64 bit MPU

• Honeywell : Rad-hard, space application

• HP : 64-bit RISC processor with copper

• IBM, Toshiba, Sony : supercomputer-on-chip


Present SOI Device and Circuits 2Present SOI Device and Circuits 2

•Hitachi : mainframe computers

•Mitsubishi : RF/anlog devices•Epson : low-voltage ASICs

•Fujitsu : high-speed logic devices (adder circuit)

•Seiko, Casio : wrist watch chip•Oki : low power high speed rf devices

•TSMC : 90 nm MOSFET with SOI


ApplicationsApplications

• Low power, high speed IC

• ULSI Circuit

• Rad-hard IC

• High power device

• High temperature device

• Si MMIC

• Sensor & MEMS application


I(In

SOI is part of your daily life!

Computing

Gaming

VNVehicle Networking)

Automotive

Quad-CoreDSP MSC8144

Networking

Images, Ultra LP


Tilted 3-D cross sectionof a FinFET on SOI

EmergingSOI application:

FinFETs manufacturing low variability & low cost

Challenge: In bulk-CMOS it’sdifficult to achieve an exact fin-height and minimize this additional variability.

FilmThickness



Optical waveguides

Challenge: To minimize signalloss and cost for optical interconnects both noise isolation and precision manufacturing are essential for highly integrated solutions.



CMOS image sensor

Challenge: Less expensivecameras and mobile phones demandsmall and low-cost image sensors, without trading off sensitivity or quantum efficiency.

Light passing througha thinned silicon wafer



Zero-Capacitor RAM

Challenge: SOC's memory content is constantly increasing.High-density, low-cost and low-power memories are essential for many systems.



SOI / XDM10 process> 350V D-S breakdown


High-voltage switching

Challenge: Car batteries will increase to 48V, hybrid batteriesoutput 200 – 300V and > 100A currents.


26 members so far, focused on reducing power

The SOI Industry Consortium

includes leaders in the

electronics industry from users

& enablers to suppliers &

manufacturers

ConclusionConclusion• After studying the various circuit issues of both

the technologies. SOI gives the superior results than Bulk technology, which increases

• The circuit performances, high reliability, removes the parasitic capacitance, punch through issue and the circuit compactness.

• Hence SOI technology is the leading and upcoming technology in both micro and nano electronics.


SOI ReferencesSOI References

• Proceedings• ECS SOI symposium proceedings• IEEE SOI conference proceedings

• Consortium industry

• TEXT• J.B.Kuo : CMOS VLSI Engineering : Silicon on

insulator


Thank you


Soi aalam

Design

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