Software-defined Radio using Software-defined Radio using XilinxXilinx

(SoRaX)(SoRaX)

By:By:Anton Rodriguez & Mike MensingerAnton Rodriguez & Mike Mensinger

Advised by:Advised by:Dr. In Soo Ahn & Dr. Yufeng LuDr. In Soo Ahn & Dr. Yufeng Lu

OutlineOutline Brief project overview/introductionBrief project overview/introduction Project Goals Project Goals Prior work and supplementsPrior work and supplements BackgroundBackground

Dissection of FlowchartDissection of Flowchart RequirementsRequirements EquipmentEquipment ScheduleSchedule

Project OverviewProject Overview A Software-defined Radio A Software-defined Radio

(SDR) offers a flexible (SDR) offers a flexible solution for many of solution for many of today’s communication today’s communication needs.needs.

The objective of this The objective of this project is to design a project is to design a communication radio communication radio system on the FPGA system on the FPGA board. board.

The main focus will lie on The main focus will lie on the carrier the carrier synchronization and phase synchronization and phase ambiguity correction from ambiguity correction from the received data.the received data.

We will start by designing We will start by designing a Simulink model of the a Simulink model of the entire system and then entire system and then implement it on the implement it on the SignalWave Virtex II FPGA SignalWave Virtex II FPGA board board ..

Project GoalsProject Goals Gain an in-depth Gain an in-depth

understanding about the understanding about the FPGA implementation of FPGA implementation of carrier synchronization.carrier synchronization.

Construct a working Construct a working Simulink model.Simulink model.

Implement the Simulink Implement the Simulink model on the FPGA board.model on the FPGA board.

Regenerate the carrier Regenerate the carrier and symbol timing to and symbol timing to decode the transmitted decode the transmitted digital data.digital data.

Achieve fast acquisition of Achieve fast acquisition of carrier synchronization carrier synchronization and symbol timing through and symbol timing through efficient Xilinx efficient Xilinx programming.programming.

Create a test signal of Create a test signal of known hard-coded values known hard-coded values (preamble) to estimate the (preamble) to estimate the channel state.channel state.

If time permits, implement If time permits, implement different modulation different modulation schemes (i.e. 16-QAM).schemes (i.e. 16-QAM).

Previous Work / Previous Work / SupplementsSupplements

Xilinx 11.1 Example – sysgen Costas LoopXilinx 11.1 Example – sysgen Costas Loop• Referenced Phase-Locked Loop (PLL) FilterReferenced Phase-Locked Loop (PLL) Filter

FPGA Implementation of Carrier Synchronization for QAM FPGA Implementation of Carrier Synchronization for QAM ReceiversReceivers• By Chris Dick (Xilinx, Inc.)By Chris Dick (Xilinx, Inc.)

Previous Senior Project on QPSK receiverPrevious Senior Project on QPSK receiver• With phase-locked loopWith phase-locked loop• Incomplete…Incomplete…

BackgroundBackground E E 332 QPSK ProjectE E 332 QPSK Project

Wireless communication introduces distortions due to multi-Wireless communication introduces distortions due to multi-pathspaths

Need to regenerate the in-phase carrier signalNeed to regenerate the in-phase carrier signal

Send through channel

Recover carrier signal

Starting signal

)(n

)(ˆ)(ˆ nQjnI

)()( njQnI

High Level FlowchartHigh Level Flowchart

Send through channel

Recover carrier signal

Phase detector

Direct Synthesizer

Starting signal

Phase error correction

Noise

X

Corrected Signal

Phase-Locked Loop

Phase-Locked LoopPhase-Locked Loop

DDS

-sin(Өon+Ф)

cos(Өon+Ф)

FIRLPF

FIRLPF

r(n)

Loop Filter

X(n)I(n)

Y(n)Q(n)

Y(n)*I(n) - X(n)*Q(n)

Corrected Signal

+

-

Loop FilterLoop Filter

RequirementsRequirements The model shall operate with a system clock of 50 MHz.The model shall operate with a system clock of 50 MHz. There shall be an explicit sampling period of 1/8 There shall be an explicit sampling period of 1/8

throughout the Simulink model.throughout the Simulink model. The sampling frequency for the model should be 12.5 MHz.The sampling frequency for the model should be 12.5 MHz. We shall use the DDS compiler 2.0 to simulate our Voltage We shall use the DDS compiler 2.0 to simulate our Voltage

Controlled Oscillator (VCO) for the Phase-Locked Loop.Controlled Oscillator (VCO) for the Phase-Locked Loop. The frequency offset provided should be no larger than 1 The frequency offset provided should be no larger than 1

kHz.kHz. We shall follow the FCC Regulations for Radio Frequency We shall follow the FCC Regulations for Radio Frequency

DevicesDevices• Stay outside of the restricted bands of operationStay outside of the restricted bands of operation

EquipmentEquipment SignalWave Virtex II FPGASignalWave Virtex II FPGA

Xilinx - ISE 9.2 CompilerXilinx - ISE 9.2 Compiler

Virtex 4 FPGAVirtex 4 FPGA

ProgressProgress To this point, we have To this point, we have

dissected all of the models we dissected all of the models we were given.were given.

Researched phase-locked Researched phase-locked loops and their components.loops and their components.

Isolated components have Isolated components have been tested to be functional:been tested to be functional:• Phase detectorPhase detector• Loop filterLoop filter• DDS compilerDDS compiler

Dr. Lu’s revisionDr. Lu’s revision

ScheduleSchedule

WeeksWeeks TasksTasks

(Winter Break)(Winter Break)Compile a functional Simulink Compile a functional Simulink

modelmodel

Design Loop FilterDesign Loop Filter

1 - 21 - 2 Load model onto the Virtex 4Load model onto the Virtex 4

2 - 52 - 5 Develop training sequenceDevelop training sequence

5 - 95 - 9Develop an algorithm to correct Develop an algorithm to correct

phase ambiguity of QPSK phase ambiguity of QPSK symbolssymbols

10 - 1310 - 13 Implement 16 – QAM modulation Implement 16 – QAM modulation schemescheme

13 – 1513 – 15 Prepare Final Report and Oral Prepare Final Report and Oral PresentationPresentation

Questions?Questions?