Software Architectureof rhe B0BB and 8086Microprocessors

._RODUCTION

This chapter begins our study ofthe 8088 rnd 8086 micfoprocessors and thejr assembly:iguage programming- To program either rhe 8088 or 8086 using assembly l3nguage, we'nust understand how the microprocessor and ir! mcrnory and input/output subsystemsrDerate from a sofiware point of view. For this reason. in this chapter. we will eramine'.1: loltwarc drchitecture ofthe 8088 ind 8086 microprocesso.s The material that follou's:=quently refers only to the 8088 microprocessor, but evefything thal is described for lhe:,188 also applies to lhe 8086. This is because the softwarc architecture of the 8086 is:1.'iical lo that of the 8088. The following topics lre covered here:

2-1 Microarchitecture of the 8088/8086 Microprocessor

2.2 Software Model ofthe 8088/8086 Miffoproceslor

2.3 Memory Addrcss Space and Data Organization2.4 Data Types1.5 \egnenr Re-i . .e- JrJ \4eno^ Sermen': ' r ' '

2.6 Dedicated, Reserved, and General Use Memory

2.7 InstructionPointer2.8 Drta Regislels2.9 Poinrer and Index Registers2.10 Status Registcr

27

2.ll Generating a Menory Address2.12 The Stack2.13 lnput/Output Address Space

2.I MICROARCHITECTURE OF THE8088/8086 MICROPROCE5S0R

The microarchitecture of a Focessor is its intemal architecture-ihat is, dle circuit build-ing blocks that implement the softwlre and hardware archiiectures of ihe 8088/8086microprocessor's. Due to the need for additional fbatures and higher perfbrmance, themicroarchitecture of a microprocessor family evolves over time, In facl, a new micro-architecnrre is introduced for Intel's 8086 fanily every few yea$. Each new genemtion ofprocesso$ (rhe 8088/8086, 80286, 80386, 80846, and Penrium processors) represenrssigni6cant changes in the microarchilecture of the u086.

The microarchitectures of the 8088 and 8086 icroprocessors arc simildr. Theyboth el|.ploy parallel tmcerrirg-that is, they rre iDrple e ted with several simulla e-ously operaling processing units. Figure 2-l(a) illustrates lhe iDtemal architecture of the8088 and 8086 mjcroproc€ssors. They contain two p ro.essing ]ux,ils: the bus interlace unh\BIU) and lhe execution uril (EU). Each unit has dedicated funclions and both operate atthe same time, ln essence, this palallel processing elTeclively makgs the fetch and execu-lion of instruclions indepeodenl operations, This results in efficient use ofthe system busand higher performance for 8088/8086 microcomputer systems.

The bus interface unit is ihe 8088/8086's connection to the outside world. By inter-face, we mean the path by whioh h connects to external devices. The BIU is responsibl€for performing all external bus operations, such as instruction fetching, reading and w,it-ing of data operands for memory and inputting or outputtlng data for input/output pei-pberals, These inlbrmadon translers lake place over tbe system bus, This bus includes an8-bit bidirectional data bus lor the 8088 (16 bits for the 8086), a 20-bit address bus, andlhe signals needed to contlol tansfers over the bus. The BIU is not only responsible forperlbrming bus operations, it also performs ofier lunctions related to instruction and dataacquisidon, For instance, it is responsible for instruction queuing and address gederaiion,

To implemenr these firnctions. the BIU contains the segment registers, fie instruc-tion pointer, the address generation adder, bus controi logic, and an instruction queue.Figwe 2 l(b) shows the bus interface unit ofthe 8088/8086 in more detail. The BIU usesa mechanism known as an inttruction que e ta lmplement a pipelined architecture. Thisqueue permits the 8088 to prefetch up to 4 bytes (6 bytes for the 8086) of instmctioncode. Whenever the queue is not firl-that is, it has room for at least 2 more bytes, and.ai the same time, the execution unit is not asking it to read or write data from memory-the BIU is free to iook ahead in the program by Fefbtching the next sequential instruc-tions. Prefetched instructions are held in the first-in first out (FIFO) queue. whenever abyte is loaded at the input end of the queue. it is autonaticdily shifted up through theFIFO to the empty location nearest the output. Here the code is held until dre executionunit is ready to accept it. Since instructions are nomally waiting in the queue, the timeneeded to felch n1sny instructions of the microcompuier's progam is etiminated. If thequeue is full and the EU is not requesting access to data in memory, the BIU does not

28 Software Architecture of the 8088 and 8086 MicroDrocessors Chao. 2

INSTRUCTIONPIPELIIIE

SYSTEM AUS

(a)

lus ||{iEaFlcc uxrr lrru)

{bt

Figurc 2-1 (a) Pipelined echitecture of the 8088/8086 microlrocessors (RePrtuted

wiih pemi$ion of l;tel Corloration. Copltisht/Intel Corp 1981) (b) E\ecution dd businterlace uits. (Reprinted with permission of Int€l Corp . ColyriShvlntel Corp l98t)

2l)

rc€d 10 p€rform atry bus opflations. These intervals of no bus activity, which occurb€twe€n bus opemtions, are k'rc.itn as idle states.

The execution unit is responsible fo. decoding and executing instructions. Notice inFig. 2-1(b) that it consists of ile arithmetic loqic unit (ALID, status and control flags,general-purpose registers, and temporary-operand registers. The EU accesses instuctionsftom the output end of the instuction queue and data from the general-purpose registersor memory. lt reads one instuction byte after the other liom the output of the queue,decodes them, generales data addresses if necessary, passes ihem to ihe BIU and requestsit to perform the read or write operations to memory or I/O, and pefolms the operationspecified by the instruction- The AIU perfoms the arithmetic, logic, and shift opemrionsrequircd by an instruction. During execution of the instruction, ihe EU may test the status and contlol flags, md updates these flags based on the results of exe.uting ihe instruction. If the queue is emptt the EU wairs for ihe nexr instrucrion byte to be fetched andshifted to the toD of the oueue.

l' 2,2 SOFTWARE MODEL OF THE8088 /808 6 MTCROPROCESSOR

The pwpose of developing a soltuate model is to aid the Fograrnmer in understandingthe operation of the mioocomputer system from a software point of view To be able toFogram a microprocesso! one does not need to krow all of its hardware architecturalfeatures. For instance, we do not necessarily need to know the functjon of the signals atits vrrio s pjns, their electrical connections, or their electrical switching characterisrics.The function. interconnection, and opemtion of the intemal circuits of the microFocessoralso may not ne€d to be considered. Wlat is important to the progammer is to know thevarious registers within rhe device and to undefitand their purpose, functions, operatingcapabiiiries, and linitations. Fudhemore, it is essential that the Fogrammer knows howextemal memory and input/outpur peripherals are organized, how info.mation is anangedin registers, memory and input/ouFul and how mernory and I/O are addressed to obraminstuctions and data. This information represents the software archilecture of the processor. UDlike the miffoarchitecture, the software architectdre changes only sllghtly liomgeneration to generaiion of processor

The software nodel in Fig. 2 2 illusaa&s the software archiiecrure of rhe 8088microprccessor Looking at this diagam, we see rhat it includes 13 16-bit intemal reg1s-te'the instruction pointer (lP), fow tta fgisten (AX, BX. CX, and DX), two pdl"re.r'€sirt?r'r (BP and SP), two inder leqistets (SI nd DD, and four r"gr€nt resisreff (CS.DS, SS, and ES). In addition, there is another register called the rtdrrr /e8trt / (SR), withnine of its bits implemented as status and control flags.

Figure 2-2 shows that the 8088 architect$e implemenfs independent memory andinpui/ouQut address spaces. Notice that the memory addrcss space is 1,048,576 bytes(lMbyte) in length and the I/O address space is 65,536 byres (64Kbyret in length. Ourconcem here is what can be done with this software architecture and how to do it duoughsofrware. For this purpose, we wil now begin a derailed srudy of the elements of rhemodel and their relationship to software.

30 Software Architecture or the 8088 and 8086 Microorocessors Chao. 2

------__-lrp

_lD5

ss

SI

OI

:rtl]

Figurc 2-2 Sotrde model of the

I.'EMORY ADDRESS SPACE]ATA ORGANIZATION

lar; ':har we have inhoduced the idea of a softwa:,:. iu.h as numbers, characters, and instrucnon-j: l-j. fie 8088 microcomputer suppods lMb)ra: rr orgrnized from a software point of view as<--:r. addresses over the address range 0000016lltlrared nicrocomputer is actually orsanized al

T.e 8088 can access any two consecutive by,-- . : , lJr( . .ed b)re . rhe lea.r -gnih.!1r bJIe ,,.:-: r! ::! mosl significmt byle. Figure 2 4(a) showr-, \.ace that &e storage location at the lower:.1r.' , ' r0- : 0216 The contents of the next-highe: iLl101r = 5516 These two bytes represent th

: : MemoryAddress Space and Data

8088/8086 microprocesor

ioftware nodel. let us look at how infoma-nctions is stored in mernory As shown inlMbyte of extemal memory. This memory

iew as individual byies of data stored at con-00016 to FFFFFL,j. Therefore, memory in anized as 8-bit byies, not as 16-bit words.jve bytes as a i,o.d of data. ln this case, ihebyte of the word, and the higher addressed) shows how a word of data is stored in memlower address. 0072,1 6. conrains dre value-higher-ad&essed srorage locatiqn. 0072516.rent the word 0101010100000010, = 550216.

3 l

T--_:-=-1

r;;-]l l

F--o1o'1I *" .ool

Figure 2-3 Menory addr€ss spaceof ure 8088/8086 nimproc€sor

To permit efncient use of memory words of alata can be srored ar what are calealeven- or odd-adalressed wod boundaries. The least significanr bit of the address dererminesthe type of word boundary. ff this bit is 0, the wod is at an eyen-addrcss boundary_tharis. a word at an even addles bounddry corresponds ro r\ o con5ecurjve tye.. wifi rteleast significant blte located ar an even address. For example, the word in Fig. 2 4(a) hasits least signilicanr byte ar addrcss 0072416. Therefore, ir is srorcd ar an even_adalrcss

A word of data stored ar an even-address boundary, such as 0000016, 0000216,0000416, and so on, is said tobe an atigned word-aat is. af aigned woras are locatJat an address that is a multiple of 2. On the other hand, a woral of data stored ar an odd_address bourdary, such as 0000116, 0000316, or 00005 16 and so on, is caled a rrtrati{rralwrfd. figure 2-5 shoq s some aligned dnd misaligned wordq of dara. Here word. 0. 2. 4.and 6 ate examples of aligned-dara words, while words I and 5 are misaliqned worts.\oaice fiar misaligned word i consisr. of blle I lrom atigned uord 0 and blre 2 fromaligned word 2.

wllen expressing addresses and data in hexadecimal form, it is cofiunon ro use theletter H io specify the base. For insrance, the nunber 00A816 can atso be writien asOOABH-

l l| l | r 1 r10 r

Il 10 ro1o1o I

{bJ

Fkure 2-4 (a) Sto.ins a word of dara in memory. (b) A! eiarnple.

Soilware Architecture or the 8088 and g086 Mjcropfocessors

00725i6 0072c8

oor2B,6

32 Chap. 2

00008H

00007H

00006H

00005H

00004H

00003H

00002H

oooolH

00000H

Byre I

B!1e 7

Byre 6

Byls 5

Byre 4

Byre 3

Blt€ 2

Bis 1

By,le 0

_l

5I

-l

1_ l

t\4isaligned Figure 2-5 Examples of aligned andwods misaligned data words

EXAMPLE 2.I

Wlat is the data word shown in FiS 2 4(b)? ExFess the result in hexadecimal form ls

it stored at an even- or odd-addressed word boundary? Is it an aligned or misaligned word

of data?

SolutionThe most significant byte of the word is stored at address 0072Cr6 and equals

1 1 1 r 1 1 0 1 , = F D r 6 = F D H

Its least signifi€ant byte is stored at address 0072816 and is

1 0 1 0 1 0 1 0 r = A A 1 6 = A A H

Together the two b''tes give the word

1111110110101010, = FDAAT6 : FDAAH

Expressing the address of the least signiicant byte in binary form gives

0072BH : 00728t6 = 0000000001110010101l'z

Because the dghtmost bjt (lJB) is logic I' the word is storcd at an odd-address bound-

ary in memory; therefore, it is a misaligned word of data'

; .6

;.

il.2

;,.0

I

5ec. 2.3 Memory Address Space and Data Organization 33

Aigned

-l

Doubl€

I

0

T\e double wod is af'ofier data form that can be Focessed by the 8088 miclo-computer. A double word conesponds to four consecutrve bytes of data stored in mem-ory; an example of double-word data is a /oint€,: A pointer is a two-word address elementthat is used to access data or code in rnemory The word of this pointer that is srored atthe higher address is cale.d the se7ment base addres8 and the word at the lower addressis called the o.fr€t

Just lile for words, a double word of data can be aligned or misaligted. An aligneddouble word is located at an address that is a multiple of4 (e.g., 0000016, 0000416, and0000816). A number of aligned and misaligned double words of data are shown inFig. 2 6. Of tbese six examples, only double words 0 and 4 are aligned double words.

An example showing the storage of a pointer in memory is given in Fig. 2-7(a).Here the higher-addressed wo.d. which represents the segment base adalress, is stored

Figure 2-6 Examples of atgned mdmissligned double words of daia.

00008H

00007H

00006H

00005H

00004H

00003H

00002H

00001H

00000H

Byte 8

Byre 7

Byts 6

Byle 5

Byle 4

Byre 3

Byle 2

By,le 1

By,te 0

lDoubl€

"g'd --l

i-- || |

Ddbre

I oo,ur" s

Doubie 2

I __ll

| 38 J 00008,6 | ao I

t-. "--l oooor,. frr- ooloooos,"l---il

fi- 5_l ooooe,"f--;_l

Figure 2-7 (a) Storilg a 32-bit pointei in nenory. (b) An examlle.

software Architecture of the 8088 and 8086 Microprocessors Chap. 234

I

:iaiing at even-ad&ess boundry 0000616. The most significant byte of tbis word is at:ddress 0000716 and equals 00111011, : 38!6. lis least sig.iGcanl byte is at addressr]10616 and equals 01001100, = 4C16. Combining ihese two valucs, we get lhe segment

rlrle addrcss. whjch cqmls 0011101101001100, - 3B4Cr6The o$set paft of the pointer is the lower addressed word. Its leasl significant

r\re is stored at address 0000416; ihis location coniains 01100i01, = 6516 The nost!:gnificanr byte is at address 00005 6, which contains 00000000' : 0016. The resultingrr'-ser is 0000000001100101, = 006516. The complete double word is 384C006516.S:nce this double word stads ar address 0000.116, it is an example of an aligned double

.XAMPLE 2.2

ir{ should the pointer with segment base address equal to A00016 and o11iet addrcss

::FFr6 be siored at an even-ad&ess bounday starling at 0000816? Is the double wod

r::ned or nisalisned?

:Jlut ion

::.age of fie two word pointer requires four consecutive byte locations in memory, sta(:: al address 0000816. The ler.st signilicant byte of the offset is stored at address 0tl008r,j

r: ii shown as FF16 in Fig. 2 7(b). The most significant byle ofiheoffset,5516, is stored

. =idress 0000916. These two bytes ffe folowed by the lcast significant byte of lie seg-

-.:ri base address, 0016. at address 0000A16, and its most signilicant byte, A016, qt

:i-3,s 0000816. Since lhe double word is slored in memory starting ai address 0000816,

: r- Jrgned.

-=ATA ryPES

::E ti..eding section identified the fundanental data fonnats of the 8088 as the byte

I :'j,. $ord (16 bits). a.d double word (32 bits). lt also showed how each of these ele--i.-i ii llored in memory. The next step is to examile the rypes of dalr ihat can be codedn r?rP f^m 'R lnr nrn.Pccino

The 8088 rnicroFocessor dirdtly processes data exprcssed in a number of differ-

:E :r riprs. Let us begin with the inteser ttuta tlpe. The 8088 can process daia as-::::c:. ahsigned ot signed trt€g?r' numbeN; each type of integcr can be either byte'wide

:' :::i-\\ide. Figure 2 8(a) reFesents an unsigned b$e irteger; this data type can be

r-: :'represent decimal numbers in the range 0 tkough 255 The unsigned word inie

E r: .ir)$ n in Fig. 2 8(b); il cm be used to represent decinlal numbers in the range 0

F:!= 6:.535.

Dat Types 35

MSe

Figure 2-8 (a) Ursisnod byteinteger (b) Unsigned word iDtcg€i

EMMPLE 2.3

What value does the unsigned word integer 100016 regesent?

Solution

Fint, the hexadecimal integer is convcrted io binary fom:

100016 = 0001000000000000,

Nex1. we tind the value lor the binary number:

000r000oooooo0001 : 2''z : 4096

The signed byte integer and signed word inteser in Fiss. 2-9(a) and (b) are similarto the unsigned integer data iypes just intoducedi however here rhe most signilicant bitis a sign bit. A zero in this bit position identifies a positive number For this reason, fiesigned integer byte can reFesent decimal nunbers in the range + 127 to 128. and ihesigned inleger word pcrmits numbers in tbe range +32,767 to 32,768, respe.tively. Forexample. the nnmber +3 exprcssed as a signed integcr byte is 0000001l, (0316). On iheother hand, the 8088 always expresses negaiive numbers in 2's-complemenl notationTheretbe. 3 is coded as 11lll10l, (FDLJ.

I'igure 2-9 (a) Siged byre i.teger(b) Signed word integer

36 software Architecture of the 8088 and 8086 Mjcroprccessors chap. 2

qAMPLE 2.4

-{ ngned word integer equals FEFFT6 . W}at decimal number does it represent?

Solution

E\pre-mg fie he(adecimal numbe' in binary fonn gives

F E F F T 6 = 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 l ' ?

Since the most significant bit is 1, the number is negative and is in 2.s complemenr form.Converting to its binary equivalent by subracting 1 ftom rhe least significant bit and rhencomplementing all bits gives

FEFFT6 = - 0000000100000001'z

The 8088 can also process data lhat is coded as ,l ary-coded decinal (BCD) num-,"ru. Figure 2-10(a) lists the BCD values for decimal numbers 0 thmush 9. BCD data

BCO

123

6I3s

00{x)00010010001101000101

0 1 1 1r000100!

MSB

BCO Oigh

BcD Disit 1 BcDDieiro FiguE 2-I0 (a) BCD nubers. (b) AnUnpacked BCD digit. (c) Pacted BCD

(c) digirs.

D,

Sec. 2.4 Data Types 37

can be stored in eith€r unpacked or packed form. For instance, the unpacked BCD bvie inFig 2. r0{br ihowi lhar a ,ingle BCD digir \ jrored in rhe four teasr significanr bir:. andthe upper foul bits are set ro 0. Figure 2-t0(c) shows a byte wirh pa"Lea nCl atgitr.H€-re two BCD numbers are srored in a byre. The upper four bits repiesent the mostiig_nificant digjt of a rwo-digir BCD number.

EMMPLE 2.5

The packed BCD data stored at byre address 0100016 equal 10010001r. What is the rwo_digit decirnal number?

SolutionWdting the value 10010001, as sepamte BCD digits gives

10010001, = 100lBcD000lBcD = glro

. Information expressed in ASC (Ane can Standad Code Jbr Inlothlation Inter-c/r.up?) can also be direcrly phcessed b) fie 80gg microprocessor. ihe cban in Fig.z-rla) snous how numbers. letters. and control characters are coded in AscI. Forinslance, the number 5 is coded as

HrHo = 0110101 , = 35H

where H denotes that theAscll-coded number is in hexadecimal form. As shown in Fig.2-ll(b), ASCII d6ta are stored as one charactef Der Dvre.

EXAMPLE 2,6

Byre addresses 0110016 through 0110416 contain the ASCII data 0tOOO001, Ol010Oll,01000011. 01001001, rnd 01001001, r€specrively, Wha! do the data stand for?

SolutionUsing the charr in Fig. 2-11(a), the data are converted to ASCII as followsl

(01 100H) : 01000001Asc! : A

(01101H) - 0101001l^scl l = s

(01102H) : 0100001lAscl : c

(01103H) - 01001001Ascr - I

(01r04H) = 0100100lAsctr = I

3A software Architecture of the 8088 and 8096 Microprocessors Chao. Z

0 10

N 0 5 7

0 0 0 0 DLE

0 0 0 1 soN DCT

2 STX ac2 2 B

0 0 1 1 3 ETX sEOT T

0 1 0 1 5 ENO E

0 t 1 0

B E L

r 0oo H

HT E]VI I

1 o l 0 SUB zESC

L

1 1 0 1 GS

1 1 1 0 E

1 1 1 1 SI 7 o O E L

ASCII 0 s r

{b )

Figue 2-11 (a) ASCI lable. (b) ASCII digir.

MSB

I : 5 SEGMENT REGISTERS AND..,iMORY SEGMENTATION

Even though the 8088 has a lMbyre addrels space, not alt this memory is active ar oneune. Actually. the lMbytes of memory are paririoned into 64Kbyte (65,536) segnents.{ segment represenls an independently addressable unit of memory consisring ot 64K.onsecutrve byte wide storage locarions. Each segrnent is assigned a l7ar€ dddr,€rr tharidentifies its st:rting point-rhal is, ih lowest address byte-storage tocation.

Sec 2.c <,egmenr RFg\ er. <,nd VFmor) leg-err.r'on t9

Only four of these 64Kbyte segments are active at a tinet the code segmenL stacksegmenL d1ta segment, and ertu segmen' The segments of memory that are active, asshowninFig.212,areident i f iedbythevaluesofadalressesheldinthe80S8'sfourinter-nal segment registers: CS (code segment). SS (stack segment), rS (dala segment), and EJ(extra segment). Each of these registers contains a 16-bit base address that points to thelowest addressed byte of the segment in memory Four segments give a ma-\imum of256Kbytes of active memory Of this, 64Kbytes are for p tognn storuqe (code), 64KBresare fo{ a rtarl, and l28Kbytes arc for data storage.

The values held in these registers are referred to as the carrcnt-segment regktet wl',l€$ for example, the value in CS points to the fust word-wide stoBge location in the cur-rcnt code segment. Code is always felched from memory as words, not as bytes.

Figure 2 13 iluslJates the se?mentation of memory In this diagram, the 64Kbytesegments are identified with letters such as A, B. and C. The data segment (DS) registercontains the value B. Therefofe, the second 64Kbyte segment of memory liom the top,labeled B, acts as ille curcnt data-storage segment. This is one of the segments in whichdaaa that are to be pmcessed by the miqocomputer are stored. For this rcason, this part

__r J---

L-

Slack

8088/8086

csssDS

Enra

Figurc 2-12 Active segments of memory

00000H

40 software Architecture of the 8088 and 8oa6 Microprocessors ChaD. 2

-^-E1----* *l--}-r

"^'" "EF-*- "Eh FFl"EL- Figure 2-13 ContiSuous. adjeent,

disjoirted, and overlapping segnells.(Reprinted by permission of IntelCorp., Copyright/hiel Corp. 1979)

of the midocomputer's memory address space musr contain read/write storage locationsdat can be accessed by instructions as storage locations for sou.ce and destinationoperands. CS selects segment E as the code segment lt is lhis segment of memory fromqhich instuctions of ihe program are currently being fetched for execution. The stack

iegnlent (SS) register contains H, thereby selecting the 64Kbvte segment labeled ,s H forllr€ as a stack. Finally, the extra segment (ES) register is loaded with value J such that.egment J of memory functions as a second 64Kblae data stonge segment.

The segment registers are sedd to be user accessible. This means tbal the program-

rer can change their contents through software. Tberefore. for a program to gzrn access_ro another part of memory one simply has to change the value of the apFopriate register

.r rcgisters. For instance. a new data space, with up to l28Kbytes, is brought in simplyi'! changing the values in DS and ES.

There is one reslriction on tl alue assigned to a segment as a base addrcss: it must6ide on a l6-blte address boundary. This is because ircreasing the 16-bit v,lue in a seg-

r.rr register by I actually increases the conesponding memory address by 16i examples ofru.lid base addresses are 0000016, 000101 6, and 00020i6. other than this restriction. segments:a be sel up to be contiSuous. adjacent, disjointed, or ever overlapping; for example' m

FS. 2 13, segnents A and B are contiguous, whereas segments B and C are overlappitrg'

I Z6 DEDICATED, RESERVED,I'{D GENEML-USE MET,4ORY

rnl p3rt of the 8088 miclocomputer's lMbl'te address space can be implenented lbr the

€r's access: howeve( some address locations have dedicated f ctions utd sharld not

!E u-ed as general memory for storage of data or instmclions of a progam. Let us now

il\.t ar these reserved, dedicated use, and general-use parts of memory.

-EH-E-n-E

:t 26 Dedicated, Reserved, and Gen€fafuse Memory 4 l

Figure 2-14 shows the ,'ererye4 dedicated-use, afi seneruI-use parts of the8088/8086\ dddr€ff space. Norice rhat storage locations liom address 0000016 to 0001316are dedicated, and those ftom address 0001416 io 0007Fr6 are reserved. These 128 bytesof memory are used for siorage of pointers to inielrupt sgrvice routines. The dedicaredpait is used to store the pointers for the 8088's intemal intenupts and exceptions. On theoiher hand, the reserved locations are saved to srore pointers rhat are used by the user-defined interruprs. As indicated earlier, a pointer is a rwo-word address elemqnt andrequires 4 byies of memory. The word of this pointer at rhe higher address is caled thesegment base adahess and the word ar rhe lower ad&ess is rhe otrset. Therefore. rhis seution of memory contains up ro 32 pointers.

The part of the address space labeled dp?,? in Fig. 2 11 is general- :e memoryr ar:dis where data or instructions of the program are srored. Notice that ihe genefal use areaof memory is the range hom addresses 8016 lhrough FFFEFT6.

At the high end of the nemory address space is anorher reserved pointer area, tocatedfrom addrcss FFFFCr6 through FFFFFT6. These four memory locations are rese edforusewidr tuture products ard should nor be used. Inrel Corporarion, rhe original manufacturerof the 8088, has identified the 12 storage locations from address FFFF0 r6 through FFFFB ,.,as dedicated for functions such as storage of the hardware reset jump instruction. Forinstance, addrcss FFFF0I6 is $here the 8088/8086 begins execurion aJter receiving a reser.

2.7 INSTRUCTION POINTER

The rcgister that we will consider next in the 8088's softwa.re model shown in Fie. 2-2 isthe inntu.t ;un rviater t lPr. LP \ rr* , lb oi ts In lelgrh ,nd idenrjhe5 rhe ocario; o, Lhenext word of instfuction code to be fetched from rhe cunent code segment of memory. TheIP is similar to a progran counter: however, it contains ahe offset of the nexr word ofinstruction code instead ofits actual address. This is because tp and CS are both 16 birs inlength, but a 20-bit address is needed to access memory. Inremal to the 8088. the offset jnIP is conbined with the currenr vaiue in CS to generate ihe address of the insrrucrion code.Therefore, the value of the address for the next code access is ofte, deDoted as CS:I?_

rigue 2-14 Dedicated use,eseredi and general-use memory(Repdnted by lermission of IntelCorp., Copyrightl el Corp. 1979)

42 software A/chitecturc of the 8088 and 8086 MicroDrocessors ChaD. 2

During nom1al operation, the 8088 fetches instructions fiom the code sesmenr ofmemor). nore. rhem In iL5 inst uclior qL,eue. and e\ecuLe\ Inem one aller the olh;r Eve^rjnre d $ord ol code i\ lelched trom memo,). rtre 8088 upddres r}le lalue i" Ip.,.h r;;it points to the firsr byte of the nexr sequenriat word of c;de_that is, Ip is incrememedby 2. Actilally, Lhe 8088 preferches up to four b],tes of insrruction code into its intemalcode queue and holds them there waiting for execution.

A1ter an instrucrion is read irom ihe outpur of the ins!.udion queue, it is decoded: ifnecessaq. operand. are read rom eithef L}e dfla.egn.n, or..rno.1 or i emal regisrers.Next, the operation specilied in the instrucrion is performed on f]le operands and thirasultls written back b either an intemal regisrer or a srorage tocatiod in memory The 808g isnow ready to execute the nexi instruction in the code queue.

fxecurin8 an in,rrl,crior $ar toad" a neu ratui inro rhe CS regisler chatrges rheactive code segmenL rhus, any 64Kb],,re segmenr of memory can Ulsea to stire rnemsruc[on code,

. 8 DATA REGISTERS

As Fig. 2-2 shows, the 8088 has fow generat_purpose data registers. During plogramirecution. they hold temporary values of frequently used intermediate results. joftivare.an read..load, or modii, rheir conrents. Any of the general-purpose data regisre$ can beus€d as rhe souce or destination of an opemnd during an arithmeti; operarion such as{DD or a logic operarion such as AND. For instance, the values of tw; pieces of data,a and B. could be moved tron memory into separate data registers and operations suchas addition, subtraction, and muttiplication performed on them. The advaniage of storingiiese data in internal regisrers insread of memory during processing is that they can b!accessed much fasrer

The four rcgisterc, known as the data rcgiste$, are shown in more detail in Fig.l-15(a). Notice lhat they are rcfened to as the accumulator re|ister (A). the base regis;;rB),the count register (C), ̂ \dtt)e data rcgister (D).These names imply speciat firnJriors

t5

axBH BI

C H i C L

DXDH DI

BX

ctDX

Word nultipl,, *ord divid.,

Byt. oulriplr, bytg divjd., byt.I/O, translate, d.cj al uirhmcricByt. muhiply. byre divid.

Word hujtiply, yo.d dirid.,

Figum^2-15 _ra, Ceremt-purpo\e oora .egr.LeF ,Repinred b) prmNjo) ^l

In f , (orp. Cop)r igh. / tnret corp ta-or ,b , DeJi ;ared regi ,Lr r :mron.r <eor n ed b) pemr. ror o, In let corp. . ( ooyr rShr / t , re t aorp ta-o l

:?_ 28 Data Regisrers 43

they are meant to perform for the 8088 rnicropmcessor Figure 2 15O) summarizes theseoperations. Notice tbal slring and loop operations use the C register. For example, the vatuein the C register is the number of bytes to be processed in a string operation. This is the rea-son it is given the nane co&nr .e3drrer Another example of the dedicated use of data regis-ters is drat all input/output operations must use accumulalor register AL or AX lbr dala.

Each of these registers can be accessed either as a whole ( 16 bits) fot word dala oper-ations or as two 8-bit registers for byte-wide data opemtions. An X alter the register letteridentifies the reference ol a register as a word; for inslance, the l6-bit accumulator is ref-erenced as AX. Similady, the other thre€ word registen are referred to a-s BX, CX, and DX.

On the other hand, when referencing one of these registers on a byte wide basis,following the register name with ihe letter H or L. respectively. identifies the high byteand low byte. For the A register the most significant byte is refered to as AH and theleast significant byte as AL: the otber byte-wide register pairs are BH and BL, CH andCL, and DH and DL. When software places a new value in one byte of a register, lbrinstance AL. rhe vatue in the other byte (AH) does not change. This ability to processinformation in either byte location permits more efficient use of the limited registerrcsources of the 8088 microprocessor

Actually, some of the data registers may also store address informanon such as abase address or an input/output address;for example, BX could hold a 16-bitbase address.

2.9 POINTER AND INDEX REGISTERS

The software nodel in Fig. 2-2 has four other geneml purpose registers: two/o,r?ter'l€8irte6 and two index resisters. They siore what are called olfiz dddrei.!?r. An offsetaddress represents the displacement of a siorage location in meruory hom ihe segmentbase address in a segment register that is, it is used as a pointer o. index to select a spe-ci{ic storage locatron within a 64Kbyte segment of memory. Software uses the value heldin an index register to reference data in memory relative to the data segmeft or extra seg-mert registet and a pointer register to access memory locations relative to the siack seg-ment register. Just as for the data registers, ihe values held in these registers can be read,loaded, or nodilied ttuough software- This is done prior to executing the instructioD ihatreferences the reglster for address offset. Unlike the general-pui?ose data regisie|s, ihepointer and index rcgisters are only accessed as words. To use the offset address in a registet the instruclion simply specifies the rcgister that contains the v21ue.

Figure216showsthatthetwopointerregistersarethestoxkpointer(SP)Ntdbasepoirter (BP). The values in SP and BP are €d as offsets from the currenr value of SSduring the executior of instructions that involve lhe stack segment of memory and permiteasy access to storage locations in the stack part of memory. The value in SP always rcp-resents the offset of the next stack location that is lo be accessed. That is, combining SPwith the value in SS (SS:SP) results in an address that points to the top ,/tftc rtdct (TOS).

BP also represenls an offset relative to the SS; howevet it is used to access data withinthe siack segment of memory To do this, it is employed as the offset in an addressing modecalled the b6ed aAiressinq ,?,ode. One common use of BP is to reference parameten thatare passed to a subroutine by way of the stack. ln ihis case, instructions are included in thesubroutine that use based addressing to access the values of parameters from the stack.

44 Software Architecture of the 8088 and 8086 Microprocessors chap. 2

BP

SI

DIFigur€ 116 Poinler and index regjs,

D4tinarion indlr re^. (Rcpdnred by pemi$ion ofhrelCorp., Copyright/ tntel Corp. r979,

Tle index regisren are used to hold offset addresses for insructions rhar access datai-..d in the data segment of memory and are automatically combined with the vatue in- DS or ES register during address calculation. In instrucrions thal involve the rxrlaedrJ;ressing, the sauft:e index (Sl) register holds an offs€r address rhat identifies the toca_r:. oi a source operand, and the dertination index (DI) register holds an offset for a des-:::!on operand,

Earlier w€ poinled oul thal dny of the data registers can be us€d as th€ source or.r..inarion of an operand du ng an aritbmetic operation such as ADD, or a locic oDera,r:o ruch a. AND. However. tbr some operuuon.. dn operand thar i5 Lo be pruc;sed ma):e:trared in memory instead ofthe inlernal register In thls case, an index address is usedi: :.i.nlify the locdtion ofthe operand in memory; fol example, string instructions use ther:1r\ regtsters to access operands in memory. SI and DI. fespeclively, 4re the pointers toe .ou.ce and destination locations in memorv.

The ind€x registers can also be source or destination regis;rs in arithmetic and log-r:a op€ralions. For example, an instructjon may add 2 10 the o1L\ct value in Sl to incre_rc.r iN value lo point to the next word-wide storage location in memory.

E :' 'IATUS REGISTER

::e ,rdrrlr reSirle4 also called rhe fa1s rcgister, js another i6-bit rcsister within the 8088.=. i - t : - l7 .ho$s rhe orgrnrauon of lh15 regi\rer in morc deraj l . I ior ice that ru,r nine oir. irl. are .mplemenled. Sir oi lhese bir, repre.enr r,arrA y'r(J: the .ttry fo| tCF,.:c-:, .flas GF), autiliary &ftr fas (AF). ze n fas (ZF). sisn faT (SF), nJ ove tfow fa|-1a The logic srat€ oI these status flags indioate conditlons that a.e produced as th;

t-l

Figure 2-U Slatus and controt iiags.(Reprintcd by pemissioD of InLelCorp., Copyright/Intel Cory. 1979)

:e: 2 l0 Sraars Register 4S

resuli of executing an instruction-that is. after executing an instruction, such as ADD,

specific flag bits are resel (logic 0) or ser (logic 1) based on the result that is produced.

l,et us fifft summarize the operation of these flags:

l. The carry fa| GF): CF is set if there is a carry-our or a bonow-in for the most sig'

nificant bit of the result during the execution of an instruction. Otherwise. CF is reset

2. The paity fag (PF): PF is set il the result Foduced by ihe instruction has evenpariry-that is, if it contains an even number of bils at dre I logic level If pariry is

odd. PF is reset.3. The auaiLia,J ca a frag (AF)r AF is set if there is a cany-out from the low nibble

iDto the high nibble or a bolrow-in ftom the high nibble into the iow nibble of dre

lower byte in a l6-bit word. Otherwise, AF is resel.

4, The zero fag (ZF): ZF is set if the resulr produced bv an instruction is zero Other-

wise. ZF is reset.

5. The sign ltag 6F): The MSB of the result is copied into SF Thus, SF is set if the

resuh is a negative number or rcset jf it is positrve

6, The owdow fag (OF): When OF is set. it indicates that the signed result is out of

range. If the result is not out of range, OF rernains rcset

For example, at the completion of execution of a b)'te_additlon instruction, rhe carry

flag (CF) could be set to indicate that lhe sum of the operurds caused a carry out condition

The auxiliary crry flag (AF) could also set due to the execution of the instruction This

depends on whether or not a carry-out occuned from the least significant nibble to the most

significant nibble when the byte operards are added. The sign flag (SD'is also affected' and

it reflects the logic 1evel of the MSB of the result The oYerflow flag (OF) is ser if there is

a carry-our of the sign bit, but no carry into the si8:n bii (an indication of overltow).The 8088 provides instructions wlthin its instruclion sei ihat are able to nse these

flags to alter lhe sequence in which the program is executedi for inslance. a jump to

anothei palt of lhe program could be conditionally initiated bv testing for ZF equal to

logic. Thi. operarion i' ca\led pnp aa .ctoThe other three implemented flag bits-the diz.rion fraB (DF), ttje intempt enabte

f"tLs 0F), ad the trap fias GFFarc untrol fags 'I'nese thrce flags provide contol func-

tions of the 8088 as follows:

l. The trap fag (TF): If TF is set, the 8088 goes into the rinSl€ r/ep ,rod? of opera-

tion. When in the single-step mode, it executes an instruction and then jumps to a

specjal seflice routine that may deter rine the effect of executing the instructionThis type of operation is very useful ror debugging Fograms

2. Th? intetru!f"B t l Forrhe8088rorecogni/ena\\ablc,nrcr 'uPt 'c, |uc\t \at i t 'interrupl (INT) input, the IF flag must be set. When IF is reset, requests at INT are

ignored and the maskable interupi intedace is disabled

3. The dircctinn fag @F)r The logic level of DF detemines the direction in which

srring operaiions will occur When set, the slring instruction automatically decre-ments the address; therefore, the string data transfers Foce€d from high addressto low address. On the other hand, resetting DF causes the string address to beincremented thal is. daia transfers proceed from low address to high ad&ess

46 Soft\rare Architecture of the 8088 and 8086 [4icroprocessoG Chap. 2

The instruction set of the 8088 includes lnstruclions for saving, loading, or manip-ulating the flags; for instance, special instuctions are provided to pemit user software toset or rcset CF, DF, aDd IF at any point in the program (e.g., just pdor to the beginnin-q ofa slring operation, DF is reset so that the string address automatically inffements).

2,iI GENEMTING A IV]EMORY ADDRESS

A segment base and an offset descibe a logicaL addless in the 8088 microcomputer sys-tem. As Fig. 2-18 shows, both the segment base and offset are 16-bit quantities, since allregisters and memory locations used in address calculations are 16 bits long. However,rhe pbsical a&lrcss that is used to access memory is 20 bils in length. The generation ofthe physical address involves combining a 16-bit offset value that is located in the instruc-iion pointet a base register, an index register, or a pointer register and a 16-bit segmentbase value that is Iocated in one of the segment registers.

The source of ihe offset value depends on which type of memory reference is tal_ing p1ace. It can be the base pointer (BP) rcgisier, stack pointer (SP) register, base (BX)regisrer, source index (SI) register, destination index (DI) regjster, or instruction poinrer(IP). An offset can even be fonned from the contents of several of these regisren On theoiher hand, the segment base value always resides in one of the segnent registen: CS, DS,SS. or ES.

For instance. when an instruciion acquisition tsLes place, ihe source of the segmentbase value is always the code segment (CS) register and tbe source of the offset value is

15

f@orrser

SEGMENTADOEESS

FigE 2-18 Generatine a lhysicaladdres. (Repnnbd by pemission ofIntel Cory., Copyrighl/Iltel Corp. 1981)

3 7 ceneratjng a Memory Address 47

always the instruction pointer (IP). This physical addrcss can be denoted as CS:IP. On theother hand, il the value of a variable is written to memory durirg executior of an insiruc-tion, typicaly the segment base value is specified by the data segnent (DS) register andthe offset value by the destination index (DI) register-that is. the physical address isgiven as DS:DI. A provision c^lled the seqment-o)e//ide plerr is used to change the seg-ment ftom which ihe variable is accessed; for example, a prefix could be used to make adrra access occm in which the segment base is in the ES rcgister.

Another example is the stack ad&ess that is needed when pushing parameters ontothe srack. This physical address is lbrned fton dle values of the segment base in the stacks€gment (SS) register and offset in dre stack pointer (SP) rcgister and is described as SS:SP.

Remember that the segmeni base address reFesents the starting location of the64Kb''te segrnent in menory-that is, the lowest address byte in the segment. Figure 2 19shows that the offset identifies dre distance in b)1es that the storage location of interestrcsides ftoln dis starting address. Therefore, the lowest add.ess bl4e in a segment has anoffset of000016, and the highest addrcss byte has an offset of FFFFI6.

Figure 2-20 shows how a segment base value in a segment register and an offsetvalue are combined to form a physical address. The value in the segment register is shiftedleft by four bit positions, with its LSBS filled with zeros. This gives a regn€rt dddr€rr thelocation where the segment starts. The offset value is then added .o the 16 LSBS of thesbifte.d segment value. The result of this addition is the 20-bit physical address.

TIIe example in Fis. 2-20 rcpresents a sesmetrt base value of 123416 and an offsetvalue of 002216. First, let us exFess the segment base value in binary folm. This gives

123416 - 0001001000110100,

8088/8086

Bx -

f ;c l-

DS:BX

Data

DSr0000H

Highgsr addressed byle

Low€st addr€ss€d byl€

Figure 2-19 Boundariei of a s€gnent.

Soih,fr'are Afchitecture of rhe 8088 and 8086 l',4icroprocessors Chap. 248

i t33i",i,

Figure 2-20 Physicai address calcurauon exam!ie. (Reprinred br pemrs$on oftntet Corp.. Copyngbrtnlel

axA IPLE 2.7

Sbifting lefr four positions and fiiling wirh zeros resutts ln rhe segment address

00010010001 101000000, = 12340i6

The offser in binary form is

002216 : 0000000000100010,

\dditrg the segmenr address and the offset gives

0o010010001 101000000, + 00000000001000102= 00010010001101100010,- 1236216: 12362H

11i. addrcss calcularion is done automarically within the 8088 microprocesso. each tine: :.Fmory access is initiared.

.I:,-:"-:lo !" ". *::,,equired {o map to physicat address locarion 002c3r6 if rhe con_=:'j oi .he correspo.ding segment register are 002A,"?

_'

-- nrT.€t talue cdn be oblajned b) .hrlriog rhe conlerr\ ot rhe'.'- Ffl po\ '^n\ and then subLracring frum lhe phy,icai addre*.

002A0,6

\:-- i{5racdng. we ger the value of rhe offset:

002c3r6 - 02A016 = 002316

,\.ruly, many dilTerent logical addresses map rc me same plysical address loca_:.:!: - m.nory. Simply changing the segment base *1"" i, Ar" ,.g-*t *gi"r", _; il

segment register lefr byShifting left gives

z- i :. 1 Generating a Memory Addfess 49

corresponding offset does this. The diagram in Fig. 2-21 demonsrrares this idea. Noricethat segment base 002B16 with otrset 001316 maps to physical address 002C3r6 in mem-ory. However if rhe segment base is changed ro 0O2Cr6 wirh a new offset of 000316, rhephysical address is stin 002C3 16. We see rhar rle physical address 002BH:0013H is equalto the physical address 002CH:0003H.

A 2, 12 THE SIACK

As indicaied earlier, the rrac* is implenented in the memory of the 8088 micfoprocessor.and it is used for temporary storage of information such as dara or adajresses. Forinstance, when a call njfd.r'oa is execured, rhe 8088 automarically pusbes the currenrvalues in CS and IP onto the stack. Ar pan of rhe subrourirc, rhe contents of oiher regis,ters may also be saved otr the stack by execuritrg p6ft insfucrrorr (e.g., when the inst uc-tion PUSH SI is executed, it causes the conGnts of SI to be pushed onto the stack). Nearthe end of the subroutine, pop i'Ltttucnons arcircftded.o pop vatues {iom the stack backinto then conesponding intemal registers (e-g., POP SI causes the value at the rop of thestack to b€ popped back into SI). At rhe endof the subrouine, a retum instructio catfsesthe values of CS and IP to be popped off $e srack and put back into ihe intemal registerwhere they ofiginaly resided.

iII

____lFigurc 2-21 Reladonship betw@D logical dd phyrical addresses-(Reprinied by p€misior of Imel Corp., Copldeht/Inrel Corp. t9?9)

Software Architecture of the 8088 and 80a6 Microprocessors50 Chap. 2

The stack is 64Kbytes long and is organized from a software point of view as 32Kwords. Figure 2-22 shows that the segment base value in the SS register points to rhelowest address word in the cunent stack. The contents of rhe Sp and Bp register ofiserinto the stack segment of memory.

Looking at Fig. 2 22, we see that SP contains an offset vatue ihar points ro a sror-age location ir the cunent siack segmenr. The address obtain€d from the contenrs of SSand SP (SSTSP) is the physical adihess of the last stonge location in the stack ro whichdata were pushed. This memory address is known as the top d the stoxk. At 6e ricro-computer's startup, the value in SP is initialized to FFFq6. Conbining this value with thecurrent value in SS gives the highest-addressed word locarion in the srack (SS:FFFEHFl]:.at is.6e bottom of the stack.

The 8088 can push data and address infomation onto rhe srack from its inremalregisters or a storage location in memory Data transferred to and {iom the srack are word-wide, not byte-wide. Each time a word is to be pushed onro the top of rhe stack, rhe valueitr SP is first automatically decremented by two, and then the contents of the register arewritten into the stack part of memory. Therefore, rhe srack grows down in memory fiomthe bottom of the stack, which conesponds to the physical address SS:FFFEH, roward theend of the stack, which corresponG to the physical address obtained from SS and offserfiXjor6 (SS:0000H).

When a value is popped fiom the rop of rhe stack. the revene of this sequenceocculs. The physical address defined by SS and SP points ro the locarion of the last valuepushed onto the stack. Its contents are first popped off rhe stack and put inro ihe specificregister within the 8088; then SP is automatically indemented by two. The top of thenack then corresponds to the address of the previous value pushed onro ihe stack.

SS:FFFEH

4088/8046

T_ ^: --_l

r ^------

SS:SP

SS:0000H

-*. Z.l2 ihe stack

Figu.e 2-22 Stack segEent ofmemory.

5 l

^'trE-r,lI

tF!| ;-e) 23

Figure L23 (r) SLacklust Pnor to

Dush operation. (Reprintod bv t)erms';ion oilnlel corp . CoPYright/lnrelCorp. 1979) (b) Stacl aftei executioD.r the PUSH AX instiuction(RepnnreLl b |ermsr.n !f JnrelCorf. CuP)lrght/Iokl CorI1 lqT{)J

The example in Fig 2 23(a) shows how the contents of a register arc pusned onlo

*. sract. He,e we tind *re state of the stack priof to execurion of the PUSH AX instruc-

iion. Norice tt at ttre stacl segment register conrains 105 16. As indicated. the bottom ot tne

*.t .".id"'-"i*" ilt"rcaiaddress derived from SS and c'ffsei FFFET6 ThiF gjves the

bottom-of stack addrcss. ABos' as

A n o s : 1 0 5 0 1 4 + F F F E r oI t04t .

Fudhermore, the stack pointct which rcpresenls the offset from the beginning of ihe stack

;;;;;;t;" -*;' "f

ss to the top of $e stack' eq als 0008L6 rherefore' the cur

renr top otitre srack is at phvsical address Arcs' which equals

A r o s = 1 0 5 0 1 6 + 0 0 0 8 1 6: r 05816

Addresseswithhighervaluesf iantha!ofthetopofthestack'105816'containval idslackdata. Those with lower addresses Uo not yet contain valid stick data Notice that the la'st

value pushed to the stack in Fig- 2 23(a).is BBAAT6

iisure 2 23(b) demonstates what htppens when the PUSH AX instruct'on rs exe

.*u.'.i"]. *" i"JiiJi i"itiulv "ontuln"

tr" number 1234 L6 Nolice that execution of

*. *J i"u-".. **"s lhe siack poinier to be decremented by two but does not aftbct

tr," i""-"rts "r:,r'. "i*t

,egrnent register Therefore' the next stack access is to the loca-

ii""-."".'o""ii"g ," "uorJss

t0se,6 rnis tocation is where the value in Ax is pushed

N"i;i" .,i"i

*" -i" 'ie"ificant bvre of Ax which equals I 216' now rcsides in nemory

,aJ..' iosi ",

and th; least significant bvte ofAX' which is 34r'J' is held in memorv

address 10s6,6.

52 software Architecture or the 8088 'nd 8086 Microprocessors Chap 2

. .kt us next look ar an example in which srack data are popped Iiom the stack backI: l..l:cl:'. ff"T I il.ch !he] r ere pushed. Figr,. :_z+ it,ioa|* *,. .p.,"i,""--r"r r g . l - 1 4 t , ) . L n e ( l a c k i ' c b o q n r o b e i a r h e , t l e L l a r r e . u t r e d o u e r o o u r p r i o i p t S H e X

llTlli:].h" ''

l" .q,n. 0006,". ss equal, t0s ".

fie lddre$ ar ,he i,p or,r,. .".requals_ru)6rb- and the word at the lop ol Ue suck equaL l2J4r6.Figure 2-24(b) shows what happens when thelnsmction; pop AX and pop Bxare executed in that order Execution of the first instrucrion causes dre 80g8 to read theyalue from rhe top of the stack and put ir into the AX ..gir,", * f Z:+,". r.l"rr, Sp i, ln"*-menred ro gi\e0008 6 and dnolber read operar;on i\ in;riarea rrom Lte yact. fn.

"efonireao con^espond, lo lhe pop BX in5rucrioo. and ir causes rhe !alue BB{A-6 ro be loadedtnto the BX regisrer. Sp is incremented once more and lr"* eqr"ts 00OA,r. ih";f;;;new rop of stack is at address 105A,..

In Fig. 2-24rbr we.ee rhar tre latues rerd our ot addre.ses lO5o,. and 1058,"Rmain at rhese tocalions, bur osy, 1s";6. u, locdlionc rhal are dbove !h. iq;""il. ;;i:derefore, they no longer represent vatid stack dara. tf new infonnation is^pustea ioGsiack. these vaiues are written over,

I

II

II

II

J

exl-iT3.l-1

1062

r060

i05c

105A

105l

axfi-fi]..--.I

s'f;T;l-r i- i i

r062?060

l05E

106C

Figure 2-X .., Srd.t iJst pnor !o pop opetulion. IReDrinred b) pemi$ion orInrel Corp-Coplriehutnr, Corp tets;ft)Srskafte, rheercu;i;norlllepop

m,?'.ffi"3i ^*"*^ rxepirred bv pemi"'on of tntercorP copvrshr/

:E 2 t2 fte Stack

00

66

a8 99

12

89 AB

c0

5t

t lI l:qol

f ffiili Figure 2-2s Ioaodre"""pee1l | , RepruLed b) pemi* ,on or bat 1---------------Jor ( o!.. cop)ri8h,/tnret corp. o-ar

Any number of stacks may exist in an 8088 nicrocomputer. Simply changing thevalue in the SS register brings in a new stack. For instance, executing the instructionMOV SS, DX loads a new value fiom DX into SS. Although many stacks can exist, onlyone can be active at a time.

A 2.I3 INPUT/OUTPUT ADDRESS SPACE

The 8088 has separate memory and inpuroutput (UO) ad&ess spaces. The 1/o adl"Jjrydce it the place where I/O interfaces, such as pdnter and nonitor ports, are imple-ment€d. Figure 2-25 shows a map of dle 8088's I/O ad&ess space. Notice that ihisaddress range is from 000016 to FFFFI6. This represents just 64Kbyte addresses; there-fore, unlike memory, I/O addresses are only 16 bits long. Each of these addresses corre-sponds to one byte wide I/O port.

The part of the map from address 000016 through 00FFr6 is referred to as pdSe 0.Ce.tain of the 8088's I/O instructioDs can perform only input or outpul data-tansferoperations to l/O devices located in this part of rhe I/O ad&ess space. Other I/O instruc-tions can input or outpul data for devices located anywhere in the I/O address space. I/Odata transfers can be byte-wide or $,ord wide. Notice that the eight locations fromaddress 00F816 through 00FFr6 are specified as reserved by lntel Corporation and should

REVIEW PROBLEMS

Section 2.I1. Name the two intemal Focessing units of the 8088.2. Wlich processing unit of the 8088 is the interface to the outside world?3. wllat arc ihe length of the 8086's address bus and data bus?4, How large is the instruction queue of the 8088? The 8086?5. List the elements of the execution unit.

Section 2.26, Wlat is the pur?ose of a software model for a microprocessor?7. Wllat must an assembly-language Fograr ner know aboui the rcgisren within the

8088 miffoprocessor?

54 Softwarc Architecture of the 8088 and 4086 MicroDfocessors Chao. 2

8. How rnany registers are located widrin the 8088?9. How large is the 8088's memory address space?

10. How large is the 8086's I/O address space?

Section 2.311. What is the highest address in rhe 8088's memory address space? The lowesr address?D. fs memory in the 8088 microprocessor organized as byt€s, words. or double words?13, The contenls of memory locarion 8000016 are FFr6, and rhose ar 8000116 are 0016.

wllat is .he data word stored a1 address 8000016? Is the word ali$ed or misaligned?11. Wlat is the value ol the double word srored in nemory starting at address 8000316

if the contents of mernory ioca.ions B0003r5, 8000416, 80005 6, and 8000616 are1116, 2216, 3316, and 4416, respectively? Is this an exampie of an aligned double lvordor a misaligned double word?

15. Show how the word ABCD16 is srored in memory starring at address 0A00216. Is theword aligned or misaljgned'i

16. Show how the double word 123,1567816 is srored in memory starring at addressA00l16. Is the double word aligned or misaligned?

i:ct ion 2.4:-. Lisi five data types Focessed directly by rhe 8088.:( E\press each of the signed decimal integers that fo1low as eirher a blre- or word

le\adecimal number (use 2\-complemenr notation for negative nurnbers).,at + 121, b r 1 0' c ) - 1 2 8' d r + 5 0 0

:r. io\. would the integer in problem 18(d) be siored in memory starring ar address\r:llor6?

L :rn soutd the decimal number 1000 be expressed for processing by the 8088?::, :!:rejs the decimal nurnbers that follow as unpacked and packed BCD bytes.

a , t 9b . ! s

: i-; liould the BCD number in problen 21(a) be srored in memory srarring al.i-..-, 0800016? (Assune that the leasi significant digir is stored a1 rhe lower

= :-::i srarement is coded inASClI by the following binary srrings?

t 0 0 l 1 l 01000101101100010101000100000i00t 001

t5

24. How would the decirnal number 1234 be coded in ASCII and stored in memory start_ing at address 0C00016? (Assume that the least significant digit is storcd at the loweraddressed memory location.)

Section 2.525. How large is a memory segment in the 8088 midoprocessor?

26. W}ich of the 8088's intemal registe$ are used for memory segmentation?

27. Whar register defines the beginning of the cunent code segment in memory?

28. Wtat is the ma-dmum amount of memory that can be active at a given trme in the8088 microprocessor?

29. How much of the 8088's active memory is available as general-purpose data storage

Section 2.630. Wlut is the dedicated use of the part of the 8088's address space fton 0000016

though 0007F16?

31. What is the address range of the general-use part of the memory adahess space?

32. Which part of the 8088's memory address space can be used to siore the instruciionsof a Plogram?

33. what is stored at address F!FF0r6?

Section 2.734. What is the function of the instruction pointer register?

35. Provide an ovefliew of the fetch and the execution of an instruction by the 8088.

36. What happens to the value in IP each time the 8088 completes an insruction fetch?

Section 2.837. Make a list of the general-pur?ose data registers of the 8088.

Al8. Ho\ ie $e word value of a data resister labeled:

- - 39. Hou ire the upper and lower byres of a dala register d€noledl

40. Name two dedicated operations assigned to the CX register.

Section 2.941. Wlat kind of inforrnation is slored in the pointer and index registers?

42. Name ihe two pointer registers.43. For which segment register are the contents of the pointer registen used as an offset?

,l4. For which segment register are the contents of fhe index registen used as an offset?

45, what do Sl and DI stand for?

46. Wlat is the difference between SI and Dl?

Sect ion 2.1047. Categorize each flag bit of the 8088 as either a contol flag or a flag that monitors the

status due to execution of an insiluctlon.

48. Describe the function of each status flag.

Software Architecture of the 8088 and 8086 Microprocessors chap. Zs6

49. How does software use a status flag?50. W}lat does TF stand for?51. Which flag determines whether the adairess for a srring operation is incremented or

52. Can the state of the flags be modified rhrough so{tware?

Section 2. I I53, What is the word length ofthe 8088's physical address?54. Wlat rwo adalrcss elements are combined io form a physicat adahess?55. Calculate the value of each of the physicat addresses thar fo ows. Assume alt num,

bers are hexadecimal numbe$.(a) 1000:i234(b) 01oo:ABCD(c) A200|12CF(d) B2C0:FAI2

56. Find the unknown value for each of the following physical addresses. Assume allnumbers are hexadecimal numben.(a) A000:? : A0123(b) ?:r4DA = 23sDA(c) D765:? = DABCo(d) ?tCD2l : 32D21

5t. If ihe current values in the code segment register and rhe instrucrion pointer are0200i6 and 0lAC16. respectively, whar physical ad&ess is used in the next instrucrionfetch?

3 A data segmenr is ro be located ftom address A000016 to AFFFFT6. Wh;i vatue mustb€ loaded into DS?

3). If the data segment register contains the value found in problem 58, what value mustbe toaded into DI if it is to point ro a destinarion operand stored in memory at addressr.12346'l

Section 2. I 2aa- What is the function oi the stack?aL lf the curent vatues in the stack segmenr register and srack pointer are C000r6 and

FF00r6, respectively, what is the address of the current toD of the srack?C1 For the base and offser addresses in p.oblem 61, how many words of data are cur,

Eotly held in the s.ack?af. Show how the value EEl I r 6 ftom register AX would be pushed onto the rop of rhe

sack as it exists in Foblem 61.

Section 2.13al kr fte 8088 microprocessor are the inpu/ourput and memory addrcss spaces com,

ffi or sepamte?G- Haa lnge is the 8088's yO address space?5, E tE n3me is given ro rhe pan of ihe I/O add.ess space ftom 000016 tbrough 00IrF16?

57