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Responsibilities: Develop testbench & reference models for block-level and full-chip verification. This work involves working closely with design engineers to create constrained random based test-bench & test cases, to ensure adequate feature and code coverage, & to help resolve test failures. You will have the opportunity to help create reusable verification environments to be used across multiple projectsRequirements: Hands-on development experience with Constrained Random test-bench using System Verilog Experience in verification environment development using OVM/UVM Emulation / silicon validation experience. Knowledge of Perl, UNIX shell. Good communications skills, both verbal and writing.SoC Expertise/Domain Knowledge ARM AXI,AHB/APB protocol in-depth knowledge. ARM AXI peripheral integration and verification. Hands-on experience on SATA, Ethernet interface. Hands-on experience on Serdes is a big plus.https://outlook.com/owa/wipro.com