SOC Design Flow - National Chiao Tung Universitytwins.ee.nctu.edu.tw/.../03_SOC_Design_flow.pdf ·...

SOC Design Flow

1

Institute of Electronics,National C

hiao Tung U

niversity

Challenges of SoC Era

• Deign complexity– Validation & Verification– Design space exploration– Integration– Timing & power– Testing– Packaging

• Time to market• The cost

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hiao Tung U

niversity

From Requirement to Deliverables

CustomerNeeds

ProductDeliver

Abstract Real

System Function

HierarchyRefinemenet

HierarchyValidaton

System Function

Fab

Mask WaferLayoutLogical Netlist Logical Device

RTL

Behavioral

Architecture

Behavioral

Architecture

TestPatern

Verification

System Vaildation "Pattern"

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hiao Tung U

niversity

Five SoC Design Issues

• To manage the design complexity– Co-design– IP modeling– Timing closure– Signal Integrity– Interoperability

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hiao Tung U

niversity

How to Conquer the Complexity

• Use a known real entity– A pre-designed component (reuse)– A platform

• Partition– Based on functionality– Hardware and software

• Modeling– At different level– Consistent and accurate

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hiao Tung U

niversity

SoC Design Flow

High Level Algorithm ModelC/C++/COSSAP/VCC/MATLAB

Hardware/Software PartitionN2C/VCC

Communication RefinementN2C/Port-C/VCC

Front End

Back EndHar

dwar

eD

esig

nSy

stem

Lev

elD

esig

n

Hardware/Software CoverificationN2C/Seamless/"Q/Bridge"

Specification

Chip

Software

Design

RTOSWinCE/VxWorks

Device DriverDriveway

API EmbeddedSoftware

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hiao Tung U

niversity

Physical Design Flow

• In VDSM– Interconnect dominates delay– Timing closure– Signal integrity

• Traditional design flow– Two-step process– Physical design is performed

independently after logic design

• New design flow– Capture real technology behaviors

early in the design flow– Break the iteration between physical

design and logic design

Synthesis

P & R

FunctionalVerification

LVS/DRC

RCExtraction

TimingSimulation

High LevelDesign

FrontEnd

BackEnd

Chip

System LevelDesign

Specification

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hiao Tung U

niversity

Making Sense of Interconnect• At 0.35u, timing convergence started to become a problem.• At 0.25u, it started to significantly impact the work of the

designer.• At 0.18u, if not accounted for, it actually causes designs to fail.

1.0uSilicon Technology

Perc

enta

ge o

f Del

ay

0.5u 0.25u 0.18u

Wire

Gat

e

Source: Avant! Source: Synopsys

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hiao Tung U

niversity

Interconnect Power Consumption in DSM

• DSM effects in energy dissipation: cross-coupling capacitances

Source: Y. Zorian, S. Dey, and M. Rodgers, “Test of Future System-on-Chips,” Proceeding of the 2000 International Conference on Computer-Aided Design, 392-398

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hiao Tung U

niversity

Signal Integrity and Timing Closure• Root causes of both Signal Integrity and Timing Closure

– Inadequate interconnect modeling techniques– No effective design methodology

• Synthesis timing does not correlate with physical timing– Factors

• Coupling capacitance increases• Interconnect resistance increases• Device noise margins decrease• Higher frequencies result in on-chip inductive effects

– Problems• Signal electromigration• Antenna effects• Crosstalk delay• Crosstalk noise

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hiao Tung U

niversity

Example - Crosstalk Delay

• Net-to-net coupling capacitance dominates as a percentage of total capacitance in VDSM.

• The coupling capacitance can be multiplied by the Miller Effect– Wire capacitance can be off by 2X if the adjacent wires

are switching in the opposite direction.– The coupling capacitance can be much less than

expected if the wires are switching in the same direction

• Both have to be considered during timing analysis to fully account for setup and hold constraints.

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hiao Tung U

niversity

New Physical Design Flow Needed

• Bring physical information into the logical design

• Overview of solutions– Single pass methodology– Synthesis-driven layout– Layout-driven synthesis– All-Integrated (optimization, analysis

and layout) layout

Synthesis

P & R

FunctionalVerification

LVS/DRC

RCExtraction

TimingSimulaton

High LevelDesign

FrontEnd

BackEnd

Chip

System LevelDesign

P&R

Synthesis

BackAnnotated

Delay

Sign-offPackage

Specification

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hiao Tung U

niversity

HW/SW Cosimulation Through Emulation

• Emulation in “virtual silicon”– Complete functional simulation

of the chip at close to real time– Run real software

• Tools to enable simulation between EDAs and emulators

– Cycle-based simulators– Full-timing simulators– Instruction set simulators– E.g. Quickturn Q/Bridge

• Expensive, long learning curve and set-up time

Simulation

Acceleration

Emulation

Silic

on IP

Mod

elsVe

rific

ation

Ser

vice

s

CPS

(Cyc

le/S

econ

d

10100

1K

10K

100K

1M10M

100M

Source: IKOS Systems Inc

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hiao Tung U

niversity

Embedded Software Architecture for SoC Design

Host Application

Application Program Interface

Hardware

Device Drivers

MessageManager

MMI/GUI

Taskcontroller

ErrorHandling

StateMachine

MemoryAllocation

Diagnostics

KernelServices

StackProtocol

DisplayServices

FileManager

AlarmServices

Library

EventManager

DataI/O

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hiao Tung U

niversity

Software Development

• Porting software to a new processor and RTOS– Using a common RTOS abstraction layer

• The evolution of embedded system in the future– An standard RTOS

Application Software

Optimized API

RTOS

Microprocessor

Application Software

New RTOS

New Microprocessor

Old New

New API Needed

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hiao Tung U

niversity

Software Performance Estimation

• Have to take the following into account– Instruction set– Bus loading– Memory fetching– Register allocation

• Example: Cadence VCC technology– CPU characterized as Virtual Processor Model– Using a Virtual Machine Instruction Set– SW estimation using annotation into C-Code – Good for early system scheduling, processor load estimation

• Two orders of magnitude faster than ISS• Greater than 80% accuracy

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hiao Tung U

niversity

Tester Partitioning

Source: Y. Zorian, S. Dey, and M. Rodgers, “Test of Future System-on-Chips,” Proceeding of the 2000 International Conference on Computer-Aided Design, 392-398

Logic

PLL

Memory

Source/Sink

Source/Sink

Source/Sink

Source/Sink

Embedded TesterExternal Tester

Logic

PLL

Memory

Source/Sink

Source/Sink

Source/Sink

Embedded TesterExternal Tester

High bandwidth

Low bandwidth

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hiao Tung U

niversity

Self-Testing of Embedded Processor Cores

• Logic BIST– Based on the application of pseudo random test

patterns generated by on-chip test pattern generators like LFSRs.

– Cannot always achieve very high fault coverage for processor cores.

• Instruction-based self-test techniques– Rely on generating and applying random instruction

sequences to processor cores.– The approach determines the structural test needs of

processor components– Advantage: programmability and flexibility

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hiao Tung U

niversity

Platform-based Design

Source: “Surviving the SOC Revolution - A Guide to Platform-Based Design” by Henry Chang et al, Kluwer Academic Publishers, 1999

VCDeliveryBlock AuthoringFu

nctio

nal

Des

ign

Arc

hite

ctur

eD

esig

nIn

tegr

atio

nD

esig

nPh

ysic

alD

esig

nM

anuf

actu

ring

Link

Supp

ortin

gTe

chno

logy

Test

benc

hes

DynamicVerification

PhysicalVerification

Implementation

StaticVerification

BlockDesign Planning

BlockSpecification

Virtual SystemAnalysis

Digital & Mixed Signal

IP Portfolio Authoring GuideCellLibraries

Form

al IP

Han

doff

SWDevelopmentChip Integration

SWDevelopment

Links

Executable Specification

Test

benc

hes

DynamicVerification

PhysicalVerification

ChipImplementation

StaticVerification

IntegrationPlanning

ChipSpecification/IP Selection

SystemAnalysis

IP Portfolio IntegrationPlatform

SystemAnalysis

RTOS/ApplicationSelection

ModuleDevelopment

SWDistribution

RTOS/Applications

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hiao Tung U

niversity

Design Entry

Gate levelTruth tableFSMWaveform

RTL level

System level modeling

1K~10K

10K~100k

Manage Size and Run-Time

100K~100M

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hiao Tung U

niversity

Hardware Platform-Based Design

Platform Provider PerspectiveSystem Integrator Perspective

It is a “meet-in-the-middle” approach.

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hiao Tung U

niversity

System-Level Design

• Goal– To define the platform that satisfies the system

functions with performance/cost tradeoff• Platform design

– Bus structure– IP and their function design

– Control scheme– Data communication (bandwidth)

Customized instructionsParallelismCommand parametersConfigurable parametersIP parameters

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hiao Tung U

niversity

Control Scheme Model

Status

CommandConfiguration

Data Receive Buffer

Data Transmit Buffer

InterruptInterrupts

Status Polling (timer)

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hiao Tung U

niversity

Some Helps in System-Level Design

• Cadence VCC (Virtual Component Codesign, from Cadence Berkely Labs)– Performance simulation– Communication refinement technology

• Vast Systems Technology– VPM (Virtual Processor Model)– HW/SW codesign

• CoWare N2C (Napkin-to-chip)– Interface synthesis

• SystemC

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hiao Tung U

niversity

Cadence’s VCC

Synthesis / Place & Route etc.

HW/SW Verifier - Verification Cockpit - NC-SIMRTL Block Verification and HW-SW-Co-Verification

SPW HDS Block Implementation

Hard

ware

Deve

lopm

ent

SPW Fixed Point Algorithm Analysis

SPW Floating Point Algorithm Analysis

IP B

lock

Aut

horin

g

Softw

are

Deve

lopm

ent

SPW DSP Behavioral Specification

Block LevelSpecification

VCC HardwareAssembly

VCC SoftwareAssembly

VCC Communication SynthesisCommunication Integration

VCC Performance Analysis and Platform Configuration

VCC FunctionalSystem Integration

VCC Platform Function

VCC Platform Architecture

Full System Specification

IP B

lock

Sys

tem

Inte

grat

ion

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hiao Tung U

niversity

An Opportunity To Do It Right !

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hiao Tung U

niversity

SystemC Heritage

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hiao Tung U

niversity

SystemC Roadmap

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hiao Tung U

niversity

The Intent of Different Level of Model

• Design exploration at higher level– Import of top-level constraint and block architecture– Hierarchical, complete system refinement– Less time for validating system requirement– More design space of algorithm and system

architecture• Simple and efficient verification and simulation

– Functional verification– Timing simulation/verification– Separate internal and external (interface) verification– Analysis: power and timing

• Verification support

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hiao Tung U

niversity

SystemC

• SystemC is a modeling platform– C++ extensions to add hardware modeling constructs– a set C++ class library– simulation kernel– supports different levels of abstraction

Good Candidate for Task Level Mapping

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hiao Tung U

niversity

Level of abstraction in SystemC

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hiao Tung U

niversity

SystemC Design Flow

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hiao Tung U

niversity

Example

Source: SystemC Users Forum, DAC, June 2000

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hiao Tung U

niversity

Implementing Virtual Prototypes

• Functionality partition• Module specification• Communication refinement

IQ-IDCT

MC

IQ-IDCT

MC

FIFOFunc_B(){ ...... IDCT(); ......}

Func_A(){ ...... IQ(); ......}

IQ_IDCT(){ ...... IQ(); IDCT(); ......}

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hiao Tung U

niversity

Functionality Partition

• Separating communication and computation• Using hierarchy to group related functionality• Choosing the granularity of the basic parts

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hiao Tung U

niversity

Module Specification (1/2)

Process A

entry(){ ...... Z = func_B(X,Y); ......}

func_B(X,Y){ Z = X+Y; retuen Z;}

Process B

entry(){ ...... X.write(); Y.write(); Z.read(); ......}

Process C

entry(){ X.read(); Y.read(); Z = X+Y; Z.write();}

Z

Y

X

1. Pull out functionality into new created process

2. Replace function call with inter-process communcation.

3. Instantiate new process and define channels to connect them.

3

1

2

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hiao Tung U

niversity

Module Specification (2/2)

• Abstraction Levels – Untimed Functional Level

– Processes execute in zero time but in order

– Timed Functional Level– Bus-Cycle Accurate Level

• Transaction on bus are modeled cycle accurate

• Cycle Accurate Level– Behavior is clock cycle accurate

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hiao Tung U

niversity

Communication Refinement

KeyGuarantee consistency of communication during refinement

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hiao Tung U

niversity

Software Performance Estimation

• Have to take the following into account– Instruction set– Bus loading– Memory fetching– Register allocation

• Example: Cadence VCC technology– CPU characterized as Virtual Processor Model– Using a Virtual Machine Instruction Set– SW estimation using annotation into C-Code – Good for early system scheduling, processor load estimation

• Two orders of magnitude faster than ISS• Greater than 80% accuracy

39


hiao Tung U

niversity

Discussion: Commonality and Differentia

• Differentiae– Processor core (e.g., customized inst. set)– IP parameterized– IP add/move

• Design methodology of platform– System-level– Platform-level design methodology

• Design flow• Models• Tools (EDA venders, 3rd party or home-made)

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hiao Tung U

niversity

Summary

• Platform-based design– From board design to SoC design– From executable spec., i.e., C/C++, to SystemC

• Modeling– Performance evaluation– Task mapping– Communication refinement

SOC Design Flow - National Chiao Tung Universitytwins.ee.nctu.edu.tw/.../03_SOC_Design_flow.pdf ·...

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