Smart EQ

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Smart EQ Smart EQ Digital Stereo Digital Stereo Equalizer Equalizer Dustin Demontigny David Bull

description

Smart EQ. Digital Stereo Equalizer. Dustin Demontigny David Bull. Project Motivation. Optimize an audio signal for a specific individual Improve on existing analog equalizer systems Apply DSP techniques using VHDL. Design Goals. Develop 10 band stereo equalizer User interface and control - PowerPoint PPT Presentation

Transcript of Smart EQ

Page 1: Smart EQ

Smart EQSmart EQDigital Stereo EqualizerDigital Stereo Equalizer

Dustin DemontignyDavid Bull

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Project MotivationProject Motivation

Optimize an audio signal for a Optimize an audio signal for a specific individualspecific individual

Improve on existing analog equalizer Improve on existing analog equalizer systemssystems

Apply DSP techniques using VHDLApply DSP techniques using VHDL

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Design GoalsDesign Goals

Develop 10 band stereo equalizerDevelop 10 band stereo equalizer User interface and controlUser interface and control Minimize FPGA resources of filterMinimize FPGA resources of filter High level of resolution (20 bit audio High level of resolution (20 bit audio

samples)samples)

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Audio InterfaceAudio Interface Combines the XStend and XSA-100 boardsCombines the XStend and XSA-100 boards FPGA controls the AKM sigma delta codec on FPGA controls the AKM sigma delta codec on

XStend boardXStend board

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VHDL ModulesVHDL Modules

User interface selects User interface selects equalizer settingsequalizer settings

ROM on arithmetic ROM on arithmetic unit holds tapsunit holds taps

Handshaking between Handshaking between sectionssections

EQ interfaces to codec EQ interfaces to codec and provides filteringand provides filtering

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User InterfaceUser Interface Push buttons toggle between preset valuesPush buttons toggle between preset values Preset number displayed on LEDPreset number displayed on LED Gain value decoded from preset valueGain value decoded from preset value Simple but very small (only 3% of FPGA)Simple but very small (only 3% of FPGA)

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Arithmetic UnitArithmetic Unit

Receives gain value Receives gain value and determines the and determines the filter coefficientsfilter coefficients

Retrieves filter taps Retrieves filter taps from ROMfrom ROM

Reduces total taps by Reduces total taps by a factor of the bands a factor of the bands (in our case 10)(in our case 10)

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EqualizerEqualizer

10 bandpass FIR digital filters10 bandpass FIR digital filters Easy to ImplementEasy to Implement No stability issuesNo stability issues Linear Phase – Can add coefficients Linear Phase – Can add coefficients

for each filter to obtain one filter that for each filter to obtain one filter that performs like all the individual filtersperforms like all the individual filters

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EqualizerEqualizer

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EqualizerEqualizer

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Useful ApplicationsUseful Applications

Hearing aidsHearing aids Consumer audioConsumer audio Musical instrument amplifiersMusical instrument amplifiers Computer soundcardsComputer soundcards

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Upgrades & EnhancementsUpgrades & Enhancements

Real-time automatic mode select Real-time automatic mode select Calibration modeCalibration mode More enhanced user interfaceMore enhanced user interface Graphic display of audio spectrum Graphic display of audio spectrum

(input and output) on VGA monitor or (input and output) on VGA monitor or LCDLCD

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QuestionsQuestions