Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland...
-
date post
19-Dec-2015 -
Category
Documents
-
view
226 -
download
3
Transcript of Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland...
![Page 1: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/1.jpg)
Slides to Accompanya Video Tutorial on
Harry Porter’s Relay Computer
Harry Porter, Ph.D.Portland State University
November 7, 2007
![Page 2: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/2.jpg)
+V
![Page 3: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/3.jpg)
Double Throw Relay
![Page 4: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/4.jpg)
+V
Double Throw Relay
![Page 5: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/5.jpg)
Four Pole, Double Throw Relay
![Page 6: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/6.jpg)
+V
Four Pole, Double Throw Relay
![Page 7: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/7.jpg)
![Page 8: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/8.jpg)
Schematic Diagrams
Assume other terminalis connected to ground
![Page 9: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/9.jpg)
Schematic Diagrams
Assume other terminalis connected to ground
+V
![Page 10: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/10.jpg)
The “NOT” Circuit
in out
in
out+V
in out 0 1 1 0
0
1
Convention: “1” = +12V “0” = not connected
![Page 11: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/11.jpg)
The “NOT” Circuit
in out
in
out+V
in out 0 1 1 0
1
0
Convention: “1” = +12V “0” = not connected
![Page 12: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/12.jpg)
c
The “OR” Circuit
b b or c
+V
+V
b c OUT0 0 0 0 1 11 0 11 1 1
bc b or c
![Page 13: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/13.jpg)
An Optimization?
c
b
b or cb or cbc
![Page 14: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/14.jpg)
c
An Optimization?
b b or c
b
b or cc
c or dd
d
c or d
![Page 15: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/15.jpg)
c
An Optimization?
b b or c
b
b or cc
c or dd
d
c or d
Whoops!
![Page 16: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/16.jpg)
An Optimization?
b or c
c
b
+V
d
c or d
b b or c
c
c or dd
![Page 17: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/17.jpg)
1-Bit Logic Circuit
b
c
NOT
b c NOT AND OR XOR0 0 1 0 0 00 1 1 0 1 11 0 0 0 1 11 1 0 1 1 0
AND
OR
XOR
![Page 18: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/18.jpg)
1-Bit Logic Circuit
b
VNOT
AND
OR
XOR
c
b c NOT AND OR XOR0 0 1 0 0 00 1 1 0 1 11 0 0 0 1 11 1 0 1 1 0
![Page 19: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/19.jpg)
1-Bit Logic Circuit
b
V
c
NOT
AND
OR
XOR
b c NOT AND OR XOR0 0 1 0 0 00 1 1 0 1 11 0 0 0 1 11 1 0 1 1 0
![Page 20: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/20.jpg)
1-Bit Logic Circuit
b
V
c
NOT
AND
OR
XOR
b c NOT AND OR XOR0 0 1 0 0 00 1 1 0 1 11 0 0 0 1 11 1 0 1 1 0
![Page 21: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/21.jpg)
1-Bit Logic Circuit
b
V
c
NOT
AND
OR
XOR
b c NOT AND OR XOR0 0 1 0 0 00 1 1 0 1 11 0 0 0 1 11 1 0 1 1 0
![Page 22: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/22.jpg)
1-Bit Logic Circuit
b
V
c
NOT
AND
OR
XOR
b c NOT AND OR XOR0 0 1 0 0 00 1 1 0 1 11 0 0 0 1 11 1 0 1 1 0
![Page 23: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/23.jpg)
AND7
OR7
Eight 1-bit circuits can be combinedto build an...
8-Bit Logic Circuit
LogicCircuit
NOT7
B7 C7
• • •
XOR7
AND1
OR1
LogicCircuit
NOT1
B1 C1
XOR1
AND0
OR0
LogicCircuit
NOT0
B0 C0
XOR0
![Page 24: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/24.jpg)
The “Full Adder” Circuit
CarryinCarryout FullAdder
Sum
B CCyin B C Cyout Sum
0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1
![Page 25: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/25.jpg)
8 full-adders can be combined to build an...
8-Bit Adder
CarryFull
AdderFull
Adder
B0 C0
Sum0Sum1
B1 C1
CarryFull
Adder
Sum7
B7 C7
• • •
+B
88
8C
SumCarry
Carry0
![Page 26: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/26.jpg)
The Zero-Detect Circuit
ResultBus
Zero V+
![Page 27: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/27.jpg)
The Zero-Detect Circuit
ResultBus
Zero V+
Sign
![Page 28: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/28.jpg)
Enable Circuit
Enable
![Page 29: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/29.jpg)
Enable Circuit x7 x6 x5 x4 x3 x2 x1 x0
ResultBus
B XOR C
Enable
![Page 30: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/30.jpg)
Enable
Shift Left Circular (SHL) b7 b6 b5 b4 b3 b2 b1 b0
ResultBus
B
![Page 31: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/31.jpg)
3-to-8 Decoder
f1
Vf0
f2
INCANDORXORNOTSHL<unused>
ADD
f0 f1 f2 OUTPUT
0 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 1 0 01 1 0 0 0 0 0 0 0 1 01 1 1 0 0 0 0 0 0 0 1
![Page 32: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/32.jpg)
CarrySign
Arithmetic Logic Unit (ALU) B 8
8
8C
Data Bus
3
Zero
8-bitLogic
8-bitAdder
Enable En En En En EnEn
AN
D
OR
XO
R
NO
T
SH
L
INC
AD
D
Function
3-to-8Decoder
Zero-Detect
![Page 33: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/33.jpg)
CarrySign
An 8-Bit ALU
ALUB
8
8
8C
Result
Function Code 000 add 001 inc 010 and 011 or 100 xor 101 not 110 shl 111 <nop>
3
Zero
![Page 34: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/34.jpg)
Register Storage
+VA
![Page 35: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/35.jpg)
Register Storage
+V
• • •
A7 A0A6
![Page 36: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/36.jpg)
Register Storage
+V
Bus
• • •
Enable
A7 A0A6
Select
![Page 37: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/37.jpg)
Register Storage
A7
Select
Load A0
• • •
Enable
A6
Bus
![Page 38: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/38.jpg)
Register Storage
A7
Select
Load A0
• • •
Enable
A6
Bus
![Page 39: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/39.jpg)
8-Bit “Data” Bus
LoadSelect
LoadSelect
“X” Register “Y” Register
8-Bit Registers
![Page 40: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/40.jpg)
16-Bit “Address” Bus
8-Bit “Data” Bus
“X” Register “Y” Register
LoadSelect
LoadSelect
LoadSelect
![Page 41: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/41.jpg)
16-bitIncrement
Inst
M1
M2 M
X
Y XY
J1
J2 J
PC
Inc
8-bitALU
Memory
AddrData
Z Cy S
SystemArchitecture
8-b
it D
ata
Bu
s
A B C D
16-b
it A
dd
ress
Bu
s
![Page 42: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/42.jpg)
QuickTime™ and aTIFF (LZW) decompressor
are needed to see this picture.
32K Byte Static RAM Chip
LEDs
8 FET Power Transistors(to drive relays during
a memory-read operation)
![Page 43: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/43.jpg)
16-bitIncrement
Inst
M1
M2 M
X
Y XY
J1
J2 J
PC
Inc
8-bitALU
Memory
AddrData
Z Cy S
8-b
it D
ata
Bu
s
A B C D
16-b
it A
dd
ress
Bu
s
Example:The ALU
Instruction
![Page 44: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/44.jpg)
16-bitIncrement
Inst
M1
M2 M
X
Y XY
J1
J2 J
PC
Inc
8-bitALU
Memory
AddrData
Z Cy S
Step 1:Fetch Instruction
8-b
it D
ata
Bu
s
A B C D
MEM-READSELECT
LOAD
16-b
it A
dd
ress
Bu
s
![Page 45: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/45.jpg)
Inst
M1
M2 M
X
Y XY
J1
J2 J
PC
Inc
8-bitALU
Memory
AddrData
Z Cy S
8-b
it D
ata
Bu
s
A B C D
Step 2:Increment PC
SELECT
LOAD 16-bitIncrement
16-b
it A
dd
ress
Bu
s
![Page 46: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/46.jpg)
16-bitIncrement
Inst
M1
M2 M
X
Y XY
J1
J2 J
PC
Inc
8-bitALU
Memory
AddrData
Z Cy S
8-b
it D
ata
Bu
s
A B C D
LOAD
SELECT
Step 3:Update PC
16-b
it A
dd
ress
Bu
s
![Page 47: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/47.jpg)
16-bitIncrement
Inst
M1
M2 M
X
Y XY
J1
J2 J
PC
Inc
Memory
AddrData
Z Cy S
8-b
it D
ata
Bu
s
A
D
Step 4:Execute Instruction
FUNCTION
LOAD
LOAD
B C
8-bitALU
16-b
it A
dd
ress
Bu
s
![Page 48: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/48.jpg)
Clock
Switch
+V Output
+V
![Page 49: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/49.jpg)
Clock
Switch
+V Output
+V
Charging
![Page 50: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/50.jpg)
Clock
Switch
+V Output
+V
Discharging
![Page 51: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/51.jpg)
Clock
Switch
+V Output
+V
![Page 52: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/52.jpg)
+V +V
Clock
+V +V
A B C D
![Page 53: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/53.jpg)
+V +V
Clock
Charging
+V +VOnOn
Discharging
A B C D
![Page 54: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/54.jpg)
+V +V
Clock
Charging
+V +VOn
Discharging
On
A B C D
![Page 55: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/55.jpg)
+V +V
Clock
Charging
+V +VOn
Discharging
On
A B C D
![Page 56: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/56.jpg)
+V +V
Clock
Charging
+V +VOn
Discharging
On
A B C D
![Page 57: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/57.jpg)
+V +V
Clock
Charging
+V +VOn
Discharging
On
A B C D
![Page 58: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/58.jpg)
Clock Timing Diagram
A
B
C
D
Clock
Clock = (A and B) or (C and D)
![Page 59: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/59.jpg)
t7t5t4t3t2t1
Finite State Machine
1 2 3 4 5 6 7 8
t6 t8
Outputs
clock
![Page 60: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/60.jpg)
Output from FSA
2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 31
t1
t2
t3
t4
t5
t6
t7
t8
![Page 61: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/61.jpg)
Instruction Timing - ALU Instruction
Select PC
Memory Read
Load Instr
Load Inc
Select Inc
Load PC
ALU Function
Load A
Load Cond.Code Reg.
2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 31
![Page 62: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/62.jpg)
Instruction Timing - ALU Instruction
Select PC
Memory Read
Load Instr
Load Inc
Select Inc
Load PC
ALU Function
Load Cond.Code Reg.
2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 31
Fetch
Load A
![Page 63: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/63.jpg)
Instruction Timing - ALU Instruction
Select PC
Memory Read
Load Instr
Load Inc
Select Inc
Load PC
ALU Function
Load Cond.Code Reg.
2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 31
Increment
Load A
![Page 64: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/64.jpg)
Instruction Timing - ALU Instruction
Select PC
Memory Read
Load Instr
Load Inc
Select Inc
Load PC
ALU Function
Load Cond.Code Reg.
2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 31
Load A
Execute
![Page 65: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/65.jpg)
Instruction Decoding
Instruction RegisterFinite State Machine
Control Signals(Load, Select, Mem-Read, etc.)
CombinationalLogic
1 2 3 4 5 6 • • • 7 6 5 4 3 2 1 0
![Page 66: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/66.jpg)
1 2 3 4 5 6 7 8 9 10
Instruction Timing - 16-bit Move
Select PC
Memory Read
Load Instr
Load Inc
Select Inc
Load PC
Select Source-Register
2 3 4 5 6 7 8 11
Load Dest-Register
(Same asbefore)
![Page 67: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/67.jpg)
Finite State Machine
1 2 3 4 5 6 7
9 11 13 15 16
17 18 19 20 21 22 23
10 12 14
24
8
![Page 68: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/68.jpg)
Instruction Decoding and Control
Clock
InstructionRegister
Finite StateMachine
Control Lines
Instruction Decoding
Dat
a B
us
![Page 69: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/69.jpg)
The Instruction Set
0 0 d d d s s s
1 0 0 0 r f f f
0 1 r d d d d d
1 0 1 1 0 0 0 0
Move
ALU
Load Immediate
16-bit Increment
ddd = destination registersss = source register (A, B, C, D, M1 ,M2 ,X or Y)
r = destination register (A or D)fff = function code (add, inc, and, or, xor, not, shl)
r = destination register (A or B)ddddd = value (-16..15)
XY XY + 1
![Page 70: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/70.jpg)
The Instruction Set
1 0 0 1 0 0 r r
1 0 0 1 1 0 r r
1 1 0 0 0 0 0 0
1 0 1 0 1 1 1 0
Load
Store
Load 16-bit Immediate
Halt
rr = destination register (A, B, C, D)reg [M]
rr = source register (A, B, C, D)[M] reg
Load the immediate value into M (i.e., M1 and M2)
v v v v v v v v v v v v v v v v
![Page 71: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/71.jpg)
The Instruction Set
1 1 1 0 0 1 1 0
1 0 1 0 d s s 0
1 0 1 0 1 0 1 0
Goto
Call
16-Bit Move
Return / Branch Indirect
a a a a a a a a a a a a a a a a
Branch to the given address
1 1 1 0 0 1 1 1 a a a a a a a a a a a a a a a a
Branch to the given addressSave return location in XY register
PC XY
d = destination register (PC or XY)ss = source register (M, XY or J)
![Page 72: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/72.jpg)
The Instruction Set
1 1 1 1 0 0 0 0
Branch If Negative
Branch If Carry
Branch If Zero
Branch If Not Zero
a a a a a a a a a a a a a a a a
Branch to the given address if S = 1
1 1 1 0 1 0 0 0 a a a a a a a a a a a a a a a a
Branch to the given address if Cy = 1
Branch to the given address if Z = 1
Branch to the given address if Z = 0
1 1 1 0 0 1 0 0 a a a a a a a a a a a a a a a a
1 1 1 0 0 0 1 0 a a a a a a a a a a a a a a a a
![Page 73: Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007.](https://reader035.fdocuments.us/reader035/viewer/2022081515/56649d405503460f94a19b6a/html5/thumbnails/73.jpg)
An Example Program
address instr assembly comment 0000 0000 0011 1001 Y=B Y B 0000 0001 0011 0110 X=0 X 0 0000 0010 1000 0101 A=¬B If sign(Y)==1 0000 0011 1111 0000 BNEG Else . 0000 0100 0000 0000 . . 0000 0101 0000 0111 . . 0000 0110 0011 0010 X=C X C Else: . 0000 0111 0101 1001 A=-7 D -7 0000 1000 0001 1000 D=A . Loop: Loop: 0000 1001 0000 1110 B=X Shift X left (circular) 0000 1010 1000 0110 A=B<<1 . 0000 1011 0011 0000 X=A . 0000 1100 0000 1111 B=Y Shift Y left (circular) 0000 1101 1000 0110 A=B<<1 . 0000 1110 0011 1000 Y=A . 0000 1111 0000 1111 B=Y If sign(Y)==1 0001 0000 1000 0101 A=¬B . 0001 0001 1111 0000 BNEG Else2 . 0001 0010 0000 0000 . . 0001 0011 0001 0111 . . 0001 0100 0000 1110 B=X X X + C 0001 0101 1000 0000 A=B+C . 0001 0110 0011 0000 X=A . Else2: . 0001 0111 0000 1011 B=D D D + 1 0001 1000 1000 1001 D=B+1 . 0001 1001 1110 0010 BNZ Loop If D != 0 goto Loop 0001 1010 0000 0000 . . 0001 1011 0000 1001 . . 0001 1100 1010 1110 HALT HALT